CN104701411A - Edge insulating method used during manufacturing of silicon-based heterojunction battery piece - Google Patents
Edge insulating method used during manufacturing of silicon-based heterojunction battery piece Download PDFInfo
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- CN104701411A CN104701411A CN201310666703.3A CN201310666703A CN104701411A CN 104701411 A CN104701411 A CN 104701411A CN 201310666703 A CN201310666703 A CN 201310666703A CN 104701411 A CN104701411 A CN 104701411A
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Abstract
The invention discloses an edge insulating method used during manufacturing of a silicon-based heterojunction battery piece. The edge insulating method comprises the following steps of providing a silicon wafer of which a front surface is deposited with a P-type amorphous silicon membrane and a reverse surface is deposited with an N-type amorphous silicon membrane layer; depositing conductive transparent oxide layers on the front surface and the reverse surface of the silicon wafer; depositing a barrier layer on each conductive transparent oxide layer; depositing a seed layer on each barrier layer; plating the conductive transparent oxide layers, the barrier layers and the seed layers on the section of the periphery of the silicon wafer in a surrounding manner; wrapping each seed layer by using a light resistance material layer which wraps the section of the periphery of the silicon wafer; wrapping a part of a mask of the section of the periphery of the silicon wafer by using the light resistance material layers; performing exposure development on the front surface and the reverse surface of the silicon wafer; etching a part of light resistance material layers which wrap the section of the periphery of the silicon wafer; etching the seed layers, the barrier layers and the conductive transparent oxide layers which are plated on the section of the periphery of the silicon wafer in the surrounding manner; and etching the light resistance material layers on the front surface and the reverse surface of the silicon wafer. By the edge insulating method used during manufacturing of the silicon-based heterojunction battery piece, edges of the silicon-based heterojunction battery piece can be insulated during manufacturing of the silicon-based heterojunction battery piece.
Description
Technical field
The present invention relates to the preparing technical field of solar cell, be related specifically to a kind of method of edge insulation when making silicon based hetero-junction cell piece.
Background technology
The substrate of silicon based hetero-junction cell piece is generally based on N-type monocrystalline silicon piece, surface is by forming P-N junction as emitter with the amorphous silicon membrane deposited by PECVD method, the formation of P-N junction is between two different materials, be the monocrystalline silicon of bandwidth about 1.12eV, another kind is the amorphous silicon membrane of bandwidth about 1.72eV.Due to the difference of bandwidth, the knot that bi-material interface is formed is called heterojunction.For hetero-junction solar cell sheet, because two kinds become the larger difference of knot material bandwidth, cause the open circuit voltage of this kind of cell piece very high, usually at more than 700mV.
When amorphous silicon membrane is after the positive and negative both sides of silicon chip are formed successively, next step is the method sputtered by PVD deposits layer of transparent successively conductive oxide on positive and negative both sides.Conductive transparent oxide layer is generally high by transmitance, the ITO material of good conductivity, or the indium oxide of other element dopings.When depositing electrically conductive transparent oxide layer, easily around the short circuit being plated to silicon chip edge and causing cell piece.For avoiding around plating the cell piece caused, the normal method using silicon chip edge press box, but sacrifice effective extinction area of sensitive surface.After positive and negative both sides have deposited conductive oxide, when making metal grid lines by galvanoplastic on conductive oxide surface, first will at the method plated metal lamination of the conductive oxide same sputtering in surface, metal laminated one deck adhesive layer that comprises directly contacts with conductive oxide, with one deck Seed Layer copper, for electro-coppering uses.Adhesive layer is in fact also one deck barrier layer, and general available Ti series metal or Ta series metal are to prevent the diffusion of copper in conductive oxide.The metal laminated bonding force problem that can solve electro-coppering and conductive oxide.For avoiding edge around plating, during plated metal lamination, also need the same with during conductive oxide uses press box at silicon chip edge.
When using press box conductive oxide, cannot ensure that press box can aim at silicon chip edge, and in press box operation, the added and undercarriage of silicon chip operates and also there is certain complexity.
Summary of the invention
The object of the invention is to provide a kind of method of edge insulation when making silicon based hetero-junction cell piece, object is when being not use press box, adopts PVD sputtering method double-sided deposition conductive transparent oxide layer, barrier layer and Seed Layer around being plated to edge and making the edge shorting problem caused by double-sided metal grid line by galvanoplastic when avoiding making silicon based hetero-junction cell piece.
For this reason, the present invention is by the following technical solutions:
Make a method for edge insulation during silicon based hetero-junction cell piece, comprising:
There is provided front to deposit P-type amorphous thin Film layers, reverse side has deposited the silicon chip of N-type amorphous thin Film layers;
Depositing electrically conductive transparent oxide layer on described silicon chip tow sides;
Deposited barrier layer on described conductive transparent oxide layer;
Deposited seed layer on described barrier layer, wherein conductive transparent oxide layer, barrier layer, Seed Layer are all around the surrounding tangent plane being plated to silicon chip;
Photoresist layer in described Seed Layer outer cladding, wherein photoresist layer is coated to silicon chip surrounding tangent plane;
Photoresist layer is coated to the part mask of silicon chip surrounding tangent plane, tow sides carry out exposure imaging;
Etch away the photoresist layer of the part being coated to silicon chip surrounding tangent plane;
Etch away around the Seed Layer being plated to silicon chip surrounding tangent plane, barrier layer and conductive transparent oxide layer;
Etch away double-edged photoresist layer.
Wherein, described conductive transparent oxide layer is the indium oxide layer of ITO layer or other element that adulterates.
Wherein, described barrier layer is Ti series of metal layers or Ta series of metal layers.
Wherein, described Ti series metal is TiNx or TiW metal level; Described Ta series of metal layers is Ta or TaNx metal level.
Wherein, described Seed Layer is copper seed layer.
Wherein, described photoresist layer is photosensitive dry film.
Wherein, the photoresist layer being coated to silicon chip surrounding tangent plane described in uses developer solution etching to remove.
Wherein, described around being plated to Seed Layer, the barrier layer of silicon chip surrounding tangent plane and using acid etching solution etching to remove to conductive oxide layer.
Wherein, described double-edged photoresist layer adopts alkaline corrosion liquid etching to remove.
The present invention adopts technique scheme, adopt when not using press box, not only avoid when making silicon based hetero-junction cell piece adopts PVD sputtering method double-sided deposition conducting objects oxide layer, barrier layer and Seed Layer around being plated to edge and making the edge shorting problem caused by double-sided metal grid line by galvanoplastic, efficiently utilize again the surface deposition conductive oxide layer of silicon chip, increase light absorbing absorption area, avoid the loss of cell piece short circuit current.
Accompanying drawing explanation
Fig. 1 is the structural representation that silicon chip of the present invention is wrapped up by conductive transparent oxide layer, barrier layer, Seed Layer and photoresist layer.
Fig. 2 is the structural representation of the present invention when silicon chip tow sides photoresist layer being exposed.
Fig. 3 is the structural representation after the present invention etches away the photoresist layer of silicon chip surrounding tangent plane, Seed Layer, barrier layer and conductive transparent oxide layer.
Fig. 4 be the present invention make silicon based hetero-junction cell piece time edge insulation after structural representation.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
The invention provides a kind of method of edge insulation when making silicon based hetero-junction cell piece, mainly comprise the following steps:
The first step, front is deposited P-type amorphous thin Film layers, reverse side has deposited the silicon chip 1 of N-type amorphous thin Film layers, move to PVD chamber, at silicon chip 1 deposited on silicon conductive transparent oxide layer 2, conductive transparent oxide layer 2 adopts ITO(tin indium oxide) layer, or the indium oxide layer of other element dopings; Deposited barrier layer 3 on conductive transparent oxide layer 2, barrier layer 3 adopts Ti series metal and Ta series metal, and Ti series metal is TiNx or TiW metal level, and Ta series of metal layers is Ta or TaNx metal level; Deposited seed layer 4 on barrier layer 3, Seed Layer 4 is copper seed layer, and wherein conductive transparent oxide layer 2, barrier layer 3, Seed Layer 4 are all around the surrounding tangent plane 11 being plated to silicon chip, wherein the surrounding tangent plane 11 of silicon chip be silicon chip all around four sides tangent plane; Photoresist layer 5 on coated in Seed Layer 4, photoresist layer 5 is photosensitive dry film, and wherein photoresist layer 5 is coated to silicon chip surrounding tangent plane.As shown in Figure 1, silicon chip 1 is wrapped by conductive transparent oxide layer 2, barrier layer 3, Seed Layer 4, photoresist layer 5.
Second step, aims at the surrounding tangent plane 11 of silicon chip 1 by mask plate 7, photoresist layer 5, the UV light 6 sheltering from the surrounding tangent plane 11 being coated to silicon chip 1 only exposes the tow sides of photoresist layer 5, as shown in Figure 2.
3rd step, gets rid of the photoresist layer 5 being coated to the surrounding tangent plane 11 of silicon chip 1 without exposure with developer solution, Seed Layer 4 is exposed, after wherein chemical reaction occurs the photoresist layer 5 of exposure region, can not be developed corrosion and fall.With Seed Layer 4 erosion removal that acidic corrosion solution will expose, barrier layer 3 is exposed; Barrier layer 3 erosion removal will exposed again, makes conducting objects oxide layer 2 expose; Conducting objects oxide layer 2 erosion removal will exposed again.As shown in Figure 3.
4th step, will overlay on the double-edged photoresist layer 5 of silicon chip 1 with alkaline solution and get rid of, and complete edge insulation when making silicon based hetero-junction cell piece.As shown in Figure 4, silicon chip 1 only has positive and negative both sides to retain conductive transparent oxide layer 2 and barrier layer 3 and Seed Layer 4.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. make a method for edge insulation during silicon based hetero-junction cell piece, it is characterized in that, comprising:
There is provided front to deposit P-type amorphous thin Film layers, reverse side has deposited the silicon chip of N-type amorphous thin Film layers;
Depositing electrically conductive transparent oxide layer on described silicon chip tow sides;
Deposited barrier layer on described conductive transparent oxide layer;
Deposited seed layer on described barrier layer, wherein conductive transparent oxide layer, barrier layer, Seed Layer are all around the surrounding tangent plane being plated to silicon chip;
Photoresist layer in described Seed Layer outer cladding, wherein photoresist layer is coated to silicon chip surrounding tangent plane;
Photoresist layer is coated to the part mask of silicon chip surrounding tangent plane, tow sides carry out exposure imaging;
Etch away the photoresist layer of the part being coated to silicon chip surrounding tangent plane;
Etch away around the Seed Layer being plated to silicon chip surrounding tangent plane, barrier layer and conductive transparent oxide layer;
Etch away double-edged photoresist layer.
2. the method for edge insulation during making silicon based hetero-junction cell piece according to claim 1, it is characterized in that, described conductive transparent oxide layer is the indium oxide layer of ITO layer or other element that adulterates.
3. the method for edge insulation during making silicon based hetero-junction cell piece according to claim 1, it is characterized in that, described barrier layer is Ti series of metal layers or Ta series of metal layers.
4. the method for edge insulation during making silicon based hetero-junction cell piece according to claim 3, it is characterized in that, described Ti series metal is TiNx or TiW metal level; Described Ta series of metal layers is Ta or TaNx metal level.
5. the method for edge insulation during making silicon based hetero-junction cell piece according to claim 1, it is characterized in that, described Seed Layer is copper seed layer.
6. the method for edge insulation during making silicon based hetero-junction cell piece according to claim 1, it is characterized in that, described photoresist layer is photosensitive dry film.
7. the method for edge insulation during making silicon based hetero-junction cell piece according to claim 1, is characterized in that, described in be coated to silicon chip surrounding tangent plane photoresist layer use developer solution etching to remove.
8. the method for edge insulation during making silicon based hetero-junction cell piece according to claim 1, is characterized in that, described around being plated to Seed Layer, the barrier layer of silicon chip surrounding tangent plane and using acid etching solution etching to remove to conductive oxide layer.
9. the method for edge insulation during making silicon based hetero-junction cell piece according to claim 1, is characterized in that, described double-edged photoresist layer adopts alkaline corrosion liquid etching to remove.
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| CN201310666703.3A CN104701411A (en) | 2013-12-10 | 2013-12-10 | Edge insulating method used during manufacturing of silicon-based heterojunction battery piece |
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Cited By (8)
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| CN106356418A (en) * | 2015-07-24 | 2017-01-25 | 钧石(中国)能源有限公司 | Silicon-based heterojunction cell and preparation method of TiNx barrier layers of silicon-based heterojunction cell |
| CN107665935A (en) * | 2016-07-27 | 2018-02-06 | 福建金石能源有限公司 | A kind of edge isolation method of efficient heterojunction battery |
| CN108987528A (en) * | 2017-06-01 | 2018-12-11 | 福建金石能源有限公司 | A kind of heterojunction solar battery edge insulation method |
| CN109659393A (en) * | 2018-12-11 | 2019-04-19 | 君泰创新（北京）科技有限公司 | The preparation method of cell piece for imbrication component |
| CN111834488A (en) * | 2019-03-28 | 2020-10-27 | 福建钜能电力有限公司 | Preparation method of solar cell |
| CN114277348A (en) * | 2021-12-27 | 2022-04-05 | 晋能清洁能源科技股份公司 | Method for controlling magnetron sputtering equipment in HJT battery production |
| CN116779494A (en) * | 2023-08-18 | 2023-09-19 | 苏州晶洲装备科技有限公司 | Etching device, etching method and battery piece production equipment |
| WO2024045807A1 (en) * | 2022-08-29 | 2024-03-07 | 通威太阳能（成都）有限公司 | Solar cell and manufacturing process therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106356418A (en) * | 2015-07-24 | 2017-01-25 | 钧石(中国)能源有限公司 | Silicon-based heterojunction cell and preparation method of TiNx barrier layers of silicon-based heterojunction cell |
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| CN114277348A (en) * | 2021-12-27 | 2022-04-05 | 晋能清洁能源科技股份公司 | Method for controlling magnetron sputtering equipment in HJT battery production |
| WO2024045807A1 (en) * | 2022-08-29 | 2024-03-07 | 通威太阳能（成都）有限公司 | Solar cell and manufacturing process therefor |
| CN116779494A (en) * | 2023-08-18 | 2023-09-19 | 苏州晶洲装备科技有限公司 | Etching device, etching method and battery piece production equipment |
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Effective date of registration: 20160928 Address after: 362000, No. five, wellspring Road, Jinjiang Economic Development Zone, Quanzhou, Fujian, 17 Applicant after: Fujian Jinshi Energy Co., Ltd. Address before: 362000, Fujian Quanzhou Licheng hi tech Zone, Chang Tai Street, Sin Tong community, Jun Stone Industrial Park, building 2 Applicant before: Quanzhou City Botai Semiconductor Technology Co., Ltd. |
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Application publication date: 20150610 |
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