CN104934497A - Method for manufacturing metal laminate of silicon-based heterojunction battery slice - Google Patents
Method for manufacturing metal laminate of silicon-based heterojunction battery slice Download PDFInfo
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- CN104934497A CN104934497A CN201410100967.7A CN201410100967A CN104934497A CN 104934497 A CN104934497 A CN 104934497A CN 201410100967 A CN201410100967 A CN 201410100967A CN 104934497 A CN104934497 A CN 104934497A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a method for manufacturing a metal laminate of a silicon-based heterojunction battery slice, which comprises the steps of providing a silicon wafer on which a P-type amorphous silicon film layer is deposited on the front surface and an N-type amorphous silicon film layer is deposited on the back surface; depositing conductive oxide layers on the front surface and the back surface of the silicon wafer; depositing a combination layer on the conductive oxide layer, wherein the combination layer is a nickel-copper alloy layer; plating a photoresistive material layer on the nickel-copper alloy layer, and forming the pattern of a metal gate line after mask exposure and developing; electroplating an electroplated layer on the nickel-copper alloy layer of the pattern of the metal gate line; and etching the photoresistive material layer and the nickel-copper alloy layer which is not covered by the electroplated layer, thereby forming the metal laminate. The method of the invention aims to enlarge a combining force between the conductive oxide layer and an electroplated copper layer and prevent diffusion of the electroplated copper layer on the conductive oxide layer through depositing the nickel-copper alloy layer as a transition combination layer on the conductive oxide layer.
Description
Technical field
The present invention relates to the technical field that heterojunction solar battery manufactures, be related specifically to the manufacture method that a kind of silicon based hetero-junction cell piece is metal laminated.
Background technology
Silicon based hetero-junction cell piece is one of direction of current high performance solar batteries sheet research and development.The substrate of silicon based hetero-junction cell piece is generally based on N-type monocrystalline silicon piece, and one side is by forming P-N junction as emitter with the amorphous silicon membrane deposited by PECVD method, another side uses the amorphous silicon layer of the same type deposited in the same way as back contacts.The formation of P-N junction is between two different materials, and a kind of is the monocrystalline silicon of bandwidth about 1.12eV, and another kind is the amorphous silicon membrane of bandwidth about 1.72eV.Due to the difference of bandwidth, the knot that bi-material interface is formed is called heterojunction.For hetero-junction solar cell sheet, because two kinds become the larger difference of knot material bandwidth, this kind of cell piece is caused to possess higher open circuit voltage.By the suitable adjustment to its thin amorphous silicon layer, its open circuit voltage is easy to reach more than 700mV.
When amorphous silicon membrane is after the positive and negative both sides of silicon chip are formed successively, next step is by PVD(physical vapor deposition) method that sputters deposits the conductive oxide TCO of layer of transparent successively on positive and negative both sides.TCO is generally high by transmitance, the ITO material of good conductivity, or the indium oxide of other element dopings.After this, the metal grid lines on transparent conductive oxide is formed by traditional method for printing screen.Print the metal grid lines got on and be attached to transparent conductive oxide surface after about 200oC low-temperature sintering.Low-temperature sintering is generally difficult to the adhesion ensureing grid line and transparent conductive oxide, and when showing making components welding, main gate line easily comes off.One of feature of silicon based hetero-junction cell piece manufacture craft is low temperature process, is less than 200oC.Therefore the sintering temperature improving the silver-colored line of printing is infeasible.Form on conductive oxide surface the off-line problem that copper metal grid lines can solve grid line and conductive oxide surface by galvanoplastic.
Directly can electric plated with copper on conductive oxide surface, but itself and conductive oxide surface conjunction power are weak.Copper and conductive oxide directly contact in addition to the diffusion inside of conductive oxide, can affect battery performance.For addressing these problems, before electro-coppering, need between electro-coppering and conductive oxide layer, to deposit one deck transitional bonding layer in order to increase the adhesion between electro-coppering and conductive oxide layer.Prior art is formed metal laminated as transitional bonding layer mainly through depositing TiN x, TaNx or WNx barrier layer and copper seed layer, but its technological process is complicated, and need afterwards to adopt different chemical solution corrosion barrier layers and copper seed layer, this can cause the Performance And Reliability of battery to decline.
Summary of the invention
The object of the present invention is to provide the manufacture method that a kind of silicon based hetero-junction cell piece is metal laminated, mainly through first depositing one deck nickel-copper alloy layer as transitional bonding layer in conductive oxide layer before copper electroplating layer, in order to increase the adhesion of conductive oxide layer and copper electroplating layer, and avoid the diffusion of copper electroplating layer in conductive oxide layer.
The invention provides following technical scheme for this reason:
The manufacture method that silicon based hetero-junction cell piece is metal laminated, comprising:
There is provided front to deposit P-type amorphous thin Film layers, reverse side has deposited the silicon chip of N-type amorphous thin Film layers;
Conductive oxide layer on described silicon chip tow sides;
Deposition deposition binder course in described conductive oxide layer, wherein binder course is nickel-copper alloy layer;
Described nickel-copper alloy layer covers photoresist layer, by mask exposure, after development, forms the pattern of metal grid lines;
The albata layer of the pattern of described metal grid lines electroplates electrodeposited coating;
Etch away the photoresist layer, the nickel-copper alloy layer that cover without electrodeposited coating, formed metal laminated.
Wherein, described conductive oxide layer is ITO layer.
Wherein, in described nickel-copper alloy layer, nickel content is 10% ~ 90%, and copper content is 10% ~ 90%, and preferably, nickel content is 20% ~ 50%, and copper content is 50% ~ 80%.
Wherein, described conductive oxide layer is also included in the step of deposited seed layer on described nickel-copper alloy layer after nickel deposited copper alloy layer.
Wherein, described Seed Layer is copper seed layer.
Wherein, described photoresist layer is photosensitive dry film.
Wherein, described electrodeposited coating is copper electroplating layer.
The present invention adopts above technical scheme, adopts nickel-copper alloy layer as the transitional bonding layer of conductive oxide layer and copper electroplating layer, in order to increase the adhesion of conductive oxide layer and copper electroplating layer, and solves the diffusion problem of copper electroplating layer in conductive oxide layer.
Accompanying drawing explanation
Fig. 1 is the structural representation after deposition of amorphous silicon films layer of the present invention, conductive oxide layer, nickel-copper alloy layer.
Fig. 2 is the structural representation after exposure imaging of the present invention.
Fig. 3 is the structural representation after the present invention electroplates copper electroplating layer.
Fig. 4 is the structural representation after the present invention etches.
Embodiment
In order to make object of the present invention, feature and advantage more clear, below in conjunction with drawings and Examples, explanation is specifically made to the specific embodiment of the present invention, in the following description, set forth a lot of concrete details so that understand the present invention fully, but the present invention can implement in other modes being much different from description.Therefore, the present invention is not by the restriction of the concrete enforcement of following discloses.
The manufacture method that silicon based hetero-junction cell piece is metal laminated, key step comprises as follows: provide front to deposit P-type amorphous thin Film layers, reverse side has deposited the silicon chip of N-type amorphous thin Film layers; Conductive oxide layer on described silicon chip tow sides; Deposition deposition binder course in described conductive oxide layer, wherein binder course is nickel-copper alloy layer; Described nickel-copper alloy layer covers photoresist layer, by mask exposure, after development, forms the pattern of metal grid lines; The albata layer of the pattern of described metal grid lines electroplates electrodeposited coating; Etch away the photoresist layer, the nickel-copper alloy layer that cover without electrodeposited coating, formed metal laminated.
Specific embodiment is as follows:
S1, as shown in Figure 1 and Figure 2, provides front to deposit P-type amorphous thin Film layers 2, the silicon chip 1 of reverse side deposition N-type amorphous thin Film layers 3; Pass through PVD sputtering method more respectively at P-type amorphous thin Film layers 2, conductive oxide layer 4 on reverse side deposition N-type amorphous thin Film layers 3, conductive oxide layer 4 adopts ITO layer; Deposition deposition binder course 5 in conductive oxide layer 4 again, wherein binder course 5 is nickel-copper alloy layer; Wherein in nickel-copper alloy layer, nickel content is 10% ~ 90%, and copper content is 10% ~ 90%, and preferably, nickel content is 20% ~ 50%, and copper content is 50% ~ 80%; Nickel-copper alloy layer is covered one deck photoresist layer 7, and wherein photoresist layer 7 is photosensitive dry film; Then photoresist layer 7 is through mask exposure, forms the pattern 8 of metal grid lines after development.Preferably, in conductive oxide layer 4 after nickel deposited copper alloy layer, deposited seed layer 6 on nickel-copper alloy layer, then carry out mask exposure after being covered with photoresist layer 7, development, wherein Seed Layer is copper seed layer.
S2, as shown in Figure 3, Figure 4, adopt electroplating technology to electroplate electrodeposited coating 9 at the pattern 8 of metal grid lines, wherein electrodeposited coating 9 is layers of copper; The photoresist layer 7 of mask is got rid of, then gets rid of the nickel-copper alloy layer 5 covered without electrodeposited coating 9 with chemical corrosion liquid, expose conductive oxide layer 4, formed metal laminated.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. the manufacture method that silicon based hetero-junction cell piece is metal laminated, is characterized in that, comprising:
There is provided front to deposit P-type amorphous thin Film layers, reverse side has deposited the silicon chip of N-type amorphous thin Film layers;
Conductive oxide layer on described silicon chip tow sides;
Described conductive oxide layer deposits binder course, and wherein binder course is nickel-copper alloy layer;
Described nickel-copper alloy layer covers photoresist layer, by mask exposure, after development, forms the pattern of metal grid lines;
The albata layer of the pattern of described metal grid lines electroplates electrodeposited coating;
Etch away the photoresist layer, the nickel-copper alloy layer that cover without electrodeposited coating, formed metal laminated.
2. the manufacture method that a kind of silicon based hetero-junction cell piece according to claim 1 is metal laminated, is characterized in that: described conductive oxide layer is ITO layer.
3. the manufacture method that a kind of silicon based hetero-junction cell piece according to claim 1 is metal laminated, it is characterized in that: in described nickel-copper alloy layer, nickel content is 10% ~ 90%, copper content is 10% ~ 90%, preferably, nickel content is 20% ~ 50%, and copper content is 50% ~ 80%.
4. the manufacture method that a kind of silicon based hetero-junction cell piece according to claim 1 is metal laminated, is characterized in that: the step being also included in deposited seed layer on described nickel-copper alloy layer in described conductive oxide layer after nickel deposited copper alloy layer.
5. the manufacture method that a kind of silicon based hetero-junction cell piece according to claim 4 is metal laminated, is characterized in that: described Seed Layer is copper seed layer.
6. the manufacture method that a kind of silicon based hetero-junction cell piece according to claim 1 is metal laminated, is characterized in that: described photoresist layer is photosensitive dry film.
7. the manufacture method that a kind of silicon based hetero-junction cell piece according to claim 1 is metal laminated, is characterized in that: described electrodeposited coating is copper electroplating layer.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106653935A (en) * | 2015-11-02 | 2017-05-10 | 钧石(中国)能源有限公司 | Tin layer protecting method in preparation of metal grid line of solar cell |
| CN108123010A (en) * | 2016-11-29 | 2018-06-05 | 茂迪股份有限公司 | Solar cell and method for manufacturing same |
| CN110176504A (en) * | 2018-02-20 | 2019-08-27 | 弗劳恩霍夫应用研究促进协会 | The method of parts metals |
| CN113035972A (en) * | 2021-02-04 | 2021-06-25 | 苏州元昱新能源有限公司 | Heterojunction photovoltaic cell of grid line electrode made of silver-free slurry |
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| CN102064210A (en) * | 2010-11-11 | 2011-05-18 | 陈哲艮 | Silicon-based double-junction solar cell with homojunction and heterojunction and preparation method thereof |
| US20120060911A1 (en) * | 2010-09-10 | 2012-03-15 | Sierra Solar Power, Inc. | Solar cell with electroplated metal grid |
| CN103107212A (en) * | 2013-02-01 | 2013-05-15 | 中国科学院上海微系统与信息技术研究所 | Heterojunction solar battery with electroplate electrodes and preparation method |
| CN103137791A (en) * | 2013-03-13 | 2013-06-05 | 中国科学院上海微系统与信息技术研究所 | Preparing heterojunction solar cell method of combining wet process deposition with low temperature heat treatment |
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2014
- 2014-03-19 CN CN201410100967.7A patent/CN104934497A/en active Pending
Patent Citations (4)
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| US20120060911A1 (en) * | 2010-09-10 | 2012-03-15 | Sierra Solar Power, Inc. | Solar cell with electroplated metal grid |
| CN102064210A (en) * | 2010-11-11 | 2011-05-18 | 陈哲艮 | Silicon-based double-junction solar cell with homojunction and heterojunction and preparation method thereof |
| CN103107212A (en) * | 2013-02-01 | 2013-05-15 | 中国科学院上海微系统与信息技术研究所 | Heterojunction solar battery with electroplate electrodes and preparation method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653935A (en) * | 2015-11-02 | 2017-05-10 | 钧石(中国)能源有限公司 | Tin layer protecting method in preparation of metal grid line of solar cell |
| CN106653935B (en) * | 2015-11-02 | 2019-02-19 | 钧石(中国)能源有限公司 | A kind of guard method preparing tin layers in solar battery metal grid lines |
| CN108123010A (en) * | 2016-11-29 | 2018-06-05 | 茂迪股份有限公司 | Solar cell and method for manufacturing same |
| CN110176504A (en) * | 2018-02-20 | 2019-08-27 | 弗劳恩霍夫应用研究促进协会 | The method of parts metals |
| CN113035972A (en) * | 2021-02-04 | 2021-06-25 | 苏州元昱新能源有限公司 | Heterojunction photovoltaic cell of grid line electrode made of silver-free slurry |
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Application publication date: 20150923 |