CN109659393A - The preparation method of cell piece for imbrication component - Google Patents
The preparation method of cell piece for imbrication component Download PDFInfo
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- CN109659393A CN109659393A CN201811511239.XA CN201811511239A CN109659393A CN 109659393 A CN109659393 A CN 109659393A CN 201811511239 A CN201811511239 A CN 201811511239A CN 109659393 A CN109659393 A CN 109659393A
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- silicon wafer
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- cell piece
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- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 197
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 197
- 239000010703 silicon Substances 0.000 claims abstract description 197
- 238000000151 deposition Methods 0.000 claims abstract description 97
- 230000008021 deposition Effects 0.000 claims abstract description 95
- 238000005520 cutting process Methods 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 230000007246 mechanism Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 29
- 235000008216 herbs Nutrition 0.000 claims description 16
- 210000002268 wool Anatomy 0.000 claims description 16
- 238000004140 cleaning Methods 0.000 claims description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 79
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 20
- 230000008569 process Effects 0.000 description 15
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 14
- 239000011259 mixed solution Substances 0.000 description 14
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- 230000000694 effects Effects 0.000 description 10
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 8
- 229910000085 borane Inorganic materials 0.000 description 8
- UORVGPXVDQYIDP-UHFFFAOYSA-N trihydridoboron Substances B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 description 8
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 7
- 239000000908 ammonium hydroxide Substances 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 239000012634 fragment Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000013081 microcrystal Substances 0.000 description 4
- 229910017604 nitric acid Inorganic materials 0.000 description 4
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 4
- 239000012495 reaction gas Substances 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/043—Mechanically stacked PV cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1876—Particular processes or apparatus for batch treatment of the devices
- H01L31/188—Apparatus specially adapted for automatic interconnection of solar cells in a module
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
This application discloses a kind of preparation methods of cell piece for imbrication component, comprising: by preset mask plate and silk-screen halftone, prepares photovoltaic cell chips in the deposition region of silicon wafer；Wherein, the mask plate and the silk-screen halftone are reserved with the barrier mechanism for forming region to be cut in the silicon wafer respectively；The cutting region of the silicon wafer is cut, the cell piece for imbrication component is prepared.The embodiment of the present application passes through mask plate and silk-screen halftone in the deposition region deposition film of silicon wafer and production electrode, and reserve region to be cut, cutting region can be treated to be cut, to obtain the cell piece of no PN junction damage, the film source of high quality is provided for imbrication component, and then improves the efficiency of imbrication component.
Description
Technical field
This application involves technical field of photovoltaic modules, particularly relate to a kind of preparation side of cell piece for imbrication component
Method.
Background technique
Imbrication technology is to be overlapped series connection using conducting resinl after conventional batteries piece is cut to multiple small pieces.Existing market
On imbrication component used in cell piece be usually by bad cell piece, non-defective unit cell piece after being laser-cut into small pieces, carry out
It encapsulates.But due to bad cell piece there are unfilled corners, chipping the defects of, using bad cell piece as imbrication component
Source, greatly limit the promotion of component efficiency；And using non-defective unit cell piece as the source of imbrication component, although
The raising of component efficiency can be brought, but in laser cutting process, easily causes the damage of cell piece PN junction, causes to generate not
Good silicon wafer, this also limits the promotion of component efficiency to a certain extent.Therefore, cutting is carried out to cell piece and be easy to cause PN junction
Damage, and bad can be generated simultaneously, a large amount of cell piece can be expended.
The a solution used in the prior art is to carry out precut processing to silicon wafer before cutting silicon wafer, generally
Including following two method:
1) precut processing (depth of cut is 20-50 μm) is carried out to silicon wafer first, then by silicon wafer be put into the gaily decorated basket into
Row making herbs into wool, cleaning and rear process processing, then silicon wafer is carried out to break piece.But it due to first being precut to silicon wafer, cuts
When cut point generate stress damage to chain effect caused by subsequent operations, eventually lead to silicon wafer and waited in making herbs into wool, cleaning
The problems such as will cause fragment, crack in journey.
2) silicon wafer is put into the gaily decorated basket first and carries out making herbs into wool, cleaning and rear process processing, pre-cut then is carried out to silicon wafer
Processing (depth of cut is 20-50 μm) is cut, then silicon wafer is carried out to break piece.Although this method can ask to avoid fragment, crack etc.
Topic, but due to precuting produced in process of production after cleaning process, before plasma enhanced chemical vapor deposition
Fecula dirt, oils lipoid material, metal impurities etc. can pollute silicon wafer, the final quality for influencing cell piece.
Summary of the invention
In view of this, the purpose of the application is to propose a kind of preparation method of cell piece for imbrication component, with solution
Certainly PN junction damages, the low-quality technical problem of cell piece.
The embodiment of the present application provides a kind of preparation method of cell piece for imbrication component, comprising the following steps:
By preset mask plate and silk-screen halftone, photovoltaic cell chips are prepared in the deposition region of silicon wafer；Wherein, described
Mask plate and the silk-screen halftone are reserved with the barrier mechanism for forming region to be cut in the silicon wafer respectively；
The cutting region of the silicon wafer is cut, the cell piece for imbrication component is prepared.
It is described by preset mask plate and silk-screen halftone in some embodiments of the present application, in the crystallizing field of silicon wafer
Domain prepares photovoltaic cell chips, comprising:
By the first mask plate silicon wafer deposition region deposition intrinsic layer, p-type doped layer and n-type doping layer；
Pass through deposition region deposition of transparent conductive film of second mask plate in the p-type doped layer and n-type doping layer；
Electrode is made by deposition region of the silk-screen halftone in the transparent conductive film, obtains the photovoltaic cell core
Piece.
In some embodiments of the present application, the mask plate includes chassis body and at least one exposure mask glazing bar, described
At least one exposure mask glazing bar is the barrier mechanism, the both ends of the exposure mask glazing bar opposite sides with the chassis body respectively
Connection, the exposure mask glazing bar are the region to be cut in the orthographic projection of the silicon wafer；The exposure mask glazing bar and the frame master
Orthographic projection of the white space between white space and the adjacent exposure mask glazing bar on the silicon wafer between body is described
Deposition region.
In some embodiments of the present application, first mask plate and second mask plate are the same mask plate.
In some embodiments of the present application, the length of the white space of second mask plate is less than first exposure mask
The length of the white space of plate, the width of the white space of second mask plate are less than the white space of first mask plate
Width；Orthographic projection of the exposure mask glazing bar of second mask plate on the silicon wafer falls in the exposure mask glazing bar with the first mask plate in institute
It states in the orthographic projection on silicon wafer.
In some embodiments of the present application, the chassis body of second mask plate includes plane framework and inclined-plane frame
Frame, the plane framework are located at the outside of the inclined-plane frame, and are fixedly connected with the edge of the inclined-plane frame；The plane
The angle of plane is 60 °~75 ° where plane where frame and the inclined-plane frame.
In some embodiments of the present application, the silk-screen halftone includes halftone main body and at least one halftone glazing bar, institute
The both ends for stating halftone glazing bar are connect with the opposite sides of the halftone main body respectively, the halftone glazing bar on the silicon wafer just
It projects identical as orthographic projection of the exposure mask glazing bar on the silicon wafer.
In some embodiments of the present application, electricity is made by deposition region of the silk-screen halftone in the transparent conductive film
Pole obtains the photovoltaic cell chips, comprising:
By silk-screen halftone and conductive silver paste, silk-screen main gate line and secondary grid line in the transparent conductive film, and dry shape
At electrode.
In some embodiments of the present application, mixed by the first mask plate in the deposition region deposition intrinsic layer of silicon wafer, p-type
Diamicton and n-type doping layer, comprising:
Deposition region deposition intrinsic layer by the first mask plate on two surfaces of silicon wafer；
P-type doping is carried out in the deposition region on a surface of the silicon wafer, forms p-type doped layer；
N-type doping is carried out in the deposition region on another surface of the silicon wafer, forms n-type doping layer；
Wherein, the intrinsic layer is intrinsic amorphous silicon film layer；The p-type doped layer is p-type film layer；The n-type doping
Layer is N-type film layer.
In some embodiments of the present application, passing through preset mask plate and silk-screen halftone, in the deposition region of silicon wafer
Before preparing photovoltaic cell chips, the method also includes:
Making herbs into wool and cleaning are carried out to silicon wafer；And/or
Label is performed etching to the silicon wafer.
The embodiment of the present application by preset mask plate and silk-screen halftone silicon wafer deposition region deposition film and silk-screen
Grid line, and region to be cut is reserved, cutting region can be treated and cut, so that the cell piece of no PN junction damage is obtained,
The film source of high quality is provided for imbrication component, and then improves the efficiency of imbrication component.Moreover, the method is using laser after passivation
On the one hand the mode of cutting may insure that cell piece is damaged without PN junction, be conducive to improve product yield；It on the other hand can be to avoid
The stress damage that cut point generates when cutting is to chain effect caused by subsequent operations, to solve silicon wafer in making herbs into wool, cleaning
It will cause the problem of fragment, crack etc. Deng during.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the flow chart of the preparation method of the cell piece for imbrication component of the embodiment of the present application；
Fig. 2 is first mask plate of the application one embodiment or the main view of the second mask plate；
Fig. 3 is the first mask plate of the application further embodiment or the main view of the second mask plate
Fig. 4 is the main view of second mask plate of the application one embodiment；
Fig. 5 is the rearview of second mask plate of the application one embodiment；
Fig. 6 is the main view of the second mask plate of another embodiment of the application；
Fig. 7 is the rearview of the second mask plate of another embodiment of the application；
Fig. 8 is the main view of the silk-screen halftone of the application one embodiment；
Fig. 9 is the main view of the silk-screen halftone of another embodiment of the application.
Specific embodiment
In order to make those skilled in the art more fully understand application scheme, below in conjunction in the embodiment of the present application
Attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is only
The embodiment of the application a part, instead of all the embodiments.Based on the embodiment in the application, ordinary skill people
Member's every other embodiment obtained without making creative work, all should belong to the model of the application protection
It encloses.
It should be noted that the description and claims of this application and term " first " in above-mentioned attached drawing, "
Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way
Data be interchangeable under appropriate circumstances, so as to embodiments herein described herein can in addition to illustrating herein or
Sequence other than those of description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that cover
Cover it is non-exclusive include, for example, the process, method, system, product or equipment for containing a series of steps or units are not necessarily limited to
Step or unit those of is clearly listed, but may include be not clearly listed or for these process, methods, product
Or other step or units that equipment is intrinsic.
The embodiment of the present application provides a kind of preparation method of cell piece for imbrication component, comprising: by preset
Mask plate and silk-screen halftone prepare photovoltaic cell chips in the deposition region of silicon wafer；Wherein, the mask plate and the silk printing screen
Version is reserved with the barrier mechanism for forming region to be cut in the silicon wafer respectively；The region to be cut of the silicon wafer is carried out
Cutting, is prepared the cell piece for imbrication component.
Wherein, various structures can be used in photovoltaic cell chips prepared by the deposition region of silicon wafer, for example, with intrinsic silicon
Hetero-junctions (HIT) structure or HIT of thin layer improve structure, are not specifically limited herein.
The embodiment of the present application prepares photovoltaic cell core in the deposition region of silicon wafer by preset mask plate and silk-screen halftone
Piece, the effect due to presetting mask plate and silk-screen halftone can reserve region to be cut in silicon wafer, be cut along region to be cut
It cuts, the cell piece of no PN junction damage can be obtained, provide the film source of high quality for imbrication component, and then improve the effect of imbrication component
Rate.
In one embodiment of the application, as shown in Figure 1, the preparation method of the cell piece for imbrication component includes following
Step:
Step 101, making herbs into wool and cleaning are carried out to silicon wafer；
Step 102, by the first mask plate silicon wafer deposition region deposition intrinsic layer, p-type doped layer and n-type doping
Layer；
Step 103, the deposition region deposition by the second mask plate in the p-type doped layer and n-type doping layer is transparent
Conductive film；
Step 104, the deposition region by silk-screen halftone in the transparent conductive film makes electrode, obtains photovoltaic cell
Chip；
Step 105, along the region to be cut of the silicon wafer, the silicon wafer is cut, is prepared for imbrication
The cell piece of component.
In embodiments herein, mixed first by mask plate in the deposition region deposition intrinsic layer of silicon chip surface, p-type
Diamicton and n-type doping layer then in the further deposition of transparent conductive film in deposition region, and make electrode in deposition region, finally
It is cut along the region to be cut of silicon chip surface.As it can be seen that method provided by the embodiments of the present application, is preparing imbrication component institute
It needs to reserve region to be cut during cell piece, to avoid cell piece is damaged in cutting process, is conducive to improve product
Yield and battery efficiency, to be conducive to the promotion of efficient imbrication component efficiency.
In one embodiment of the application, as illustrated in figs. 2-7, mask plate includes chassis body 1 and at least one exposure mask lattice
Item 2, at least one exposure mask glazing bar 2 be the barrier mechanism, the both ends of the exposure mask glazing bar 2 respectively with the chassis body
1 opposite sides connection, orthographic projection of the white space of the mask plate on silicon wafer are the deposition region of silicon wafer.Wherein, institute
The white space for stating mask plate includes: white space between the exposure mask glazing bar 2 and the chassis body 1 and adjacent described
White space between exposure mask glazing bar 2.Orthographic projection of the exposure mask glazing bar 2 on the silicon wafer is the region to be cut.
Above-mentioned steps 101- step 105 is described in detail below:
In one embodiment of the application, in a step 101, first to silicon wafer carry out making herbs into wool, then to making herbs into wool after
Silicon wafer is cleaned.Making herbs into wool advantageously reduces the reflectivity of light, improves short circuit current, so that improving photoelectric conversion efficiency.It is optional
Ground, the step 101 may include: that silicon wafer is put into the mixed solution containing ammonium hydroxide and hydrogen peroxide to carry out prerinse；By institute
It states silicon wafer and is put into lye and polished；The silicon wafer is put into the mixed solution containing lye and additive and carries out making herbs into wool；
The silicon wafer is cleaned using hydrochloric acid, hydrogen peroxide, nitric acid, hydrofluoric acid and ammonium hydroxide, or is passed through the ultrapure of ozone using
Water cleans the silicon wafer.The embodiment of the present application by prerinse, silicon chip surface is dirty and mechanical damage layer for polishing removal,
Then the processes such as making herbs into wool, cleaning are successively carried out again.
Optionally, the silicon wafer is cleaned using hydrochloric acid, hydrogen peroxide, nitric acid, hydrofluoric acid and ammonium hydroxide, comprising: by institute
It states silicon wafer and is put into the mixed solution containing hydrochloric acid and hydrogen peroxide and cleaned；The silicon wafer is put into containing hydrofluoric acid and nitric acid
Mixed solution in cleaned；The silicon wafer is put into the mixed solution containing ammonium hydroxide and hydrogen peroxide and is cleaned；By institute
It states silicon wafer and is put into the mixed solution containing hydrofluoric acid and hydrochloric acid and cleaned.Optionally, during cleaning, contain described
It is passed through ozone in the mixed solution for having hydrochloric acid and hydrogen peroxide, is passed through in the mixed solution containing ammonium hydroxide and hydrogen peroxide smelly
Oxygen, to improve cleaning effect.
In one embodiment of the application, before step 101, the method can also include: to carve to silicon wafer
Erosion label.It is alternatively possible to perform etching label to silicon wafer using laser, thus the silicon wafer surface markers number and
Positive and negative etc..Wherein, the depth of the label can be 20~40 μm.In practical application, the silicon of 100~250 μm of thickness can use
Piece (its size can be 125 × 125mm, 156.75 × 156.75mm or 158 × 158mm etc.), using laser to silicon wafer
Wherein a horizontal edge of one side performs etching label, in the surface markers lot number of the silicon wafer, number etc., in order to distinguish silicon
Two surfaces of piece.
In one embodiment of the application, as shown in Fig. 2, first mask plate includes chassis body 1 and at least one
Root exposure mask glazing bar 2, the both ends of the exposure mask glazing bar 2 are connect with the opposite sides of the chassis body 1 respectively, the exposure mask glazing bar
The white space between white space or the adjacent exposure mask glazing bar 2 between 2 and the chassis body 1 is in the silicon wafer
Orthographic projection on surface is the deposition region, and orthographic projection of the exposure mask glazing bar 2 on the silicon chip surface is region to be cut.
It should be pointed out that after mask plate is placed on silicon wafer, can be divided on silicon wafer due to the presence of exposure mask glazing bar 2
Deposition region and region to be cut out.
In one embodiment of the application, in a step 102, the first mask plate is placed on the silicon wafer, and is passed through
Deposition region deposition intrinsic layer, p-type doped layer and n-type doping of the plasma enhanced chemical vapor deposition in the silicon chip surface
Layer.It, can since the first mask plate being placed on silicon wafer before deposition intrinsic layer, p-type doped layer and n-type doping layer
Accurately to carry out the deposition of intrinsic layer, p-type doped layer and n-type doping layer in the deposition region of the silicon wafer, while making silicon wafer
Region to be cut (i.e. orthographic projection of the exposure mask glazing bar 2 on silicon wafer) without deposition operation, in order to which subsequent step is described
Region to be cut carries out cutting silicon wafer.
In one embodiment of the application, the first mask plate can be aluminum material, 1~3 ㎜ of thickness.First mask plate
The quantity of middle exposure mask glazing bar 2 can be n, so that silicon wafer to be equably divided into the figure of n+1 homalographic.
In one embodiment of the application, as shown in Fig. 2, location hole 3 is also provided in the exposure mask main body 1, it is described
The diameter of location hole 3 be 1~3mm, the center of the location hole 3 with the internal edge of the exposure mask main body 1 at a distance from be 1~
2mm.It should be pointed out that location hole 3 can also be located on four angles of exposure mask main body 1, for example, equity is located at exposure mask main body
On 1 four angles, the design of location hole 3 can be depending on support plate actual conditions.In actual use, it is contemplated that the reality of production
Effect property, therefore mask plate can be the intergrant of multiple single mask plates, in order to make multiple cell pieces simultaneously.
Silicon wafer is put on support plate and (has groove body on support plate, silicon wafer is placed in groove body) before deposition, can be designed on support plate
Then the pin of some protrusions is put down mask plate on silicon wafer gently, mask plate is fallen on pin by location hole 3 thereon
It is fixed.It, can be by mask plate exposure mask on silicon wafer every time before deposition.
In one embodiment of the application, the quadrangle of mask plate can be right angle, as shown in Fig. 2, it is also possible to chamfering,
As shown in Figure 3.For draw-type silicon wafer, preferably exposure mask can be carried out by chamfering mask plate, as shown in Figure 3；For ingot mould silicon wafer,
Preferably exposure mask can be carried out by right angle mask plate, as shown in Figure 2.
In one embodiment of the application, intrinsic layer, p-type doped layer and n-type doping layer are respectively as follows: intrinsic amorphous silicon film
Layer, p-type film layer and N-type film layer.
In one embodiment of the application, mixed by the first mask plate in the deposition region deposition intrinsic layer of silicon wafer, p-type
Diamicton and n-type doping layer, comprising: the deposition region deposition intrinsic layer by the first mask plate on two surfaces of silicon wafer；Institute
The surface for stating the intrinsic layer on a surface of silicon wafer carries out p-type doping, forms p-type doped layer；In another table of the silicon wafer
The surface of the intrinsic layer in face carries out n-type doping, forms n-type doping layer.Wherein, p-type doped layer can for P-type non-crystalline silicon film layer or
P-type microcrystal silicon film layer；N-type doping layer can be N-type amorphous silicon film layer or N-type microcrystal silicon film layer.
In one embodiment of the application, p-type doping can be carried out in the front of the silicon wafer, in the anti-of the silicon wafer
Face carries out n-type doping；N-type doping can also be carried out in the front of the silicon wafer, carry out p-type doping in the reverse side of the silicon wafer,
The embodiment of the present application to this with no restriction.P-type doping can be first carried out, then carries out n-type doping；N-type doping can also be first carried out,
Carry out p-type doping again, the embodiment of the present application to this with no restriction.
Since the region to be cut of silicon chip surface is not deposited, the region to be cut along the silicon wafer into
When row silicon wafer is cut, PN junction will not be damaged.
Wherein, PN junction refers to: different doping process is used, by diffusion, by P-type semiconductor (i.e. p-type film
Layer) it is produced on same block semiconductor (usually silicon or germanium) substrate with N-type semiconductor (i.e. N-type film layer), in their friendship
The space-charge region that interface is formed is PN junction.
It, can be using chemical deposition come deposition intrinsic layer, p-type doped layer and N in one embodiment of the application
Type doped layer, such as common plasma reinforced chemical vapour deposition (Plasma Enhanced Chemical Vapor
Deposition, PECVD) and hot-wire chemical gas-phase deposition etc..
In the deposition intrinsic layer the step of, generally using the silane of diluted in hydrogen as presoma, depositing temperature 180 DEG C~240
DEG C, tens pa of deposition pressure is to several hundred pas, and in plasma system, electronics reacts with reaction gas, so that reaction gas
Body decomposes, and forms ion and active group, these ions and active group deposit on carrier silicon chip surface, and are constantly occurring
Reaction, is finally respectively formed intrinsic layer in the front and back sides of silicon wafer.
In doping step, P can be carried out to a surface of the silicon wafer using borine or trimethyl borine as doped source
Type doping；Using phosphine as doped source, n-type doping is carried out to a surface of the silicon wafer.Specifically, use and deposition intrinsic
Layer similar plasma system is completed, and is often borine or trimethyl borine with doped source gas to p-type doped layer, and to N-type
Doping then does doped source with phosphine, usually can be all diluted with a large amount of hydrogen in these doped source gases.
In one embodiment of the application, in step 103, by the second mask plate in the p-type doped layer and N-type
Deposition region deposition of transparent conductive film on doped layer, to collect the photo-generated carrier generated in silicon wafer.Further, transparent to lead
Electrolemma is also used as antireflective film, to reduce or eliminate the reflected light of element optical surface, to increase the light transmission capacity of element.Wherein,
White space on second mask plate is in the deposition region that the orthographic projection on p-type doped layer surface is in p-type doped layer；Second covers
White space on diaphragm plate is in the deposition region that the orthographic projection on n-type doping layer surface is in n-type doping layer.
It is alternatively possible to pass through physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) for electrically conducting transparent
Oxide (TCO) deposits to the deposition region of the silicon wafer, to form transparent conductive film in silicon chip surface.
Optionally, the first mask plate used in the second mask plate and step 102 used in the step 103 can phase
Together, as shown in Figure 2,3.In practical application, the first mask plate and the second mask plate can be the same mask plate.
Optionally, it in order to realize better deposition effect, avoids occurring in plating phenomenon, the step 102 and step 103
Different mask plates can be used and carry out exposure mask, specific difference may be embodied in the size of mask plate.First mask plate and second
The structure of mask plate is similar but size is different.The length of the white space of second mask plate can be less than first exposure mask
The length of the white space of plate, the width of the white space of second mask plate can be less than the blank of first mask plate
The width in region.The exposure mask glazing bar that orthographic projection of the exposure mask glazing bar of second mask plate on the silicon wafer falls in the first mask plate exists
In orthographic projection on the silicon wafer.
As shown in Figure 2,3, second mask plate includes chassis body 1 and at least one exposure mask glazing bar 2, the exposure mask lattice
The both ends of item 2 are connect with the opposite sides of the chassis body 1 respectively, between the exposure mask glazing bar 2 and the chassis body 1
Orthographic projection of the white space on the silicon wafer between white space or the adjacent exposure mask glazing bar 2 is the crystallizing field
Domain.
Optionally, the second mask plate can be aluminum material, 1~3 ㎜ of thickness.The number of exposure mask glazing bar 2 in second mask plate
Amount can be n, so that silicon wafer to be equably divided into the figure of n+1 homalographic.
As shown in Fig. 2, being also provided with location hole 3 in the exposure mask main body 1 of the second mask plate, the diameter of the location hole 3 is 1
~3mm is 2~5mm at a distance from the internal edge of the exposure mask main body 1 at the center and the second mask plate of the location hole 3.In step
The length of the white space of second mask plate, width used in 103 are less than the length of silicon wafer, width, in this way, can be with
Prevent from occurring to cause around plating in PVD deposition transparent conductive film the p-type film layer and the conducting of N-type film layer on two surfaces of silicon wafer,
It is inefficent so as to cause cell piece or efficiency is relatively low.
It should be pointed out that the position of location hole 3 is also possible to the four of the exposure mask main body 1 positioned at the second mask plate of equity
On a angle (design of location hole 3 can be depending on support plate actual conditions).In actual use, it is contemplated that the actual effect of production
Property, therefore mask plate can be the intergrant of multiple single mask plates, in order to make multiple cell pieces simultaneously.
Optionally, the structure of second mask plate can also be different from the structure of the first mask plate.As shown in figs. 4-7,
The chassis body 1 of second mask plate includes plane framework 12 and inclined-plane frame 11, wherein the plane framework 12 and inclined-plane frame
11 are located at two different planes, i.e., between 11 place plane of 12 place plane of plane framework and inclined-plane frame at an angle
Angle, so that deposition of transparent conductive film on the silicon wafer contacted with mask plate internal edges.The plane framework 12 is located at the inclined-plane
The outside of frame 11, and be fixedly connected with the edge of the inclined-plane frame 11；Wherein, the 12 place plane of plane framework and tiltedly
The angle of 11 place plane of surface frame frame is 60 °~75 °.If 11 place plane of 12 place plane of plane framework and inclined-plane frame
Angle is too large or too small, will lead to the silicon wafer contacted with mask plate internal edges and occurs not having the phenomenon that transparent conductive film, finally
It is relatively low to will lead to cell piece efficiency.Therefore, the angle of 12 place plane of plane framework and 11 place plane of inclined-plane frame is designed
It is 60 °~75 °, it is ensured that transparent conductive film is all deposited in the deposition region of silicon wafer, to guarantee to obtain efficient battery
Piece.
It is understood that similar with step 102, the quadrangle of the second mask plate used in step 103 can be right angle,
As shown in 4,5, it is also possible to chamfering, as shown in Figure 6,7.For draw-type silicon wafer, preferably exposure mask can be carried out by chamfering mask plate,
As shown in Figure 6,7；For ingot mould silicon wafer, preferably exposure mask can be carried out by right angle mask plate, as shown in Figure 4,5.
At step 104, first the second mask plate used in step 103 is taken off from the silicon wafer, then by silk
Printed network version is placed on the silicon wafer that deposited transparent conductive film, then the deposition region production using conductive silver paste on nesa coating
Electrode.Since the region to be cut not to silicon wafer makes electrode, the use cost of silver paste can be saved.Wherein, silk printing screen
The orthographic projection of the white space of version on nesa coating is the deposition region in transparent conductive film.
As shown in figure 8, the silk-screen halftone includes halftone main body 4 and at least one halftone glazing bar 5, the halftone glazing bar 5
Both ends connect respectively with the opposite sides of the halftone main body 4, orthographic projection and institute of the halftone glazing bar 5 on the silicon wafer
State that orthographic projection of the exposure mask glazing bar 2 on the silicon wafer is identical, to avoid in the silk-screen grid line in region to be cut of the silicon wafer.
Specifically, can be by silk-screen halftone and conductive silver paste, silk-screen main gate line and secondary grid line on nesa coating, and
Drying forms electrode.The main gate line and secondary grid line are used to collected current, while main gate line also collects the electric current of secondary grid line.
For the design of silk-screen halftone, reasonable halftone master can be designed according to mask plate and silicon wafer size dimension
Body 4, as shown in Figure 8, Figure 9, the halftone main body 4 include halftone main grid 41 and halftone pair grid 42, and wherein halftone main grid 41 can be with
It is designed as no main grid, six main grids, five main grids, four main grids etc..Wherein, silk-screen halftone shown in Fig. 8 is suitable for ingot mould silicon wafer, figure
Silk-screen halftone shown in 9 is suitable for draw-type silicon wafer.
In step 105, first silk-screen halftone used in step 104 is taken off from the silicon wafer, then along institute
The region to be cut for stating silicon wafer, cuts the silicon wafer, so that the cell piece for imbrication component be prepared.
Optionally, the placement location for adjusting silicon wafer makes laser alignment region to be cut (i.e. without film layer), and along described
The region to be cut of silicon wafer, is cut by laser the silicon wafer, is imbrication component to obtain the cell piece of no PN junction damage
The film source of high quality is provided, and then improves the efficiency of imbrication component.
As it can be seen that silk printing screen needed for mask plate needed for the special deposition procedures of the embodiment of the present application and silkscreen process
Version by special mask plate and silk-screen halftone in the deposition region deposition film of silicon wafer and production electrode, and reserves to be cut
Region is cut, can be cut along region to be cut, to obtain the cell piece of no PN junction damage, provides height for imbrication component
The film source of quality, and then improve the efficiency of imbrication component.
Moreover, on the one hand may insure that cell piece is damaged without PN junction by the way of the method is cut by laser after passivation,
Be conducive to improve product yield；On the other hand, since silicon wafer is because silicon wafer itself is than relatively thin, toughness is very low, and multiple-contact is easily made
Fragmentate, the embodiment of the present application does not precut silicon wafer, and last in process is directly cut, can to avoid cutting when
The stress damage that cut point generates is to chain effect caused by subsequent operations, to solve silicon wafer in processes such as making herbs into wool, cleanings
In will cause the problem of fragment, crack etc..
It should be noted that the size in above-described embodiment is only schematical, in the actual production process, size is big
Rootlet according to actual process determine, the embodiment of the present application to this with no restriction.
Below by taking a specific embodiment as an example, embodiments herein is described in detail:
Step 1), in this step, take 100~250 μm of thickness silicon wafer (its size can be 125 × 125mm,
156.75 × 156.75mm or 158 × 158mm etc.), label is performed etching using a horizontal edge of the laser to silicon wafer, in institute
Front, the reverse side of surface markers lot number, number of silicon wafer etc. and silicon wafer are stated, in order to distinguish two surfaces of silicon wafer.Its
In, the depth of the label is 20~40 μm.
Step 2) carries out making herbs into wool and cleaning to silicon wafer, specifically includes:
A), inserted sheet: will be in the silicon wafer insertion gaily decorated basket after laser ablation；
B), silicon wafer prerinse: is put into 5~10min in 50~90 DEG C of the mixed solution containing ammonium hydroxide and hydrogen peroxide；
C), wash: the silicon wafer being put into room temperature sink and is cleaned；
D), polish: the silicon wafer is put into 1~5min in 60~90 DEG C of lye；
E), the silicon wafer making herbs into wool: is put into 5~20min in 60~90 DEG C of the mixed solution containing lye and additive；
Wherein, the additive can be TK81；
F), wash: the silicon wafer being put into room temperature sink and is cleaned；
G), the silicon wafer is put into the mixed solution containing hydrochloric acid and hydrogen peroxide and is cleaned；The silicon wafer is put into
It is cleaned in mixed solution containing hydrofluoric acid and nitric acid；The silicon wafer is put into the mixed solution containing ammonium hydroxide and hydrogen peroxide
In cleaned；The silicon wafer is put into the mixed solution containing hydrofluoric acid and hydrochloric acid and is cleaned.
Step 3), PECVD process: mask plate is placed on the silicon wafer, and heavy by plasma enhanced chemical vapor
Long-pending two surface deposition intrinsic layers in the silicon wafer, to form deposition region and area to be cut on the surface of the silicon wafer
Domain；P-type doping is carried out in the deposition region on a surface of the silicon wafer, so that it is non-to form p-type in the deposition region on the surface
Crystal silicon film layer or p-type microcrystal silicon film layer；N-type doping is carried out in the deposition region on another surface of the silicon wafer, thus at this
The deposition region on surface forms N-type amorphous silicon film layer or N-type microcrystal silicon film layer.In the deposition intrinsic layer the step of, generally with hydrogen
The diluted silane of gas be presoma, 180 DEG C~240 DEG C of depositing temperature, tens pa of deposition pressure to several hundred pas, in plasma system
In system, electronics reacts with reaction gas, so that reaction gas decomposes, forms ion and active group, these ions and work
Property group deposits on carrier silicon chip surface, and constantly reacts, and is finally respectively formed intrinsic layer in the front and back sides of silicon wafer.
In doping step, P can be carried out to a surface of the silicon wafer using borine or trimethyl borine as doped source
Type doping；Using phosphine as doped source, n-type doping is carried out to a surface of the silicon wafer.Specifically, use and deposition intrinsic
Layer similar plasma system is completed, and is often borine or trimethyl borine with doped source gas to p-type doped layer, and to N-type
Doping then does doped source with phosphine, usually can be all diluted with a large amount of hydrogen in these doped source gases.
Step 4), PVD process: mask plate is placed on the silicon wafer, and TCO is deposited to the silicon wafer by PVD
The deposition region on two surfaces, to form transparent conductive film in silicon chip surface.
Silk-screen halftone is placed on the silicon wafer by step 5), then uses conductive silver paste in the transparent conductive film of the silicon wafer
Upper silk-screen main gate line and secondary grid line.
Step 6), IV test (VA characteristic curve test): the electric property of cell piece of the test after above-mentioned steps；
Step 7), laser dicing: if electric property meets the requirements, it is directed at region to be cut, and along the silicon wafer
Region to be cut, the silicon wafer is cut by laser.
Step 8), sorted and packaged: arranging the cell piece after cutting and pack, using spare as imbrication component.
It can be seen that the embodiment of the present application passes through mask plate and silk-screen halftone in the deposition region deposition film and system of silicon wafer
Make electrode, and reserve region to be cut, can be cut along region to be cut, to obtain the battery of no PN junction damage
Piece provides the film source of high quality for imbrication component, and then improves the efficiency of imbrication component.Moreover, after the method is using passivation
On the one hand the mode of laser cutting may insure that cell piece is damaged without PN junction, be conducive to improve product yield；It on the other hand can be with
Avoid cutting when cut point generate stress damage to chain effect caused by subsequent operations, thus solve silicon wafer making herbs into wool,
It will cause the problem of fragment, crack etc. during cleaning etc..
It should be understood by those ordinary skilled in the art that: the discussion of any of the above embodiment is exemplary only, not
It is intended to imply that the scope of the present disclosure (including claim) is limited to these examples；Under the thinking of the application, above embodiments
Or it can also be combined between the technical characteristic in different embodiments, and there are the different aspects of the application as described above
Many other variations, in order to it is concise they do not provided in details.Therefore, within the spirit and principles of this application,
Any omission, modification, equivalent replacement, improvement for being made etc., should be included within the scope of protection of this application.
Claims (10)
1. a kind of preparation method of the cell piece for imbrication component, which comprises the following steps:
By preset mask plate and silk-screen halftone, photovoltaic cell chips are prepared in the deposition region of silicon wafer；Wherein, the exposure mask
Plate and the silk-screen halftone are reserved with the barrier mechanism for forming region to be cut in the silicon wafer respectively；
The cutting region of the silicon wafer is cut, the cell piece for imbrication component is prepared.
2. the preparation method of the cell piece according to claim 1 for imbrication component, which is characterized in that described by pre-
If mask plate and silk-screen halftone, prepare photovoltaic cell chips in the deposition region of silicon wafer, comprising:
By the first mask plate silicon wafer deposition region deposition intrinsic layer, p-type doped layer and n-type doping layer；
Pass through deposition region deposition of transparent conductive film of second mask plate in the p-type doped layer and n-type doping layer；
Electrode is made by deposition region of the silk-screen halftone in the transparent conductive film, obtains the photovoltaic cell core
Piece.
3. the preparation method of the cell piece according to claim 2 for imbrication component, which is characterized in that the mask plate
Including chassis body and at least one exposure mask glazing bar, at least one exposure mask glazing bar is the barrier mechanism, the exposure mask lattice
The both ends of item are connect with the opposite sides of the chassis body respectively, and the exposure mask glazing bar is described in the orthographic projection of the silicon wafer
Region to be cut；Between white space and the adjacent exposure mask glazing bar between the exposure mask glazing bar and the chassis body
Orthographic projection of the white space on the silicon wafer is the deposition region.
4. the preparation method of the cell piece according to claim 3 for imbrication component, which is characterized in that described first covers
Diaphragm plate and second mask plate are the same mask plate.
5. the preparation method of the cell piece according to claim 3 for imbrication component, which is characterized in that described second covers
The length of the white space of diaphragm plate is less than the length of the white space of first mask plate, the blank area of second mask plate
The width in domain is less than the width of the white space of first mask plate；The exposure mask glazing bar of second mask plate is on the silicon wafer
Orthographic projection falls in the exposure mask glazing bar with the first mask plate in the orthographic projection on the silicon wafer.
6. the preparation method of the cell piece according to claim 3 for imbrication component, which is characterized in that described second covers
The chassis body of diaphragm plate includes plane framework and inclined-plane frame, and the plane framework is located at the outside of the inclined-plane frame, and with
The edge of the inclined-plane frame is fixedly connected；The angle of plane and plane where the inclined-plane frame is where the plane framework
60 °~75 °.
7. the preparation method of the cell piece according to claim 3 for imbrication component, which is characterized in that the silk printing screen
Version includes halftone main body and at least one halftone glazing bar, and the both ends of the halftone glazing bar are respectively with the halftone main body with respect to two
Side connection, the halftone glazing bar is in orthographic projection phase of the orthographic projection with the exposure mask glazing bar on the silicon wafer on the silicon wafer
Together.
8. the preparation method of the cell piece according to claim 2 for imbrication component, which is characterized in that pass through silk printing screen
Deposition region of the version in the transparent conductive film makes electrode, obtains the photovoltaic cell chips, comprising:
By silk-screen halftone and conductive silver paste, silk-screen main gate line and secondary grid line in the transparent conductive film, and dry and to form electricity
Pole.
9. the preparation method of the cell piece according to claim 2 for imbrication component, which is characterized in that covered by first
Deposition region deposition intrinsic layer, p-type doped layer and n-type doping layer of the diaphragm plate in silicon wafer, comprising:
Deposition region deposition intrinsic layer by the first mask plate on two surfaces of silicon wafer；
P-type doping is carried out in the deposition region on a surface of the silicon wafer, forms p-type doped layer；
N-type doping is carried out in the deposition region on another surface of the silicon wafer, forms n-type doping layer；
Wherein, the intrinsic layer is intrinsic amorphous silicon film layer；The p-type doped layer is p-type film layer；The n-type doping layer is N
Type film layer.
10. the preparation method of the cell piece according to claim 1 for imbrication component, which is characterized in that by pre-
If mask plate and silk-screen halftone, before the deposition region of silicon wafer prepares photovoltaic cell chips, the method also includes:
Making herbs into wool and cleaning are carried out to silicon wafer；And/or
Label is performed etching to the silicon wafer.
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