CN115101412A - Preparation method of TVS chip - Google Patents
Preparation method of TVS chip Download PDFInfo
- Publication number
- CN115101412A CN115101412A CN202210878959.XA CN202210878959A CN115101412A CN 115101412 A CN115101412 A CN 115101412A CN 202210878959 A CN202210878959 A CN 202210878959A CN 115101412 A CN115101412 A CN 115101412A
- Authority
- CN
- China
- Prior art keywords
- silicon wafer
- cleaning
- tvs chip
- tvs
- shallow trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- 238000004140 cleaning Methods 0.000 claims abstract description 22
- 238000001514 detection method Methods 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 238000012360 testing method Methods 0.000 claims abstract description 5
- 238000004506 ultrasonic cleaning Methods 0.000 claims abstract description 5
- 230000009471 action Effects 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 238000000576 coating method Methods 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 239000007788 liquid Substances 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000009740 moulding (composite fabrication) Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000005554 pickling Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 230000007797 corrosion Effects 0.000 abstract description 6
- 238000005260 corrosion Methods 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 230000001052 transient effect Effects 0.000 description 5
- 230000001629 suppression Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66113—Avalanche diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
The invention provides a preparation method of a TVS chip, and relates to the technical field of TVS chips. The preparation method of the TVS chip comprises the following steps of S1, using an ultrasonic cleaning device, primarily cleaning a silicon wafer under the action of a cleaning solution, oxidizing the silicon wafer after cleaning to form an oxidation film, S2, coating photoresist on the silicon wafer after being processed by S1, photoetching the silicon wafer by utilizing photoetching equipment to form a required ditching area, S3, placing the silicon wafer after being processed by S2 into a corrosive solution to form a shallow trench, primarily detecting the shallow trench by utilizing detection equipment, S4, placing the silicon wafer after being qualified by S3 into the cleaning solution to remove the photoresist on the surface of the silicon wafer, adding the detection step after corrosion, and simultaneously mutually matching with the subsequent test steps, thereby ensuring the integrity of the corrosion result, reducing the reject ratio of production, reducing the production cost and ensuring the normal function of the TVS chip.
Description
Technical Field
The invention relates to the technical field of TVS chips, in particular to a preparation method of a TVS chip.
Background
The TVS diode, also known as a transient suppression diode, is a commonly used novel high-efficiency circuit protection device, has extremely fast response time (subnanosecond level) and quite high surge absorption capacity, and is used for transient high-voltage suppression protection in cooperation with components such as resistors, capacitors and the like. When the two ends of the TVS are subjected to transient high-energy impact, the TVS can change the impedance value between the two ends from high impedance to low impedance at a very high speed so as to absorb a transient large current and clamp the voltage between the two ends of the TVS at a preset value, thereby protecting the following circuit elements from the impact of transient high-voltage spike pulse. The circuit is widely applied to various protective electronic circuits, and has wide market prospect and larger development space.
In the prior art, the subsequent procedures are generally directly carried out after the silicon chip is corroded, so that incomplete corrosion results are easily generated, the integrity of a node layer is influenced, the reject ratio of chip production is increased, and the production cost is increased.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects of the prior art, the invention provides a preparation method of a TVS chip, which solves the problems that incomplete corrosion results are easy to occur, the integrity of a node layer is influenced, the reject ratio of chip production is increased, and the production cost is increased.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme: a preparation method of a TVS chip comprises the following steps:
s1, using an ultrasonic cleaning device to primarily clean the silicon wafer under the action of cleaning liquid, and oxidizing the silicon wafer after cleaning to form an oxide film;
s2, coating photoresist on the silicon wafer processed in the S1, and photoetching the silicon wafer by utilizing photoetching equipment to form a required ditching area;
s3, putting the silicon wafer processed in the step S2 into corrosive liquid to form a shallow trench, and performing primary detection on the shallow trench by using detection equipment;
s4, putting the qualified silicon wafer of S3 into cleaning liquid, and removing the photoresist on the surface of the silicon wafer;
s5, putting the silicon wafer processed in the step S4 into a pickling tank, removing an oxide film on the surface of the silicon wafer, and cleaning and drying the silicon wafer;
s6, attaching a diffusion source on the surface of the silicon wafer processed in the S5 to form a junction layer;
s7, passivating, surface metalizing, cutting, testing and forming the TVS chip.
Preferably, in the step S1, the silicon wafer is immersed in the cleaning solution for 3 to 8min, then ultrasonically cleaned for 3 to 5min, and then dried after cleaning.
Preferably, in the step S3, the etching time is 5-7min, and a shallow trench with a depth of 20-30um is formed.
Preferably, in S6, the diffusion source is a liquid source of boron or phosphorus, and a junction layer with a depth of 50-65um is formed.
(III) advantageous effects
The invention provides a preparation method of a TVS chip. The method has the following beneficial effects:
compared with the prior art, the method has the advantages that the detection step after corrosion is added, and meanwhile, the detection step is matched with the subsequent test step, so that on one hand, the integrity of the corrosion result is ensured, the reject ratio of production is reduced, the production cost is reduced, and on the other hand, the normal function of the TVS chip is ensured.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example (b):
the embodiment of the invention provides a preparation method of a TVS chip, which comprises the following steps:
s1, using an ultrasonic cleaning device to primarily clean the silicon wafer under the action of cleaning liquid, and oxidizing the silicon wafer after cleaning to form an oxide film;
s2, coating photoresist on the silicon wafer processed in the S1, and photoetching the silicon wafer by utilizing photoetching equipment to form a required ditching area;
s3, putting the silicon wafer processed in the step S2 into corrosive liquid to form a shallow trench, and performing primary detection on the shallow trench by using detection equipment;
s4, putting the qualified silicon wafer of S3 into cleaning liquid, and removing the photoresist on the surface of the silicon wafer;
s5, putting the silicon wafer processed in the step S4 into a pickling tank, removing an oxide film on the surface of the silicon wafer, and cleaning and drying the silicon wafer;
s6, attaching a diffusion source on the surface of the silicon wafer processed in the S5 to form a junction layer;
s7, passivating, surface metalizing, cutting, testing and forming the TVS chip.
In S1, the silicon wafer is immersed in the cleaning solution for 3-8min, then cleaned by ultrasonic wave for 3-5min, and dried after cleaning.
In S3, the etching time is 5-7min, and a shallow trench with a depth of 20-30um is formed.
In S6, the diffusion source is a liquid source of boron or phosphorus, and a junction layer with a depth of 50-65um is formed.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. A preparation method of a TVS chip is characterized by comprising the following steps:
s1, using an ultrasonic cleaning device to primarily clean the silicon wafer under the action of cleaning liquid, and oxidizing the silicon wafer after cleaning to form an oxide film;
s2, coating photoresist on the silicon wafer processed in the S1, and photoetching the silicon wafer by utilizing photoetching equipment to form a required ditching area;
s3, putting the silicon wafer processed in the step S2 into corrosive liquid to form a shallow trench, and performing primary detection on the shallow trench by using detection equipment;
s4, putting the qualified silicon wafer of S3 into cleaning liquid, and removing the photoresist on the surface of the silicon wafer;
s5, putting the silicon wafer processed in the step S4 into a pickling tank, removing an oxide film on the surface of the silicon wafer, and cleaning and drying the silicon wafer;
s6, attaching a diffusion source on the surface of the silicon wafer processed in the S5 to form a junction layer;
s7, passivating, surface metalizing, cutting, testing and forming the TVS chip.
2. The method for preparing a TVS chip as claimed in claim 1, wherein: in the step S1, the silicon wafer is immersed in the cleaning solution for 3-8min, then ultrasonic cleaning is carried out for 3-5min, and the silicon wafer is dried after cleaning.
3. The method for preparing a TVS chip according to claim 1, wherein: in the step S3, the etching time is 5-7min, and a shallow trench with the depth of 20-30um is formed.
4. The method for preparing a TVS chip as claimed in claim 1, wherein: in S6, the diffusion source is a liquid source of boron or phosphorus, and a junction layer with a depth of 50-65um is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210878959.XA CN115101412A (en) | 2022-07-25 | 2022-07-25 | Preparation method of TVS chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210878959.XA CN115101412A (en) | 2022-07-25 | 2022-07-25 | Preparation method of TVS chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115101412A true CN115101412A (en) | 2022-09-23 |
Family
ID=83299460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210878959.XA Pending CN115101412A (en) | 2022-07-25 | 2022-07-25 | Preparation method of TVS chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115101412A (en) |
-
2022
- 2022-07-25 CN CN202210878959.XA patent/CN115101412A/en active Pending
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