CN103594474A - 半导体存储器器件及其制造方法 - Google Patents

半导体存储器器件及其制造方法 Download PDF

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CN103594474A
CN103594474A CN201310043672.6A CN201310043672A CN103594474A CN 103594474 A CN103594474 A CN 103594474A CN 201310043672 A CN201310043672 A CN 201310043672A CN 103594474 A CN103594474 A CN 103594474A
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groove
layer
semiconductor substrate
hard mask
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李闰敬
安正烈
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

提供了一种半导体存储器器件及其制造方法。所述器件包括：半导体衬底，其中交替限定了有源区和隔离区，且在与所述有源区和所述隔离区相交的方向上限定了支持区；第一沟槽，形成在所述隔离区中；第二沟槽，形成在所述有源区和所述隔离区中的第一沟槽之下；以及支持层，形成在所述支持区中的第一沟槽之下。

Description

半导体存储器器件及其制造方法
相关申请的交叉引用
本申请要求2012年8月16日向韩国知识产权局提交的申请号为10-2012-0089578的韩国专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本发明的示例实施例涉及一种半导体存储器器件及其制造方法。更具体而言，本发明的示例性实施例涉及一种半导体存储器器件的隔离区。
背景技术
半导体存储器器件可以包括多个有源区和多个隔离区。
存储器单元或晶体管可以形成在半导体衬底的有源区之上，而被配置成将有源区彼此电隔离的沟槽可以形成在半导体衬底的隔离区中。可以利用绝缘材料来填充沟槽，或者可以在沟槽内形成气隙。
同时，随着半导体存储器器件的集成度的增加，有源区和隔离区的宽度和节距趋于减少。因而，即使在半导体衬底的隔离区中形成了沟槽，在有源区之间也可能出现漏电流。
例如，在NAND快闪存储器器件中，多个存储器单元可以连接到每个字线，通过器件隔离区限定的隔离层可以形成在形成了存储器单元的半导体衬底的有源区之间。在编程操作中，待编程的存储器单元和不要编程的存储器单元可以连接到被供给了编程电压的选中的字线。由于编程允许电压（例如，约0V）被供给到每个待编程存储器单元的沟道，由于沟道和字线之间的电压差电子可以从沟道隧穿至浮栅，使得相应的存储器单元被编程。相反，通过将编程禁止电压（例如，电源电压）供给到每个不要编程的存储器单元的沟道，沟道的电势可以由于沟道升压而变得高于编程禁止电压。由此，由于沟道和字线之间的电势差变得非常低，电子没有隧穿至相应存储器单元的浮栅。
然而，当形成了不要编程的存储器单元的有源区和形成了待编程的存储器单元的有源区之间出现漏电流时，可以减少形成了不要编程的存储器单元的有源区的沟道电势。结果，在沟道和字线之间的电势差增加，使得不要编程的存储器单元也被编程。执行不期望的操作可以被称作干扰。具体而言，在单个存储器单元可以被编程为多个状态的多电平单元中，由于在不同状态中的阈值电压分布之间的电压差非常小，所以当出现干扰时可靠性迅速下降。
发明内容
本发明的示例性实施例涉及一种半导体存储器器件及其制造方法，其可以防止被隔离区隔离的有源区之间的漏电流。
本发明一个方面的实施例提供一种半导体存储器器件，包括：半导体衬底，其中交替限定了有源区和隔离区，且在与所述有源区和所述隔离区相交的方向上限定了支持区；第一沟槽，形成在所述隔离区中；第二沟槽，形成在所述有源区和所述隔离区中的第一沟槽之下；以及支持层，形成在所述支持区中的第一沟槽之下。
本发明另一个方面的实施例提供一种制造半导体存储器器件的方法，所述方法包括：通过将离子注入到半导体衬底中来形成沟道区，在所述半导体衬底中限定了有源区和隔离区，且在与所述有源区和所述隔离区相交的方向上限定了支持区；在所述隔离区中形成第一沟槽；以及，在不包括所述支持区的所述有源区和所述隔离区中的第一沟槽下形成第二沟槽。
附图说明
通过参考附图详细描述示例性实施例，本发明的上述和其他特点和优势对本领域技术人员而言将变得更加明显，其中：
图1是示出半导体衬底中的出现的漏电流的透视图；
图2A至2J是示出制造根据本发明第一示例性实施例的半导体存储器器件的方法的透视图；
图3A是根据本发明第一示例性实施例的半导体存储器器件的横截面视图；
图3B是根据本发明第二示例性实施例的半导体存储器器件的横截面视图；以及
图3C是根据本发明第三示例性实施例的半导体存储器器件的横截面视图。
具体实施方式
此后将参考附图更详细描述本发明，在附图中示出了本发明的示例性实施例。然而，本发明可以以其他形式实施，且不应被解释为限于这里描述的实施例。相反，提供这些示例性实施例使得本公开内容是透彻的并且可以完全、充分地将本发明的范围提供给本领域技术人员。应易于理解到，在本公开中的“上”和“之上”的意义应该被解释为最广的方式，使得“上”不仅表示直接在某物上而且还包括存在中间特征物或层而在某物上的情况，而“之上”不仅表示直接在某物之上而且还包括不存在中间特征物或层而在某物之上的情况（即，直接在某物上）。在本说明书中，“连接”表示一个部件直接耦接到另一个部件。另外，除非在句子中有明确提及，单数形式也可以包括复数形式。
图1是示出半导体衬底中的出现的漏电流的透视图。
参见图1，在NAND快闪存储器器件中，掺杂沟道区CH可以形成在限定了有源区ACT的半导体衬底110中，而隔离沟槽TC可以形成限定了隔离区ISO的半导体衬底110中。沟槽TC可以被形成为具有比沟道区CH更深的深度，使得形成在不同有源区ACT中的沟道区CH可以彼此电隔离。如果有源区ACT和隔离区ISO设置在一个方向上，则漏极选择区DSL、字线区WL和源极选择区SSL可以被限定在半导体衬底110上并被布置在与所述一个方向交叉的方向上。尽管图1中没有示出，但是漏极选择晶体管可以形成在半导体衬底101的漏极选择区DSL上，多个字线可以形成在半导体衬底110的字线区WL上，且源极选择晶体管可以形成在半导体衬底110的源极选择区SSL上。在每个漏极选择区DSL中的沟道区CH可以通过沟槽CT而彼此隔离，字线区WL的沟道区CH可以通过沟槽TC而彼此隔离，且源极选择区SSL的沟道区CH可以通过沟槽TC而彼此隔离。然而，由于在半导体衬底110附近的沟槽TC的下部通过半导体衬底110电连接到沟道区CH的下部，在半导体存储器器件的操作期间电子EL可以通过设置在相邻沟道区CH之下的半导体衬底110来输运，由此造成了漏电流。
因而，在本发明的示例性实施例中，为了切断可能出现漏电流的电子EL的输运路径，可以在沟槽TC之下进一步形成灯泡形沟槽。具体来说，可以通过重叠灯泡形沟槽来防止沟道区CH之下的电子EL的输运。现在将描述具体制造方法和结构。
图2A至2J是示出制造根据本发明第一示例性实施例的半导体存储器器件的方法的透视图。
参见图2A，可以使用离子注入将沟道区CH形成在半导体衬底210中。第一硬掩模212可以形成在具有沟道区CH的半导体衬底210上。具体而言，第一硬掩模图案212可以形成在半导体衬底210的有源区ACT上，以形成半导体衬底210的隔离区ISO中的第一沟槽。即，第一硬掩模图案212可以包括被配置成暴露半导体衬底210的隔离区ISO的图案。可以通过使用氧化物层、氮化物层或导电层、或者通过层叠其中的至少两层来形成第一硬掩模图案212。
参见图2B，可以使用第一刻蚀工艺在隔离区ISO中形成第一沟槽T1。可以使用干法刻蚀工艺来执行第一刻蚀工艺。为了形成基本与半导体衬底210垂直的第一沟槽T1，可以使用各向异性干法刻蚀工艺来执行第一刻蚀工艺。另外，可以执行第一刻蚀工艺，使得第一沟槽T1具有比沟道区CH的深度更大的深度H1。
参见图2C，可以沿着具有第一沟槽T1的整个结构的表面形成第二硬掩模层214。可以通过使用氧化物层、氮化物层或导电层、或者通过层叠其中的至少两层来形成第二硬掩模层214。
参见图2D，在具有第二硬掩模层214的整个结构中，第三硬掩模图案216可以形成在被限定成支持半导体衬底210的沟道区CH的支持区SP中。具体来说，第三硬掩模图案216可以形成在支持区SP与隔离区ISO重叠的部分区域中。第三硬掩模图案216可以由与第二硬掩模层214具有不同的刻蚀选择性的材料形成。
在第三硬掩模图案216形成在支持区SP中的第二硬掩模层214上之后，可以使用第二刻蚀工艺从半导体衬底210的除了支持区SP之外的隔离区ISO的平坦表面去除第二硬掩模层214。由此，第二硬掩模层214可以变成第二硬掩模图案214a。可以执行第二刻蚀工艺，使得第二硬掩模层214保留在隔离区ISO的内侧壁上以及在支持区SP中。为此，可以使用各向异性干法刻蚀工艺来执行第二刻蚀工艺。
参见图2E，在去除第三硬掩模图案216后，可以使用剩余的第二硬掩模图案214a作为刻蚀掩模来执行第三干法刻蚀工艺。可以使用各向同性干法刻蚀工艺来执行第三刻蚀工艺，以在第一沟槽T1的底表面上形成具有灯泡形的第二沟槽T2。具体来说，可以执行第三刻蚀工艺，使得具有灯泡形的第二沟槽T2的中相邻沟槽彼此重叠。即，可以执行第三刻蚀工艺来连接第二沟槽T2。然而，由于第二硬掩模图案214a保留在支持区SP中，第二沟槽T2在支持区SP中可以没有彼此连接。即，在支持区SP中，由于没有形成第二沟槽T2而半导体衬底210保留，保留在支持区SP中的半导体衬底210可以起到支持层PP的作用，所述支持层PP能够支持包括被第一沟槽T1分割的沟道区CH的半导体衬底210。因而，当支持层SP具有极小的宽度时，在第三刻蚀工艺期间形成的第二沟槽T2可以彼此连接，所以没有形成支持层PP。由此，被形成为限定图2D中的支持区SP的第三硬掩模图案216可以形成地足够宽而没有连接第二沟槽T2。
参见图2F，可以利用隔离层218来填充第一沟槽T1和第二沟槽T2。具体来说，可以形成隔离层218以填充第一沟槽T1和第二沟槽T2，并完全覆盖第一硬掩模图案212。例如，可以使用氧化物层或可流动绝缘材料来形成隔离层218。如果隔离层218由可流动绝缘材料形成，则可流动绝缘材料可以是旋涂玻璃（SOG）。另外，气隙可以由在第二沟槽T2内具有较低台阶覆盖特性的绝缘材料形成或形成在第一沟槽T1和第二沟槽T2内。
参见图2G，可以使用平坦化工艺例如化学机械抛光（CMP）工艺去除在隔离层218的第一硬掩模图案212之上的上部部分。可以执行平坦化工艺直到第一硬掩模图案212和第二硬掩模图案214a被暴露出来。
参见图2H，可以去除形成在沟道区CH上的第一硬掩模图案212和第二硬掩模图案214a，以暴露第二硬掩模图案214a和沟道区CH的半导体衬底210。由此，隔离层218的上部部分可以部分地从沟道区CH突出。
参见图2I，在暴露的沟道区CH和第二硬掩模图案214a上形成用于浮栅的栅绝缘层220和第一导电层222。例如，可以使用氧化物层形成栅绝缘层220，或者通过层叠氧化物层、氮化物层和氧化物层来形成栅绝缘层220。可以使用多晶硅（poly-Si）层来形成第一导电层222。例如，可以使用掺杂poly-Si层来形成第一导电层222，或者通过层叠未掺杂的poly-Si层和掺杂的poly-Si层来形成第一导电层222。可以根据存储器器件的特性通过注入N型杂质或P型杂质来形成第一导电层222。
参见图2J，为了控制形成在隔离区ISO中的隔离层218的顶表面和沟道区CH的顶表面之间的有效场高度（EFH），可以部分地刻蚀隔离层218的上部部分。此后，可以沿着整个结构的表面形成电介质层224，用于控制栅的第二导电层226可以形成在电介质层224上。例如，可以通过层叠氧化物层、氮化物层和氧化物层来形成电介质层224，或者电介质层224可以由高k电介质材料形成。第二导电层226可以由掺杂poly-Si层形成。另外，金属层可以进一步形成在poly-Si层上，以减少第二导电层226的电阻。此后，可以使用栅极图案化工艺将漏极选择线DSL形成在漏极选择区DSL中，多个字线WL0至WLn可以形成在字线区WL中，且源极选择线SSL可以形成在源极选择区SSL中。由此，可以形成一种半导体器件，其中具有灯泡形的第二沟槽T2彼此连接。另外，可以使用半导体衬底210的一部分来形成支持层PP以支持沟道区CH，并可以防止沟道区之间产生漏电流。
具体来说，支持层PP可以形成在字线区WL或源极选择区SSL而不是可能出现漏电流的漏极选择区DSL中。将参考后续的横截面视图来进行详细描述。
图3A是根据本发明第一实施例的半导体存储器器件的横截面视图。
参见图3A，示出了沿着图2J的透视图的方向A-A’获得的横截面视图。在第一实施例中，支持层PP可以形成在半导体衬底210的字线区WL中，第二沟槽T2可以在漏极选择区DSL和源极选择区SSL中彼此连接。单个支持层PP或多个支持层PP可以形成在字线区WL中。例如，假设有源区（参见图2A中的ACT）和隔离区（参见图2A中的ISO）交替地限定在一个方向上，则支持区SP可以限定在基本穿过有源区和隔离区的另一方向上。即使一个支持层PP或多个支持层PP形成在字线区WL中，由于在沟道区CH之下的彼此连接的第二沟槽T2形成在漏极选择区DSL和源极选择区SSL中，所以可以切断漏极选择区DSL和源极选择区SSL中的漏电流路径。因而，在漏极选择区DSL和源极选择区SSL中可以防止在沟道区CH之下出现漏电流。
图3B是根据本发明第二实施例的半导体存储器器件的横截面视图。
参见图3B，在第二实施例中，支持层PP可以形成在半导体衬底210的源极选择区SSL中，第二沟槽T2可以在漏极选择区DSL和字线区WL中彼此连接。即使一个支持层或多个支持层PP形成在源极选择区SSL中，由于在漏极选择区DSL和字线区WL中形成了在沟道区CH之下的彼此连接的第二沟槽T2，也可以切断漏极选择区DSL和字线区WL中的漏电流路径。因而，可以防止在漏极选择区DSL和字线区WL中产生在沟道区CH之下的漏电流。
图3C是根据本发明第三实施例的半导体存储器器件的横截面视图。
参见图3C，在第三实施例中，支持层PP可以形成在半导体衬底210的字线区WL和源极选择区SSL中，支持层PP可以没有形成在漏极选择区DSL中。即使一个支持层PP或多个支持层PP形成在字线区WL和源极选择区SSL中，由于在漏极选择区DSL中形成了在沟道区CH之下的彼此连接的第二沟槽T2，也可以切断漏极选择区DSL中的漏电流路径。因而，可以防止在漏极选择区DSL中产生沟道区CH之下的漏电流。
上述实施例描述了制造半导体存储器器件的方法，其中灯泡形的第二沟槽T2形成在半导体衬底210的字线区WL、漏极选择区DSL和源极选择区SSL中且相互连接，并且支持层PP形成在字线区WL和源极选择区SSL中的至少一个中。然而，连接的第二沟槽T2也可以形成在除了上述的字线区WL、漏极选择区DSL和源极选择区SSL以外的其他区域中。例如，具有灯泡形的连接的沟槽也可以形成在外围电路区中，使得可以防止相邻晶体管之间的漏电流。在这种情况下，支持层PP可以形成在半导体衬底210的没有漏电流或与其他部分相比出现较小漏电流的区域中，所以沟道区CH可以通过支持层PP来支持。
此外，尽管上述示例性实施例描述了NAND快闪存储器器件，本发明也可以应用于硅-氧化物-氮化物-氧化物-硅（SONOS）型存储器器件。
由于本发明的示例性实施例可以防止在不同有源区之间产生漏电流，所以可以提高半导体存储器器件的可靠性。
在附图和说明书中，已经公开了本发明的典型示例性实施例，尽管采用了特定术语，但是这些术语只是一般性且描述性的，并非用于限定。本发明的范围在后续的权利要求中限定。因此，本领域技术人员将理解到在不脱离后续权利要求限定的本发明的精神和范围的情况下，可以进行形式和细节的各种改变。

Claims (18)

1.一种半导体存储器器件，包括：
半导体衬底，其中交替限定了有源区和隔离区，且在与所述有源区和所述隔离区相交的方向上限定了支持区；
第一沟槽，形成在所述隔离区中；
第二沟槽，形成在所述有源区和所述隔离区中的第一沟槽之下；以及
支持层，形成在所述支持区中的第一沟槽之下。
2.如权利要求1所述的半导体存储器器件，其中，所述支持层由所述半导体衬底形成。
3.如权利要求1所述的半导体存储器器件，其中，所述支持层在与所述有源区和所述隔离区交叉的方向上隔开所述第二沟槽。
4.如权利要求1所述的半导体存储器器件，其中，所述第二沟槽形成为灯泡形。
5.如权利要求1所述的半导体存储器器件，还包括：通过对所述第一沟槽之间的半导体衬底注入离子而形成的沟道区。
6.如权利要求5所述的半导体存储器器件，其中，所述沟道区具有比所述第一沟槽小的深度。
7.如权利要求1所述的半导体存储器器件，还包括形成在半导体衬底上的漏极选择线、字线和源极选择线。
8.如权利要求7所述的半导体存储器器件，其中，所述支持层被限定在形成所述字线的区域中、或被限定在形成所述源极选择线的区域中，或被分别限定在形成所述字线的区域中和形成所述源极选择线的区域中。
9.一种制造半导体存储器器件的方法，所述方法包括：
通过将离子注入到半导体衬底中来形成沟道区，在所述半导体衬底中限定了有源区和隔离区，且在与所述有源区和所述隔离区相交的方向上限定了支持区；
在所述隔离区中形成第一沟槽；以及
除了所述支持区以外在所述有源区和所述隔离区中的第一沟槽下形成第二沟槽。
10.如权利要求9所述的方法，其中，形成所述第一沟槽包括：
形成被设置在形成了所述沟道区的半导体衬底之上的第一硬掩模图案，所述第一硬掩模图案暴露半导体衬底的隔离区；以及
在被所述隔离区暴露的半导体衬底上执行第一刻蚀工艺以形成所述第一沟槽。
11.如权利要求10所述的方法，其中，通过氧化物层、氮化物层或导电层、或者通过层叠其中的至少两层来形成所述第一硬掩模图案。
12.如权利要求10所述的方法，其中，通过使用各向异性干法刻蚀工艺来执行所述第一刻蚀工艺。
13.如权利要求10所述的方法，其中，所述第一沟槽被形成为比所述沟道区更深的深度。
14.如权利要求9所述的方法，其中，形成所述第二沟槽包括：
沿着具有所述第一沟槽的整个结构的表面形成第二硬掩模层；
在形成在所述支持区中的第二硬掩模层上形成第三硬掩模图案；
在第三硬掩模图案之间暴露的第二硬掩模层中，使用第二刻蚀工艺来去除形成在所述隔离区的底表面上的第二硬掩模层，以暴露所述半导体衬底并留下沿着所述第一沟槽的内表面形成的第二硬掩模层；
去除所述第三硬掩模图案；以及
通过使用剩余的第二硬掩模层作为刻蚀掩模来执行第三刻蚀工艺而刻蚀在所述隔离区中暴露的半导体衬底，以形成所述第二沟槽。
15.如权利要求14所述的方法，其中，使用各向异性干法刻蚀工艺来执行所述第二刻蚀工艺。
16.如权利要求14所述的方法，其中，使用各向同性干法刻蚀工艺来执行所述第三刻蚀工艺，以形成灯泡形的第二沟槽。
17.如权利要求14所述的方法，其中，通过氧化物层、氮化物层或导电层、或者通过层叠其中的至少两层来形成所述第二硬掩模图案。
18.如权利要求10所述的方法，还包括，在形成所述第二沟槽之后：
在所述第一沟槽和所述第二沟槽内形成隔离层；
去除所述第一硬掩模图案以暴露从半导体衬底突出的隔离层和半导体衬底的有源区；
在暴露在隔离层之间的半导体衬底上形成栅绝缘层和第一导电层；
沿着第一导电层和隔离层的表面形成电介质层和第二导电层；以及
将所述第二导电层、所述电介质层和所述第一导电层图案化。
CN201310043672.6A 2012-08-16 2013-02-04 半导体存储器器件及其制造方法 Pending CN103594474A (zh)

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