CN103582563B - 制造具有防水性表面以及亲水性背面的芯片的方法 - Google Patents
制造具有防水性表面以及亲水性背面的芯片的方法 Download PDFInfo
- Publication number
- CN103582563B CN103582563B CN201380001476.0A CN201380001476A CN103582563B CN 103582563 B CN103582563 B CN 103582563B CN 201380001476 A CN201380001476 A CN 201380001476A CN 103582563 B CN103582563 B CN 103582563B
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- back side
- manufacture method
- hydrophobic solvent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 239000005871 repellent Substances 0.000 title claims abstract description 19
- 239000002904 solvent Substances 0.000 claims abstract description 41
- 230000002209 hydrophobic effect Effects 0.000 claims abstract description 39
- 238000004078 waterproofing Methods 0.000 claims abstract description 18
- 125000002887 hydroxy group Chemical group [H]O* 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 93
- XEKOWRVHYACXOJ-UHFFFAOYSA-N Ethyl acetate Chemical compound CCOC(C)=O XEKOWRVHYACXOJ-UHFFFAOYSA-N 0.000 claims description 30
- HEDRZPFGACZZDS-UHFFFAOYSA-N Chloroform Chemical compound ClC(Cl)Cl HEDRZPFGACZZDS-UHFFFAOYSA-N 0.000 claims description 28
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 claims description 15
- DKPFZGUDAPQIHT-UHFFFAOYSA-N Butyl acetate Natural products CCCCOC(C)=O DKPFZGUDAPQIHT-UHFFFAOYSA-N 0.000 claims description 14
- 229930195733 hydrocarbon Natural products 0.000 claims description 11
- 150000002430 hydrocarbons Chemical class 0.000 claims description 11
- 125000000217 alkyl group Chemical group 0.000 claims description 10
- 239000000203 mixture Substances 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 239000004215 Carbon black (E152) Substances 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 229910052736 halogen Inorganic materials 0.000 claims description 5
- 150000002367 halogens Chemical class 0.000 claims description 5
- 125000003545 alkoxy group Chemical group 0.000 claims description 4
- 238000006701 autoxidation reaction Methods 0.000 claims description 3
- FUZZWVXGSFPDMH-UHFFFAOYSA-N hexanoic acid Chemical group CCCCCC(O)=O FUZZWVXGSFPDMH-UHFFFAOYSA-N 0.000 claims 4
- 239000000243 solution Substances 0.000 description 16
- FUZZWVXGSFPDMH-UHFFFAOYSA-M hexanoate Chemical compound CCCCCC([O-])=O FUZZWVXGSFPDMH-UHFFFAOYSA-M 0.000 description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- DCAYPVUWAIABOU-UHFFFAOYSA-N hexadecane Chemical compound CCCCCCCCCCCCCCCC DCAYPVUWAIABOU-UHFFFAOYSA-N 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 230000010148 water-pollination Effects 0.000 description 4
- 239000012528 membrane Substances 0.000 description 3
- 239000005011 phenolic resin Substances 0.000 description 3
- 229920001568 phenolic resin Polymers 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 150000003505 terpenes Chemical class 0.000 description 3
- 235000007586 terpenes Nutrition 0.000 description 3
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/95053—Bonding environment
- H01L2224/95085—Bonding environment being a liquid, e.g. for fluidic self-assembly
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/951—Supplying the plurality of semiconductor or solid-state bodies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
- H01L2224/95143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
- H01L2224/95143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
- H01L2224/95146—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium by surface tension
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Laminated Bodies (AREA)
- Application Of Or Painting With Fluid Materials (AREA)
- Die Bonding (AREA)
Abstract
提供一种制造具有防水性表面以及亲水性背面的芯片的新方法。为此,本公开的第1方式所涉及的制造方法包括如下工序,通过水膜(902)来保护芯片(811)的背面(811b),同时使具有羟基的芯片(811)的表面(811a)接触使R1-Si(OR2)3或R1-SiY3溶解于第2疏水性溶剂(905a)而得到的有机溶液(905),从而在芯片(811)的表面(811a)形成防水性的薄膜。
Description
技术领域
本公开涉及制造具有防水性表面以及亲水性背面的芯片的方法。
背景技术
专利文献1公开了一种将芯片那样的微小的构件20配置在基板10上的方法。该方法被称为“FSA法”。在FSA法中,如图15A所示,准备具备多个亲水性区域11以及包围该亲水性区域11的防水性区域12的基板10。接着,如图15B所示,将配置于基板10的构件20分散于实质上不溶于水的溶剂40,来准备构件含有液50。由于构件20的背面是亲水性的,因此构件20的背面能够与1个亲水性区域11接合。另一方面,表面是防水性的。不仅表面是防水性的,构件20的背面以外的面都是防水性的。
接着,如图15C所示,利用第1刮板(squeegee)61在多个亲水性区域11配置水30。然后,图15D所示,利用第2刮板62,涂敷构件含有液50,使构件含有液50与配置于亲水性区域11的水31接触。在该过程中,各构件20在配置于亲水性区域11的水31中移动。此时,亲水性背面面向亲水性区域11。然后,去除水31以及构件含有液50所含的溶剂,在亲水性区域11配置构件20。所配置的构件20的背面与亲水性区域11相接。专利文献1作为参照而编入本说明书。
在先技术文献
专利文献
专利文献1:美国专利第7,730,610号说明书
发明内容
发明要解决的课题
本公开的目的在于,提供一种制造具有防水性表面以及亲水性背面的芯片的新方法。
解决课题的手段
本公开所涉及的制造具有防水性表面以及亲水性背面的芯片的方法,包括如下工序:
工序(a),准备隔着蜡膜而在背面侧具备芯片的第1基板,并且所述芯片具备表面以及背面,所述芯片的所述表面与所述蜡膜相接,且所述芯片的所述背面是亲水性的;
工序(b),使所述芯片的所述背面与在表面具有水膜的第2基板接触,获得由所述第1基板以及所述第2基板构成的层叠体,并且所述芯片的所述背面与所述水膜接触;
工序(c),将所述层叠体浸渍在第1疏水性溶剂中,使所述蜡膜溶解于所述第1疏水性溶剂;
工序(d),去除所述第1基板,获得在表面附着了所述芯片的所述第2基板,并且所述芯片的所述背面与所述水膜接触,且所述芯片的所述表面露出;
工序(e),通过所述水膜保护所述芯片的所述背面,同时使具有羟基的所述芯片的所述表面接触使R1-Si(OR2)3或R1-SiY3溶解于第2疏水性溶剂而得到的有机溶液,从而在所述芯片的所述表面形成防水性的薄膜,并且所述R1表示烃基或氟化烃,所述R2表示烷氧基,且所述Y表示卤素;和
工序(f),去除所述第2基板,从而获得具有防水性表面以及亲水性背面的所述芯片。
发明效果
本公开提供一种制造具有防水性表面以及亲水性背面的芯片的新方法。
附图说明
图1表示实施方式所涉及的芯片的制造方法所含的工序(a)。
图2表示实施方式所涉及的芯片的制造方法所含的工序(b)。
图3表示实施方式所涉及的芯片的制造方法所含的工序(c)。
图4表示实施方式所涉及的芯片的制造方法所含的工序(d)。
图5表示实施方式所涉及的芯片的制造方法所含的工序(e)。
图6表示实施例所涉及的芯片的制造方法所含的一个工序。
图7表示图6后续的、实施例所涉及的芯片的制造方法所含的一个工序。
图8表示图7后续的、实施例所涉及的芯片的制造方法所含的一个工序。
图9表示图8后续的、实施例所涉及的芯片的制造方法所含的一个工序。
图10表示图9后续的、实施例所涉及的芯片的制造方法所含的一个工序。
图11表示实施例所涉及的芯片的制造方法所含的一个工序。
图12表示图11后续的、实施例所涉及的芯片的制造方法所含的一个工序。
图13表示实施例所涉及的芯片的制造方法所含的一个工序。
图14表示图13后续的、实施例所涉及的芯片的制造方法所含的一个工序。
图15A表示专利文献1中公开的FSA法的一个工序。
图15B表示专利文献1中公开的FSA法的一个工序。
图15C表示专利文献1中公开的FSA法的一个工序。
图15D表示专利文献1中公开的FSA法的一个工序。
具体实施方式
本公开的第1方式所涉及的制造具有防水性表面811a以及亲水性背面811b的芯片811的方法,包括如下工序:
工序(a),准备隔着蜡膜830而在背面侧具备芯片811的第1基板110,并且芯片811具备表面811a以及背面811b,芯片811的表面811a与蜡膜830相接,且芯片811的背面811b是亲水性的;
工序(b),使芯片811的背面811b接触在表面具有水膜902的第2基板120,获得由第1基板110以及第2基板120构成的层叠体100,并且芯片811的背面811b与水膜902接触;
工序(c),使层叠体100浸渍在第1疏水性溶剂903a中,使蜡膜830溶解于第1疏水性溶剂903a;
工序(d),去除第1基板110,获得在表面附着了芯片811的第2基板120,并且芯片811的背面811b与水膜902接触,且芯片811的表面811a露出;
工序(e),通过水膜902来保护芯片811的背面811b,同时使具有羟基的芯片811的表面811a接触有机溶液905,该有机溶液905是使R1-Si(OR2)3或R1-SiY3溶解于第2疏水性溶剂905a而得到的,从而在芯片811的表面811a形成防水性的薄膜,其中R1表示烃基或氟化烃,R2表示烷氧基,且Y表示卤素;和
工序(f),去除第2基板120,从而获得具有防水性表面811a以及亲水性背面811b的芯片811。
第2方式所涉及的制造方法,在上述第1方式中,蜡膜830也可以是粘着性的。
第3方式所涉及的制造方法,在上述第1方式中,第1疏水性溶剂903a也可以是乙酸丁酯、乙酸乙酯、氯仿、甲苯、或它们的混合物。
第4方式所涉及的制造方法,在上述第1方式中,在工序(e)中,也可以将在表面附着了芯片811的第2基板102浸渍在有机溶液905中。
第5方式所涉及的制造方法,在上述第1方式中,第2疏水性溶剂905a也可以是具有6个以上碳数的烃、乙酸丁酯、乙酸乙酯、氯仿、或它们的混合物。
此外,本公开的第6方式所涉及的制造具有防水性表面811a以及亲水性背面811b的芯片811的方法,包括如下工序:
工序(a),准备隔着蜡膜830而在背面侧具备芯片811的第1基板110,并且芯片811具备表面811a以及背面811b,芯片811的表面811a与蜡膜830相接,且芯片811的背面811b是亲水性的;
工序(b),使芯片811的背面811b与在表面具有水膜902的第2基板120接触,获得由第1基板110以及第2基板120构成的层叠体100,并且芯片811的背面811b与水膜902接触;
工序(c),使层叠体100浸渍在第1疏水性溶剂903a中,使蜡膜830溶解于第1疏水性溶剂903a;
工序(d),去除第1基板110,获得在表面附着了芯片811的第2基板120,并且芯片811的背面811b与水膜902接触,且芯片811的表面811a露出;
工序(e),通过水膜902来保护芯片811的背面811b,同时使具有金膜的芯片811的表面811a接触含有R1-SH的有机溶液905,该有机溶液905溶解于第2疏水性溶剂905a,使烷基或氟化烷基与芯片811的表面结合来赋予防水性,其中R1表示烃基或氟化烃;和
工序(f),去除第2基板120,获得具有防水性表面811a以及亲水性背面811b的芯片811。
第7方式所涉及的制造方法,在上述第6方式中,蜡膜830也可以是粘着性的。
第8方式所涉及的制造方法,在上述第6方式中,第1疏水性溶剂903a也可以是乙酸丁酯、乙酸乙酯、氯仿、甲苯、或它们的混合物。
第9方式所涉及的制造方法,在上述第6方式中,在工序(e)中,也可以将在表面附着了芯片811的第2基板102浸渍在有机溶液905中。
第10方式所涉及的制造方法,在上述第6方式中,第2疏水性溶剂905a也可以是具有6个以上碳数的烃、乙酸丁酯、乙酸乙酯、氯仿、或它们的混合物。
以下,参照附图对本公开的实施方式进行说明。
在实施方式中,依次执行工序(a)~工序(f)。
(工序(a))
首先,如图1所示,准备第1基板110。
第1基板110在背面具有蜡膜830。蜡膜830的材料的例子是萜烯酚醛树脂。蜡被涂敷在第1基板110,形成蜡膜830。涂敷蜡的方法的例子是旋涂法。
隔着蜡膜830,将芯片811设置在第1基板110。芯片811包含表面811a以及背面811b。表面811a与蜡膜830相接。另一方面,背面811b露出。
用语“表面”是指上表面。另一方面,用语“背面”是指底面。
为了抑制芯片811从第1基板110的背面落下,优选蜡膜830是粘着性的。
芯片811的例子是半导体元件或太阳能电池元件。电极最好在芯片811的背面811b露出。若通过FSA法而将芯片811配置于具有电极的基板10,则露出到背面811b的电极与基板10的表面所具备的电极电连接。
芯片811的背面811b是亲水性的。在以下的项目(a)~(c)中记述对背面811b赋予亲水性的方法的例子。
(a)对附着了芯片811的第1基板110的背面进行等离子照射处理。
(b)在芯片811的背面811b形成SiO2层或SiN层。
(c)在芯片811的背面811b形成金层或铜层之后,将由X-R-SH表示的有机化合物提供给芯片811的背面811b。X表示-COOH、-OH、-SO3、或-SO4 -。
(工序(b))
接着,如图2所示,使芯片811的背面811b与在表面具有水膜902的第2基板120接触。如此,能够获得由第1基板110以及第2基板120构成的层叠体100。如图2所示,芯片811的背面811b与水膜902接触。
(工序(c))
在工序(c)中,如图3所示,将层叠体100浸渍在含有第1疏水性溶剂903a的容器903中。第1疏水性溶剂903a使蜡膜830溶解。第1疏水性溶剂903a的例子为乙酸丁酯、乙酸乙酯、氯仿、甲苯、或它们的混合物。在后述的实施例中,使用了乙酸丁酯。
水膜902不溶解于第1疏水性溶剂903a,因此芯片811的背面811b保持亲水性。换言之,通过水膜902保护了芯片811的亲水性背面811b免受第1疏水性溶剂903a的影响。
(工序(d))
由于在工序(c)中蜡膜830被溶解,因此如图4所示,第1基板110被简单地去除。最好第1基板110在第1疏水性溶剂903a中从第2基板120分离。如此,能够获得在表面附着了芯片811的第2基板120。芯片811的背面811b与水膜902接触。另一方面,芯片811的表面露出。
(工序(e))
在工序(e)中,对芯片811的表面811a赋予防水性。以下说明对表面811a赋予防水性的方法的例子。
如图5所示,将在表面附着了芯片811的第2基板120浸渍在含有有机溶液905的容器904中。有机溶液905含有R1-Si(OR2)3、R1-SiY3、或R1-SH。在此,R1表示烃基或氟化烃。R2表示烷氧基。Y表示卤素。优选卤素为氯。
芯片811的表面811a与R1-Si(OR2)3、R1-SiY3、或R1-SH发生反应,在芯片811的表面811a形成防水性的薄膜。
有机溶液905的溶剂是疏水性的。为了与第1疏水性溶剂903a区分,在工序(e)中使用的疏水性溶剂称为“第2疏水性溶剂905a”。第2疏水性溶剂905a的例子是具有6以上碳数的烃、乙酸丁酯、乙酸乙酯、氯仿、或它们的混合物。在后述的实施例中,使用了氯仿/十六烷混合溶液。
与工序(c)中的说明相同,因为水膜902不溶解于第2疏水性溶剂905a,所以芯片811的背面811b保持亲水性。换言之,通过水膜902保护了芯片811的亲水性背面811b不受第2疏水性溶剂905a的影响。因此,防水性的薄膜不形成在芯片811的亲水性背面811b。另一方面,如上所述,防水性的薄膜形成在芯片811的表面811a。
有机溶液905中含有的R1-Si-(OR2)3与存在于芯片811的表面811a的羟基发生反应,形成防水性的薄膜。这样的羟基通过将芯片811暴露于自然氧化环境中而形成。因此,优选在将芯片811浸渍于有机溶液905之前,将芯片811暴露于自然氧化环境中。
有机溶液905中含有的R1-SH与形成在芯片811的表面811a的金膜发生反应,形成防水性的薄膜。因此,优选在将芯片811浸渍于有机溶液905之前,在芯片811的表面811a形成金膜。
(工序(f))
工序(e)之后,去除第2基板120。由于第2基板120的表面不具有粘着性,因此第2基板120能够简单地去除。如此,能够获得具有防水性表面811a以及亲水性背面811b的芯片811。
(实施例)
在以下的实施例中,对本公开更详细地进行说明。
作为芯片811,准备了多个平板状GaAs元件。参照附图来说明制造平板状GaAs元件的方法。
首先,如图6所示,准备GaAs基板作为支撑基板800。支撑基板800的厚度是450微米。接着,如图7所示,具有100纳米的厚度的AlAs层820形成在支撑基板800的表面。进而,具有5微米的厚度的GaAs层810形成在AlAs层820的表面。
然后,如图8所示,在GaAs层810的表面上形成掩模层900。如图9所示,没有被掩模层900覆盖的部分通过湿法蚀刻而被去除。然后,去除掩模层900。如此,如图10所示,由GaAs元件构成的多个芯片811形成在支撑基板800上。
各芯片811具有150微米的长度、150微米的宽度、以及5.1微米的厚度。
另一方面,如图11所示,准备具有700微米的厚度的玻璃基板作为第1基板110。在第1基板110的表面,通过旋涂法,涂敷萜烯酚醛树脂蜡,形成蜡膜830。萜烯酚醛树脂蜡购买了日化精工株式会社生产的商品名“SPACELIQUID”。蜡膜830具有1.5微米的厚度。
然后,如图12所示,将第1基板110翻过来。
如图13所示,在支撑基板800上层叠第1基板110,使蜡膜830与芯片811的表面811a接触。然后,如图14所示,将支撑基板800以及第1基板110浸渍在具有1M的浓度的盐酸水溶液901中,将AlAs层820溶解。如此,去除了支撑基板800,获得了如图1所示的、隔着粘着性的蜡膜830而在背面侧具备芯片811的第1基板110。
从第1基板110的背面侧起进行氧等离子处理,使芯片811的背面侧811b成为亲水性。
另一方面,准备硅基板作为第2基板120。该第2基板120具有525微米的厚度。第2基板120的表面在氧气氛下暴露于等离子处理。如此,对第2基板120的表面赋予了亲水性。接着,将第2基板120浸渍在水中,在第2基板120的表面形成了水膜902。
接着,如图2所示,将第1基板110的背面附着在第2基板120的表面,使得芯片811的背面811b与水膜902相接,从而获得了层叠体100。
如图3所示,层叠体100在40℃的温度下浸渍在乙酸丁酯中。蜡膜830被乙酸丁酯溶解。然后,如图4所示,第1基板110在乙酸丁酯中被容易地去除。如此,获得了隔着水膜902而在表面具有多个芯片811的第2基板120。
接着,如图5所示,将该第2基板120在含有具有0.1vol%的浓度的CH3CH2CH2SiCl3(以下,称为“PTS”)的氯仿/十六烷混合溶液(体积比=1:4)中浸渍60分钟。接下来,将在该第2基板120的表面配置的多个芯片811在纯净的氯仿中洗净,然后去除氯仿。如此,平板状的芯片811的表面811a被由PTS构成的防水膜覆盖。在此期间,芯片811的亲水性背面811b被水膜902保护。因此,防水膜没有形成在芯片811的背面811b。换言之,芯片811的背面811b没有被防水膜覆盖。
如此,获得了具有防水性表面811a以及亲水性背面811b的芯片811。更详细来说,表面811a的整个面是防水性的,背面811b的整个面是亲水性的。
-工业实用性-
通过本公开所获得的芯片可以在FSA法中使用。
-符号说明-
100层叠体
110第1基板
120第2基板
811芯片
811a防水性表面
811b亲水性背面
830蜡膜
902水膜
903容器
903a第1疏水性溶剂
904容器
905有机溶液
905a第2疏水性溶剂
800支撑基板
810GaAs层
820AlAs层
900掩模层
Claims (10)
1.一种制造方法,制造具有防水性表面以及亲水性背面的芯片,
所述制造方法包括如下工序:
工序(a),准备隔着蜡膜而在背面侧具备芯片的第1基板,并且所述芯片具备表面以及背面,所述芯片的所述表面与所述蜡膜相接,且所述芯片的所述背面是亲水性的;
工序(b),使所述芯片的所述背面与在表面具有水膜的第2基板接触,获得由所述第1基板以及所述第2基板构成的层叠体,并且所述芯片的所述背面与所述水膜接触;
工序(c),将所述层叠体浸渍在第1疏水性溶剂中,使所述蜡膜溶解于所述第1疏水性溶剂;
工序(d),去除所述第1基板,获得在表面附着了所述芯片的所述第2基板,并且所述芯片的所述背面与所述水膜接触,且所述芯片的所述表面露出;
工序(e),通过所述水膜保护所述芯片的所述背面,同时使具有羟基的所述芯片的所述表面接触有机溶液,该有机溶液是使R1-Si(OR2)3或R1-SiY3溶解于第2疏水性溶剂而得到的,从而在所述芯片的所述表面形成防水性的薄膜,其中所述羟基是通过将所述芯片暴露于自然氧化环境中而形成的,所述R1表示烃基或氟化烃,所述R2表示烷氧基,且所述Y表示卤素;和
工序(f),去除所述第2基板,从而获得具有防水性表面以及亲水性背面的所述芯片。
2.根据权利要求1所述的制造方法,其中,
所述蜡膜是粘着性的。
3.根据权利要求1所述的制造方法,其中,
所述第1疏水性溶剂是乙酸丁酯、乙酸乙酯、氯仿、甲苯、或它们的混合物。
4.根据权利要求1所述的制造方法,其中,
在所述工序(e)中,将在表面附着了所述芯片的所述第2基板浸渍在所述有机溶液中。
5.根据权利要求1所述的制造方法,其中,
所述第2疏水性溶剂是具有6个以上碳数的烃、乙酸丁酯、乙酸乙酯、氯仿、或它们的混合物。
6.一种制造方法,制造具有防水性表面以及亲水性背面的芯片,
所述制造方法包括如下工序:
工序(a),准备隔着蜡膜而在背面侧具备芯片的第1基板,并且所述芯片具备表面以及背面,所述芯片的所述表面与所述蜡膜相接,且所述芯片的所述背面是亲水性的;
工序(b),使所述芯片的所述背面与在表面具有水膜的第2基板接触,获得由所述第1基板以及所述第2基板构成的层叠体,并且所述芯片的所述背面与所述水膜接触;
工序(c),将所述层叠体浸渍在第1疏水性溶剂中,使所述蜡膜溶解于所述第1疏水性溶剂;
工序(d),去除所述第1基板,获得在表面附着了所述芯片的所述第2基板,并且所述芯片的所述背面与所述水膜接触,且所述芯片的所述表面露出;
工序(e),在所述芯片的表面形成了金膜之后,通过所述水膜保护所述芯片的所述背面,同时使具有所述金膜的所述芯片的所述表面接触含有R1-SH的有机溶液,该有机溶液溶解于第2疏水性溶剂,使烷基或氟化烷基与所述芯片的所述表面结合来赋予防水性,并且所述R1表示烃基或氟化烃;和
工序(f),去除所述第2基板,从而获得具有防水性表面以及亲水性背面的所述芯片。
7.根据权利要求6所述的制造方法,其中,
所述蜡膜是粘着性的。
8.根据权利要求6所述的制造方法,其中,
所述第1疏水性溶剂是乙酸丁酯、乙酸乙酯、氯仿、甲苯、或它们的混合物。
9.根据权利要求6所述的制造方法,其中,
在所述工序(e)中,将在表面附着了所述芯片的所述第2基板浸渍在所述有机溶液中。
10.根据权利要求6所述的制造方法,其中,
所述第2疏水性溶剂是具有6个以上碳数的烃、乙酸丁酯、乙酸乙酯、氯仿、或它们的混合物。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012073191 | 2012-03-28 | ||
JP2012-073191 | 2012-03-28 | ||
PCT/JP2013/001701 WO2013145610A1 (ja) | 2012-03-28 | 2013-03-14 | 撥水性表面および親水性裏面を有するチップを製造する方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103582563A CN103582563A (zh) | 2014-02-12 |
CN103582563B true CN103582563B (zh) | 2016-03-02 |
Family
ID=49258925
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201380001476.0A Expired - Fee Related CN103582563B (zh) | 2012-03-28 | 2013-03-14 | 制造具有防水性表面以及亲水性背面的芯片的方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9018042B2 (zh) |
JP (1) | JP5411395B1 (zh) |
CN (1) | CN103582563B (zh) |
WO (1) | WO2013145610A1 (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10418527B2 (en) * | 2014-10-31 | 2019-09-17 | eLux, Inc. | System and method for the fluidic assembly of emissive displays |
US10446728B2 (en) * | 2014-10-31 | 2019-10-15 | eLux, Inc. | Pick-and remove system and method for emissive display repair |
FR3063832B1 (fr) * | 2017-03-08 | 2019-03-22 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede d'auto-assemblage de composants microelectroniques |
CN108333817B (zh) * | 2018-01-25 | 2021-03-02 | Oppo广东移动通信有限公司 | 显示屏组件及电子设备 |
FR3137208A1 (fr) * | 2022-06-28 | 2023-12-29 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Collage auto-aligné par contraste d’hydrophilie |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5391913A (en) * | 1991-12-27 | 1995-02-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US5980992A (en) * | 1997-10-03 | 1999-11-09 | 3M Innovative Properties Company | Fluorochemical treatments to provide low-energy surfaces |
CN101310373A (zh) * | 2005-09-29 | 2008-11-19 | 松下电器产业株式会社 | 电子电路构成部件的装配方法以及装配装置 |
US7459197B2 (en) * | 2004-11-30 | 2008-12-02 | Lucent Technologies Inc. | Reversibly adaptive rough micro- and nano-structures |
WO2011081095A1 (ja) * | 2009-12-28 | 2011-07-07 | 東京エレクトロン株式会社 | 実装方法及び実装装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60229932A (ja) * | 1984-04-28 | 1985-11-15 | Toyota Central Res & Dev Lab Inc | 複合部材およびその製造方法 |
DE69218811T2 (de) | 1991-01-23 | 1997-07-17 | Matsushita Electric Ind Co Ltd | Wasser- und ölabweisender adsorbierter Film und Verfahren zu dessen Herstellung |
JP3150133B2 (ja) * | 1991-01-23 | 2001-03-26 | 松下電器産業株式会社 | 撥水撥油性面と親水性面を有する物品及びその製造方法 |
JP4488702B2 (ja) * | 2003-07-30 | 2010-06-23 | 株式会社沖データ | 半導体装置の製造方法 |
US20050271893A1 (en) * | 2004-06-04 | 2005-12-08 | Applied Microstructures, Inc. | Controlled vapor deposition of multilayered coatings adhered by an oxide layer |
GB0618460D0 (en) * | 2006-09-20 | 2006-11-01 | Univ Belfast | Process for preparing surfaces with tailored wettability |
US20090265629A1 (en) * | 2008-04-18 | 2009-10-22 | Samsung Electronics Co., Ltd | Systems and methods for extending assistance in a multi-function peripheral device |
-
2013
- 2013-03-14 CN CN201380001476.0A patent/CN103582563B/zh not_active Expired - Fee Related
- 2013-03-14 JP JP2013537960A patent/JP5411395B1/ja not_active Expired - Fee Related
- 2013-03-14 WO PCT/JP2013/001701 patent/WO2013145610A1/ja active Application Filing
- 2013-11-26 US US14/090,198 patent/US9018042B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5391913A (en) * | 1991-12-27 | 1995-02-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US5980992A (en) * | 1997-10-03 | 1999-11-09 | 3M Innovative Properties Company | Fluorochemical treatments to provide low-energy surfaces |
US7459197B2 (en) * | 2004-11-30 | 2008-12-02 | Lucent Technologies Inc. | Reversibly adaptive rough micro- and nano-structures |
CN101310373A (zh) * | 2005-09-29 | 2008-11-19 | 松下电器产业株式会社 | 电子电路构成部件的装配方法以及装配装置 |
WO2011081095A1 (ja) * | 2009-12-28 | 2011-07-07 | 東京エレクトロン株式会社 | 実装方法及び実装装置 |
Also Published As
Publication number | Publication date |
---|---|
JPWO2013145610A1 (ja) | 2015-12-10 |
WO2013145610A1 (ja) | 2013-10-03 |
CN103582563A (zh) | 2014-02-12 |
JP5411395B1 (ja) | 2014-02-12 |
US9018042B2 (en) | 2015-04-28 |
US20140080261A1 (en) | 2014-03-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103582563B (zh) | 制造具有防水性表面以及亲水性背面的芯片的方法 | |
EP3028299B1 (en) | Methods and structures for processing semiconductor devices | |
US10381277B2 (en) | Method for producing a plurality of measurement regions on a chip, and chip with measurement regions | |
KR102046534B1 (ko) | 기판 가공 방법 | |
CN102130259A (zh) | 一种发光二极管芯片的复合电极及其制作方法 | |
CN109103072B (zh) | 一种大面积单层及少层二硫化钼薄膜的转移方法 | |
TW201230141A (en) | Glass wafers for semiconductor fabrication processes and methods of making same | |
KR20140095824A (ko) | 기판 가공 방법 | |
CN101609828B (zh) | 半导体器件以及半导体器件的制造方法 | |
US20070218192A1 (en) | Method of manufacturing interconnect substrate | |
KR20100087932A (ko) | 자기 조립 단분자막을 이용한 다이 어태치 방법 및 자기 조립 단분자막을 이용하여 다이가 어태치된 패키지 기판 | |
CN109641419A (zh) | 层叠体、电子设备的制造方法、层叠体的制造方法 | |
KR101926357B1 (ko) | 반도체 발광장치 제조방법 | |
TWI623986B (zh) | 封裝結構及其形成方法 | |
CN109545805A (zh) | 一种半导体芯片封装方法 | |
CN102365722B (zh) | 装配部件的方法 | |
US8877298B2 (en) | Printing using a structure coated with ultraviolet radiation responsive material | |
CN108602844A (zh) | 金属组合物及其制备方法 | |
CN105374855A (zh) | 器件和用于制造器件的方法 | |
KR20110131674A (ko) | 감광성 유리 기판을 이용한 디바이스 보호용 캡 및 그 제조 방법 | |
CN105405826B (zh) | 一种铜柱凸块封装结构及其制作方法 | |
CN102064092A (zh) | 用于半导体工艺的载体分离方法 | |
KR101868867B1 (ko) | 플렉서블 표시장치의 제조 방법 | |
US8178154B2 (en) | Method for disposing a component | |
CN109524479A (zh) | 一种半导体芯片封装方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20160106 Address after: Japan Osaka Applicant after: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT Co.,Ltd. Address before: Osaka Japan Applicant before: Matsushita Electric Industrial Co.,Ltd. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160302 |
|
CF01 | Termination of patent right due to non-payment of annual fee |