CN103560113B - 一种阵列结构及其制作方法、阵列基板和显示装置 - Google Patents

一种阵列结构及其制作方法、阵列基板和显示装置 Download PDF

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CN103560113B
CN103560113B CN201310571411.1A CN201310571411A CN103560113B CN 103560113 B CN103560113 B CN 103560113B CN 201310571411 A CN201310571411 A CN 201310571411A CN 103560113 B CN103560113 B CN 103560113B
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drain electrode
layer
source
electrode metal
metal level
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CN103560113A (zh
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史大为
冀新友
李付强
郭建
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Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

本发明公开了一种阵列结构及其制作方法、基于该阵列结构的阵列基板和显示装置，其中阵列结构的制作方法是在栅绝缘层上形成源漏极金属层之前还包括：对源漏极金属信号接入端子所在位置对应的栅绝缘层进行刻蚀，在栅绝缘层上形成过孔结构；或者在栅绝缘层上形成源漏极金属层之后还包括：在源漏极金属信号接入端子所在位置对应的源漏极金属层上形成过孔结构，过孔结构的两侧具有缓和的斜坡。通过对源漏极金属层下方的栅绝缘层进行刻蚀，降低源漏极金属层上方的导电膜层的高度；或者对源漏极金属层进行刻蚀，形成两侧具有缓和斜坡的过孔结构，交替布线中SD基和Gate基上方的ITO高度相同，使得导电球受力更加均匀，提高导线性能。

Description

一种阵列结构及其制作方法、阵列基板和显示装置
技术领域
本发明涉及显示技术领域，特别涉及一种阵列结构及其制作方法、基于该阵列结构的阵列基板和显示装置。
背景技术
目前随着液晶显示面板分辨率的不断提高，特别是对于小尺寸的液晶显示面板而言，提高分辨率就意味着增加指单位长度内包含的像素点的数量，即PPI(Pixels PerInch，每英寸像素的数目)，因此在相同空间下引线的数目就会随之增加。
现有技术一般是通过对IC(Integrated Circuit，集成电路)采用交替布线的方法来尽量压缩布线空间，以应对IC引脚越来越多的问题，图1为栅电极层(Gate层)和源漏金属层(SD层)交替布线的示意图，其中01为Gate层，02为SD层。通过Gate层和SD金属层交替布线，再在其上方进行曝光刻蚀，形成过孔，最后通过ITO(Indium Tin Oxides，铟锡金属氧化物)层导出，如图2所示，图2中左侧和右侧分别为采用交替布线时Gate层和SD金属层的截面示意图，其中03为栅绝缘层，即GI层，04为钝化层，即PVX层，05为导电膜层，即ITO层。但是交替布线的方法存在以下问题，由于在Gate基和SD基设计Pad(信号接入端子)时形成不同的结构，最终形成的Pad高度不同，造成IC Bonding Pad与IC引脚接触不良，Gate层和SD金属层交替布线出现接触不良的示意图如图3所示。图3中可以看出SD金属层的高度高于Gate层的高度，导致SD基和Gate基上方的ITO高度存在高度差，图3中06为导电球，07为IC引脚。
因此，基于上述现有技术的方法由于SD基和Gate基上方的ITO高度不同，最后在相邻IC引脚上对应的ITO与IC Bonding Pad之间出现不同的高度差，导致导电球与ITO的接触面积不同，受力不均匀，产生不良Bonding状态，降低导电性能。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是如何解决交替布线过程中SD基和Gate基上方的ITO高度不同的问题。
(二)技术方案
为解决上述技术问题，本发明提供了一种阵列结构的制作方法，在栅绝缘层上形成源漏极金属层之前还包括：对源漏极金属信号接入端子所在位置对应的栅绝缘层进行刻蚀，在所述栅绝缘层上形成过孔结构。
进一步地，所述对源漏极金属信号接入端子所在位置对应的栅绝缘层进行刻蚀之后还包括：在具有过孔结构的栅绝缘层上方逐层形成源漏极金属层、钝化层以及导电膜层。
进一步地，形成源漏极金属层之后还包括：对所述源漏极金属层在所述过孔结构所对应的位置进行与所述过孔结构相同的刻蚀，继续在所述源漏极金属层上形成钝化层，也进行相同的刻蚀，最后形成导电膜层。
为解决上述技术问题，本发明还提供了一种阵列结构，该阵列结构是通过以上所述的阵列结构制作方法得到的。
为解决上述技术问题，本发明还提供了一种显示装置，包括阵列基板和彩膜基板，其中所述阵列基板是在玻璃基板上形成以上所述的阵列结构得到的。
为解决上述技术问题，本发明还提供了一种阵列结构的制作方法，在栅绝缘层上形成源漏极金属层之后还包括：在所述源漏极金属信号接入端子所在位置对应的源漏极金属层上形成过孔结构，所述过孔结构的两侧具有缓和斜坡。
进一步地，所述过孔结构包括主孔以及主孔两侧的补偿孔，所述补偿孔小于所述主孔，且上述主孔为全透光，所述补偿孔为非全透光。
进一步地，所述过孔结构包括主孔以及主孔两侧的半透膜，所述主孔为全透光，所半透膜为非全透光。
进一步地，所述半透膜包括多级不同透过率的次半透膜，并且所述次半透膜的透过率从所述主孔为起始端向两侧逐级递减分布。
进一步地，在所述源漏极金属层通过湿法刻蚀，形成主孔和补偿孔或主孔和半透膜的过孔结构，之后在所述源漏极金属层上形成具有斜坡的光刻胶，所述光刻胶的高度从两侧向所述主孔逐渐降低，并对所述光刻胶进行曝光以及对所述源漏极金属层进行干法刻蚀。
进一步地，对所述源漏极金属层进行干法刻蚀之后还包括：在所述源漏极金属层上形成钝化层并在所述过孔结构对应的位置也进行相同的斜坡刻蚀，最后形成导电膜层。
为解决上述技术问题，本发明还提供了一种阵列结构，该阵列结构是通过以上所述的阵列结构制作方法得到的。
为解决上述技术问题，本发明还提供了一种显示装置，包括阵列基板和彩膜基板，其中所述阵列基板是在玻璃基板上形成以上所述的阵列结构得到的。
(三)有益效果
本发明实施例提供了一种阵列结构及其制作方法、基于该阵列结构的阵列基板和显示装置，其中阵列结构的制作方法是在栅绝缘层上形成源漏极金属层之前还包括：对源漏极金属信号接入端子所在位置对应的栅绝缘层进行刻蚀，在栅绝缘层上形成过孔结构；或者在栅绝缘层上形成源漏极金属层之后还包括：在源漏极金属信号接入端子所在位置对应的源漏极金属层上形成过孔结构，过孔结构的两侧具有缓和的斜坡。通过对源漏极金属层下方的栅绝缘层进行刻蚀，降低源漏极金属层上方的导电膜层的高度；或者对源漏极金属层进行刻蚀，形成两侧具有缓和斜坡的过孔结构，交替布线中SD基和Gate基上方的ITO高度相同，使得导电球受力更加均匀，提高导线性能。
附图说明
图1为现有技术中Gate层和SD层交替布线的示意图；
图2为现有技术中采用交替布线时Gate层和SD金属层的截面示意图；
图3为现有技术中Gate层和SD金属层交替布线出现接触不良的示意图；
图4是本发明实施例一提供的一种阵列结构的制作方法的流程示意图；
图5为本发明实施例二提供的一种阵列结构的截面示意图；
图6为本发明实施例二中IC引脚与IC Bonding Pad之间通过ACF胶相连的示意图；
图7为本发明实施例二中提供的阵列基板的示意图；
图8为本发明实施例三中采用主孔+补偿孔的设计方式示意图；
图9为本发明实施例三中采用主孔+半透膜的设计方式示意图；
图10为本发明实施例三中源漏极金属层上形成具有斜坡的光刻胶的示意图；
图11为本发明实施例三中主孔中间以及两侧具有斜坡的光刻胶在过孔处的光强分布示意图；
图12为本发明实施例三中湿法刻蚀后得到的结果示意图；
图13为本发明实施例三中干法刻蚀后得到的结果示意图；
图14为本发明实施例三提供的阵列结构的制作方法的步骤流程图；
图15为本发明实施例四提供的阵列结构的截面示意图；
图16为本发明实施例四提供的阵列基板的示意图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
实施例一
本发明实施例提供了一种阵列结构的制作方法，在栅绝缘层上形成源漏极金属层之前还包括：对源漏极金属信号接入端子所在位置对应的栅绝缘层进行刻蚀，在栅绝缘层上形成过孔结构。
该阵列结构的制作方法通过在制作源漏极金属层之前，即进行栅绝缘层(即GIMASK)制作时，将源漏极金属层信号接入端子(即SD Pad)对应位置的栅绝缘层也做同样的MASK处理，经过GI刻蚀之后，消除SD Pad高度的升高，从而降低Gate基和SD基上导电膜层(ITO)的高度差，使连接相邻IC引脚的ITO具有相同的高度，使得导电球受力更加均匀，提高导线性能。
优选地，本实施例中对源漏极金属信号接入端子(SD Pad)所在位置对应的栅绝缘层进行刻蚀之后还包括：在具有过孔结构的栅绝缘层(GI)上方逐层形成源漏极金属层(SD)、钝化层(PVX)以及导电膜层(ITO)。
进一步地，本实施例提供的方法形成源漏极金属层(SD)、钝化层(PVX)以及导电膜层(ITO)之后还包括：对源漏极金属层(SD)在过孔结构所对应的位置进行与过孔结构相同的刻蚀，继续在源漏极金属层(SD)上形成钝化层(PVX)和导电膜层(ITO)，并在过孔结构对应的位置也进行相同的刻蚀。
需要说明的是，最后在导电膜层、钝化层、源漏极金属层以及栅绝缘层上刻蚀得到的过孔依次减小。
对于该方法的步骤流程示意图如图4所示，具体包括以下步骤：
步骤S1、在玻璃基板上形成栅绝缘层；
步骤S2、对栅绝缘层对应SD Pad的位置进行刻蚀，形成过孔结构；
步骤S3、在栅绝缘层和过孔结构上方依次形成SD层和PVX层，并在过孔结构对应的位置进行与过孔结构相同的刻蚀，最后形成ITO层。
上述步骤是对SD基一侧的处理流程，而在Gate基一侧仍然是现有结构，即在玻璃基板形成栅电极层，将Gate基周围的栅电极层刻蚀掉，形成栅电极01，在栅电极上方形成栅绝缘层(GI)，并将Gate基上方的GI层刻蚀形成过孔，然后再依次在GI层上方经过沉积，并在对应过孔位置进行刻蚀，最后形成ITO层。
上述方法通过刻蚀掉栅绝缘层(GI)中源漏极金属信号接入端子(SD Pad)对应的部分，当沉积SD金属层时，使得SD Pad位置处的SD金属层更加紧贴玻璃表面，以缓解由于GI的存在将GI基上方ITO垫高的效果。之后再进行后续图层(即SD层、PVX层和ITO层)的沉积和刻蚀，最后得到的ITO层高度较现有技术有所降低，能够实现降低Gate基和SD基上方ITO层的高度差，保证IC引脚与IC Bonding Pad之间的空间均匀性，两者之间的导电球受力更加均匀，提高导线性能。
实施例二
基于上述阵列结构的制作方法，本发明实施例二还提供了一种阵列结构，截面示意图如图5所示，图5的左侧与图2的左侧相同，都是对Gate基过孔设计，图5的右侧是对SD基进行改进之后的示意图，其中01为Gate层，02为SD层，03为GI层，04为PVX层，05为ITO层。
需要说明的是，IC引脚与IC Bonding Pad之间通过ACF胶(AnisotropicConductive Film，各向异性胶)相连的示意图如图6所示，其中Q1为IC引脚，Q2为ICBonding Pad，07为导电球，IC Bonding Pad下方为TFT基板，用U表示。
另外，基于上述阵列结构，本实施例还提供了一种显示装置，包括阵列基板和彩膜基板，其中的阵列基板是在玻璃基板上形成本发明实施例二中阵列结构得到的。
其中的阵列基板示意图如图7所示，是在玻璃基板00上形成上述的阵列结构。
本实施例提供的阵列基板，能够实现降低Gate基和SD基上方ITO层的高度差，保证IC引脚与IC Bonding Pad之间的空间均匀性，两者之间的导电球受力更加均匀，提高导线性能。
实施例三
本发明实施例三还提供了一种阵列结构的制作方法，在栅绝缘层(GI层)上形成源漏极金属层(SD层)之后还包括：在源漏极金属信号接入端子(SD Pad)所在位置对应的源漏极金属层(SD层)上形成过孔结构，过孔结构的两侧具有缓和斜坡。
该方法是在玻璃基板上形成GI层之后，再沉积一层SD层，之后将SD Pad所在位置对应的SD层刻蚀掉，同样可以降低SD基上ITO层的高度，能够实现降低Gate基和SD基上方ITO层的高度差，保证IC引脚与IC Bonding Pad之间的空间均匀性，两者之间的导电球受力更加均匀，提高导线性能。
优选地，本实施例中形成过孔结构的掩膜包括主孔以及主孔两侧的补偿孔，补偿孔小于主孔，且上述主孔为全透光，补偿孔为非全透光，采用主孔+补偿孔的设计方式示意图如图8所示，其中A为主孔，B1和B2为补偿孔，补偿孔的尺寸一般是远小于曝光机的分辨率的，通过补偿孔能够透过的光可以对中间的主孔透过的光进行叠加和增强，同时主孔的光强能够缓慢降低。
或者形成过孔结构的掩膜包括主孔以及主孔两侧的半透膜，主孔为全透光，所半透膜为非全透光，采用主孔+半透膜的设计方式示意图如图9所示，其中A为主孔，C1和C2为半透膜。
进一步地，半透膜C1和C2包括多级不同透过率的次半透膜，本实施例中是以三级为例，即图9中的C11～C13和C21～C23，并且上述次半透膜从主孔为起始端向两侧逐级递减分布，即C13、C12、C11的透过率是递减的，C23、C22、C21的透过率是也递减的。这种在主孔+半透膜的设计方式能够保证主孔周边的光强并给急转直下，而是逐渐向周围有光强的过渡，即缓和延伸的光强。
优选地，对于上述两种方案都是在源漏极金属层通过湿法刻蚀，形成主孔和补偿孔或主孔和半透膜的过孔结构，之后进一步包括：在源漏极金属层上形成具有斜坡的光刻胶，光刻胶的高度从两侧向主孔逐渐降低，如图10所示。在SD层上方对应SD Pad的光刻胶为空的，向两侧是逐渐增高的斜坡，也就是从两侧向SD Pad对应的位置递减。对于主孔中间以及两侧具有斜坡的光刻胶在过孔处的光强分布如图11所示，其中PR为光刻胶。
涂覆光刻胶之后在进行湿法刻蚀，得到如图12所示的结果。但是本实施例提供的制作工艺是在湿法刻蚀后，还进一步地对光刻胶进行曝光以及对源漏极金属层进行干法刻蚀，由于光刻胶为斜坡形的，在干法刻蚀过程中光刻胶可有刻蚀作用，随着干刻的进行，光刻胶的厚度逐渐降低，最终形成SD层比较缓和的结构，经过附加的干法刻蚀后得到的结果如图13所示。SD层具有缓和的斜坡使得SD Pad形貌于圆球类似，增大了导电球与ITO层的接触面积，也增大了ITO和SD金属的接触面积，导电性更好。
优选地，对源漏极金属层(SD层)进行干法刻蚀之后还包括：在源漏极金属层上形成钝化层(PVX)并在过孔结构对应的位置也进行相同的斜坡刻蚀，最后形成导电膜层(ITO层)。
对于本实施例中提供的步骤流程图如图14所示，具体包括以下步骤：
步骤S1’、在玻璃基板上形成GI层；
步骤S2’、在GI层上形成SD层，并对SD Pad对应位置的SD层进行湿法刻蚀和干法刻蚀，形成过孔结构；
步骤S3’、在SD层上形成PVX层，并在过孔结构对应的位置进行与过孔结构相同的刻蚀，最后形成ITO层。
本实施例中上述提供的也是对SD基上方的各层图形工艺，对于Gate基一侧同实施例一中所述，此处不再赘述。
上述方法通过刻蚀掉栅绝缘层(GI)中源漏极金属信号接入端子(SD Pad)对应的部分，当沉积SD金属层时，使得SD Pad位置处的SD金属层更加紧贴玻璃表面，以缓解由于GI的存在将GI基上方ITO垫高的效果。之后再进行后续图层(即SD层、PVX层和ITO层)的沉积和刻蚀，最后得到的ITO层高度较现有技术有所降低，能够实现降低Gate基和SD基上方ITO层的高度差，保证IC引脚与IC Bonding Pad之间的空间均匀性，两者之间的导电球受力更加均匀，提高导线性能。
实施例四
基于上述阵列结构的制作方法，本发明实施例四还提供了一种阵列结构，截面示意图如图15所示，图15的左侧与图2和图5的左侧相同，都是对Gate基过孔设计，图15的右侧是对SD基进行改进之后的示意图。与图5不同之处在于，图15中并未对GI层进行刻蚀，而是将多余高度的SD层刻蚀。
另外，基于上述阵列结构，本实施例还提供了一种显示装置，包括阵列基板和彩膜基板，其中的阵列基板是在玻璃基板上形成本发明实施例二中阵列结构得到的。其中的阵列基板示意图如图16所示，是在玻璃基板00上形成实施例三提供的阵列结构。
本实施例提供的阵列基板，能够实现降低Gate基和SD基上方ITO层的高度差，保证IC引脚与IC Bonding Pad之间的空间均匀性，两者之间的导电球受力更加均匀，提高导线性能。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (10)

1.一种阵列结构的制作方法，其特征在于，在栅绝缘层上形成源漏极金属层之前还包括：对源漏极金属信号接入端子所在位置对应的栅绝缘层进行刻蚀，在所述栅绝缘层上形成过孔结构；
对源漏极金属信号接入端子所在位置对应的栅绝缘层进行刻蚀之后还包括：在具有过孔结构的栅绝缘层上方逐层形成源漏极金属层；然后对所述源漏极金属层在所述过孔结构所对应的位置进行与所述过孔结构相同的刻蚀，继续在所述源漏极金属层上形成钝化层，在所述钝化层上与所述过孔结构对应的位置进行与所述过孔结构相同的刻蚀，最后形成导电膜层；
所述源漏金属层的上方与栅电极层的上方，用于连接相邻IC引脚的导电膜层高度相同。
2.一种阵列结构，其特征在于，所述阵列结构是通过权利要求1所述的阵列结构制作方法得到的。
3.一种显示装置，包括阵列基板和彩膜基板，其特征在于，所述阵列基板是在玻璃基板上形成权利要求2所述的阵列结构得到的。
4.一种阵列结构的制作方法，其特征在于，在栅绝缘层上形成源漏极金属层之后还包括：在所述源漏极金属信号接入端子所在位置对应的源漏极金属层上形成过孔结构，所述过孔结构的两侧具有缓和斜坡；
在所述源漏极金属层上形成钝化层并在所述钝化层的与所述过孔结构对应的位置进行相同的斜坡刻蚀，在所述过孔结构的底部和两侧形成导电膜层。
5.如权利要求4所述的阵列结构的制作方法，其特征在于，形成所述过孔结构的掩膜包括主孔以及主孔两侧的补偿孔，所述补偿孔小于所述主孔，且上述主孔为全透光，所述补偿孔为非全透光。
6.如权利要求4所述的阵列结构的制作方法，其特征在于，形成所述过孔结构的掩膜包括主孔以及主孔两侧的半透膜，所述主孔为全透光，所述半透膜为非全透光。
7.如权利要求6所述的阵列结构的制作方法，其特征在于，所述半透膜包括多级不同透过率的次半透膜，并且所述次半透膜的透过率从所述主孔为起始端向两侧逐级递减分布。
8.如权利要求5或6所述的阵列结构的制作方法，其特征在于，在所述源漏极金属层通过湿法刻蚀，形成主孔和补偿孔或主孔和半透膜的过孔结构，之后在所述源漏极金属层上形成具有斜坡的光刻胶，所述光刻胶的高度从两侧向所述主孔逐渐降低，并对所述光刻胶进行曝光以及对所述源漏极金属层进行干法刻蚀。
9.一种阵列结构，其特征在于，所述阵列结构是通过权利要求5-8任意一项所述的阵列结构制作方法得到的。
10.一种显示装置，包括阵列基板和彩膜基板，其特征在于，所述阵列基板是在玻璃基板上形成权利要求9所述的阵列结构得到的。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6767754B2 (en) * 1995-05-31 2004-07-27 Fujitsu Display Technologies Corporation Thin film transistor matrix device and method for fabricating the same
CN101393364A (zh) * 2007-09-21 2009-03-25 北京京东方光电科技有限公司 Tft lcd像素结构及其制造方法
CN101621039A (zh) * 2008-07-01 2010-01-06 中华映管股份有限公司 像素结构的制作方法以及像素结构

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3253808B2 (ja) * 1994-07-07 2002-02-04 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JPH10209393A (ja) * 1997-01-22 1998-08-07 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6492190B2 (en) * 1998-10-05 2002-12-10 Sony Corporation Method of producing electrooptical device and method of producing driving substrate for driving electrooptical device
JP3818906B2 (ja) * 2001-12-13 2006-09-06 シャープ株式会社 マイクロコーナーキューブアレイ、その作製方法、および表示装置
KR20040022770A (ko) * 2002-09-07 2004-03-18 엘지.필립스 엘시디 주식회사 액정표시소자의 제조방법
US7372513B2 (en) * 2003-12-30 2008-05-13 Lg.Philips Lcd Co., Ltd. Liquid crystal display device and method for fabricating the same
US20060180569A1 (en) * 2005-02-15 2006-08-17 Chang Hsi-Ming Method of manufacturing step contact window of flat display panel
KR20110061773A (ko) * 2009-12-02 2011-06-10 엘지디스플레이 주식회사 액정표시장치용 어레이 기판 및 그 제조방법
TWI595565B (zh) * 2011-06-17 2017-08-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
CN103560113B (zh) * 2013-11-15 2017-02-01 北京京东方光电科技有限公司 一种阵列结构及其制作方法、阵列基板和显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6767754B2 (en) * 1995-05-31 2004-07-27 Fujitsu Display Technologies Corporation Thin film transistor matrix device and method for fabricating the same
CN101393364A (zh) * 2007-09-21 2009-03-25 北京京东方光电科技有限公司 Tft lcd像素结构及其制造方法
CN101621039A (zh) * 2008-07-01 2010-01-06 中华映管股份有限公司 像素结构的制作方法以及像素结构

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