CN103441146A - 一种恒流二极管芯片 - Google Patents

一种恒流二极管芯片 Download PDF

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CN103441146A
CN103441146A CN2013103464145A CN201310346414A CN103441146A CN 103441146 A CN103441146 A CN 103441146A CN 2013103464145 A CN2013103464145 A CN 2013103464145A CN 201310346414 A CN201310346414 A CN 201310346414A CN 103441146 A CN103441146 A CN 103441146A
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diode chip
mos integrated
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CN103441146B (zh
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钟盛鸣
陆国华
吴亚红
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Jiangsu Xinlong Microelectronics Technology Co ltd
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RUGAO RIXIN ELECTRONIC CO Ltd
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Abstract

本发明公开了一种恒流二极管芯片,主要部件为一个硅片衬底,所述硅片衬底上隔离出两个独立的MOS集成块,所述MOS集成块内为源漏极和栅等距分布的阵列且MOS集成块为4个电极,分别为源漏极和上下两个栅极,所述源漏区的n+掺杂浓度为0.153×18/cm3的高浓度施主杂质掺杂,源漏区通过金属引线与电极连接,所述栅极沟道区域内为0.014×18/cm3的受主杂质掺杂,栅极扩透隔离区,与硅片衬底连接,且栅氧厚度为上下对称的4-6nm。本芯片设计时,源、漏之间的间距决定恒流管的低饱和压降,再根据宽输入的要求在扩散的掺杂度等进行最佳参数的控制,以达到低饱和压降且输入电压范围广,电流变化率低的优点。

Description

一种恒流二极管芯片
技术领域
本发明涉及一种恒流二极管芯片的结构,具体是一种采用栅结构的恒流二极管芯片结构。
背景技术
恒流二极管是近年来问世的半导体恒流器件,它能在很宽的电压范围内输出恒定的电流,并具有很高的动态阻抗。由于它们的恒流性能好、价格较低、使用简便,因此目前已被广泛用于恒流源、稳压源、放大器以及电子仪器的保护电路中。
恒流二极管(CRD)属于两端结型场效应恒流器件。恒流二极管在正向工作时存在一个恒流区,在此区域内IH不随VI而变化;其反向工作特性则与普通二极管的正向特性有相似之处。恒流二极管的外形与3DG6型晶体管相似,但它只有两个引线,靠近管壳突起的引线为正极。
恒流二极管在零偏置下的结电容近似为10pF,进入恒流区后降至30~50pF,其频率响应大致为0~5000kHz。当工作频率过高时,由于结电容的容抗迅速减小,动态阻抗就升高,导致恒流特性变差。
目前市场上常用的技术为螺旋结构的二极管芯片,其缺点具有击穿电压低:上限30V以内。导致适用范围窄。
发明内容
本发明的主要任务在于提供一种恒流二极管芯片,具体是一种低饱和压降、宽输入电压、低电流变化率的恒流二极管芯片。
为了解决以上技术问题,本发明的一种恒流二极管芯片,主要部件为一个硅片衬底,所述硅片衬底上用隔离带隔离出两个独立的MOS集成块,形成双栅,并接为一体,所述MOS集成块内为源、漏极和栅等距分布的阵列,所述MOS集成块为4个电极,分别为源、漏极和上下两个栅极,双栅器件的上下2个栅极同步工作;其创新点在于:所述源漏区的n+掺杂浓度为0.153×18/cm3的高浓度施主杂质掺杂,源漏区通过金属引线与电极连接,所述栅极沟道区域内为0.014×18/cm3的受主杂质掺杂,栅极扩透隔离区,与硅片衬底连接,且栅氧厚度为上下对称的4-6nm。
进一步地,所述源、漏的面积相等。
进一步地,所述栅的面积为源的面积的0.5-3倍。
本发明的优点在于:本芯片设计时,源、漏之间的间距决定恒流管的低饱和压降,再根据宽输入的要求在扩散的掺杂度等进行最佳参数的控制,以达到低饱和压降且输入电压范围广,电流变化率低的优点。
附图说明
图1所示为对芯片制成的251封装形式的恒流管进行的测试。
图2所示为对芯片制成的TO251封装形式的恒流管进行的测试。
具体实施方式
恒流二极管芯片的结构为:在所述硅片衬底1上用隔离带2隔离出独立的MOS集成块3和MOS集成块4,形成双栅,并接为一体。 所述MOS集成块内为源5、漏6和栅7等距分布的阵列,所述MOS集成块为4个电极,分别为源极5a、漏极6a和上栅极7a和下栅极7b,双栅器件的上下2个栅极同步工作。
 在本发明中,源5、漏6区的n+掺杂浓度为0.153×18/cm3的高浓度施主杂质掺杂,源5、漏6区均与金属引线8连接,形成源极5a和漏极6a,且源5、漏6的面积等同。
所述栅7沟道区域内为0.014×18/cm3的受主杂质掺杂,栅7扩透隔离区,与硅片衬底1连接,栅7氧厚度为上下对称的4-6nm且栅7的面积为源5的面积的0.5-3倍。
实施例1
251封装形式的恒流管:
源5、漏6区的n+掺杂浓度为0.153×18/cm3的高浓度施主杂质掺杂,漏源的面积为20×70mm。栅7沟道区域内为0.14×18/cm的受主杂质掺杂,栅7氧厚度为上下对称的4nm且栅7的面积为20×80mm。
对上述芯片制成的251封装形式的恒流管进行以下测试,结果如图1所示:电压在3-5V之间,电流迅速升至20mA,然后,电压继续增大,在5-80V之间,电流问恒定,控制在20-21mA之间。
实施例2
TO220封装形式的恒流管:
源5、漏6区的n+掺杂浓度为0.153×18/cm3的高浓度施主杂质掺杂,漏源的面积为20×70mm。栅7沟道区域内为0.14×18/cm的受主杂质掺杂,栅7氧厚度为上下对称的4nm且栅7的面积为20×80mm。
对上述芯片制成的TO251封装形式的恒流管进行以下测试,结果如图2所示:电压在3-5V之间,电流迅速升至120mA,然后,电压继续增大,在5-80V之间,电流恒定,控制在120-121mA之间。

Claims (3)

1.一种恒流二极管芯片,主要部件为一个硅片衬底,所述硅片衬底上用隔离带隔离出两个独立的MOS集成块,形成双栅,并接为一体,所述MOS集成块内为源漏极和栅等距分布的阵列,所述MOS集成块为4个电极,分别为源漏极和上下两个栅极,双栅器件的上下2个栅极同步工作;其特征在于:所述源漏区的n+掺杂浓度为0.153×18/cm3的高浓度施主杂质掺杂,源漏区通过金属引线与电极连接,所述栅极沟道区域内为0.014×18/cm3的受主杂质掺杂,栅极扩透隔离区,与硅片衬底连接,且栅氧厚度为上下对称的4-6nm。
2.根据权利要求1所述的一种恒流二极管芯片,其特征在于:所述源、漏的面积相等。
3.根据权利要求1所述的一种恒流二极管芯片,其特征在于:所述栅的面积为源的面积的0.5-3倍。
CN201310346414.5A 2013-08-09 2013-08-09 一种恒流二极管芯片 Expired - Fee Related CN103441146B (zh)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1105783A (zh) * 1993-09-29 1995-07-26 精工电子工业株式会社 稳流半导体集成电路器件及其制造方法
JPH0973331A (ja) * 1995-06-30 1997-03-18 Seiko Instr Inc 半導体集積回路装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1105783A (zh) * 1993-09-29 1995-07-26 精工电子工业株式会社 稳流半导体集成电路器件及其制造方法
JPH0973331A (ja) * 1995-06-30 1997-03-18 Seiko Instr Inc 半導体集積回路装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
陈凯良: "《恒流源及其应用电路》", 31 August 1992, 浙江科学技术出版社 *

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