CN103367310B - 互连结构及其形成方法 - Google Patents

互连结构及其形成方法 Download PDF

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CN103367310B
CN103367310B CN201210258769.4A CN201210258769A CN103367310B CN 103367310 B CN103367310 B CN 103367310B CN 201210258769 A CN201210258769 A CN 201210258769A CN 103367310 B CN103367310 B CN 103367310B
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adhesion coating
layer
dielectric
dielectric layer
adhesion
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CN103367310A (zh
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施伯铮
彭羽筠
周家政
刘中伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

公开了互连结构及其形成方法。互连结构包括形成在介电层中的导电层。粘着层形成在介电层和衬底之间。粘着层的碳含量比大于介电层的碳含量比。

Description

互连结构及其形成方法
相关申请的交叉参考
本申请要求于2012年3月29日提交的美国临时专利申请第61/617，530号的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及半导体器件，具体涉及铜互连件及其制造方法。
背景技术
半导体器件用于各种电子应用中，比如个人电脑、移动电话、数码相机和其他电子设备。随着技术进步，对具有改善性能的更小的半导体器件的需求增加。随着半导体器件中的部件密度增加，导线的宽度以及半导体器件中的后端工艺(BEOL)互连结构的导线之间的间隔也需要按比例缩小。
为了满足这些需求，已经实施了若干方法。当导线的宽度减小时，具有导线的两个连续层之间的间隔也减小了。减小的间隔因而可能增加电阻电容(RC)时间延迟。为了降低RC时间延迟，低介电常数(低k)材料用作绝缘材料，并且铜替换铝用于互连结构。因为与铝相比，铜具有更低的电阻率和增大的电迁移电阻，采用铜用于半导体器件互连件的优势包括能够更快速地操作以及制造出更薄的导线。举例来说，将铜互连件和低k介电材料结合起来通过降低RC时间延迟来增加互连速度。
通常采用镶嵌工艺而不是通过直接蚀刻来形成铜互连件。镶嵌工艺通常是单镶嵌或双镶嵌，其包括通过图案化和蚀刻金属间介电(IMD)层形成开口以及用铜填充开口。但是，在铜镶嵌结构中存在一些挑战，比如低k介电材料和下层之间的粘着问题。粘着问题可能导致膜开裂和/或剥离，从而导致器件封装件质量不合格。
发明内容
为了解决上述技术问题，一方面，本发明提供了一种器件，包括：衬底；粘着层，位于所述衬底上方，所述粘着层具有第一碳含量比；介电层，位于所述粘着层上方，所述介电层具有第二碳含量比，所述第一碳含量比大于所述第二碳含量比；以及导体，位于所述介电层中。
在所述的器件中，所述第一碳含量比大于13at％(原子百分比)。
在所述的器件中，所述第一碳含量比在约15at％至约30at％的范围内。
在所述的器件中，所述第二碳含量比小于13at％。
在所述的器件中，所述第二碳含量比在约10at％至约13at％的范围内。
所述的器件还包括位于所述粘着层下方的含SiOx层、含SiCN层或含SiON层。
所述的器件还包括位于所述粘着层下方的含SiOx层、含SiCN层或含SiON层，以及设置在所述衬底和所述含SiOx层、所述含SiCN层或所述含SiON层之间的第一蚀刻终止层。
在所述的器件中，所述粘着层和所述含SiOx层、所述含SiCN层或所述含SiON层之间的粘着强度约为14J/m2以上。
所述的器件还包括位于所述介电层和所述导体上方的第二蚀刻终止层。
在所述的器件中，所述介电层的介电常数和所述粘着层的介电常数之间的差值小于约2％。
在所述的器件中，所述介电层的厚度在约5埃至约300埃的范围内。
另一方面，本发明提供了一种半导体器件，包括：半导体衬底；第一粘着层，位于所述半导体衬底上方；第二粘着层，位于所述第一粘着层上方，其中，所述第二粘着层包含C、Si或O；低k介电层，位于所述第二粘着层上方，其中，所述低k介电层包含C、Si或O，其中，所述低k介电层中的碳的原子百分比小于所述第二粘着层中的碳的原子百分比；以及导体，位于所述介电层、所述第二粘着层和所述第一粘着层中。
在所述的半导体器件中，所述低k介电层中的碳的原子百分比在约10at％至约13at％的范围内。
在所述的半导体器件中，所述第二粘着层中的碳的原子百分比在约15at％至约30at％的范围内。
在所述的半导体器件中，所述第二粘着层的介电常数与所述低k介电层的介电常数基本相同。
在所述的半导体器件中，所述第二粘着层的介电常数在约2.5至约2.8的范围内。
在所述的半导体器件中，所述第一粘着层和所述第二粘着层之间的粘着强度等于或大于约14J/m2。
又一方面，本发明提供了一种方法，包括：在衬底上方形成第一粘着层；在所述第一粘着层上方形成第二粘着层，其中，在第一RF功率下采用具有第一流速的惰性气体形成所述第二粘着层；在所述第二粘着层上方形成低k介电层，其中，在以下两个条件中的至少一个条件下在第二RF功率下采用具有第二流速的惰性气体形成所述低k介电层：1)所述第二流速不同于所述第一流速；以及2)所述第二RF功率不同于所述第一RF功率；在所述介电层、所述第二粘着层和所述第一粘着层中形成开口；以及在所述开口中形成导体。
在所述的方法中，所述第二流速大于所述第一流速。
在所述的方法中，所述第二RF功率大于所述第一RF功率。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，对各种部件没有被按比例绘制并且仅用于举例说明的目的。实际上，为了清楚的论述，各种部件的尺寸可以被任意增大或减小。
图1是根据本发明的实施例用于制造集成电路器件的方法的流程图。
图2至图7是根据本发明的实施例根据图1的方法在各个制造阶段的集成电路器件的截面图。
具体实施方式
应当理解为了实施本发明的不同部件，以下公开内容提供了许多不同的实施例或实例。在下面描述元件和布置的特定实例以简化本发明。当然这些仅是实例并不打算用于限定。例如，在下面的描述中第一部件在第二部件上方或者在第二部件上的形成可以包括其中第一和第二部件以直接接触形成的实施例，并且也可以包括其中可以在第一和第二部件之间形成额外的部件，使得第一和第二部件可以不直接接触的实施例。另外，本发明可以在各个实例中重复附图标号和/或字母。这种重复只是为了简明和清楚的目的且其本身并不一定指定所论述的各个实施例和/或结构之间的关系。
参照图1和图2至图7，在下面共同描述了方法100和半导体器件200。半导体器件200示出集成电路或其一部分，其可以包括存储器单元和/或逻辑电路。半导体器件200可以包括无源元件，比如电阻器、电容器、电感器和/或熔丝；以及有源元件，比如P沟道场效应晶体管(PFET)、N沟道场效应晶体管(NFET)、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体晶体管(CMOS)、高电压晶体管和/或高频晶体管、其他合适的元件和/或它们的组合。可以理解，可以在方法100之前、期间和/或之后实施其他步骤，并且对于方法的其他实施例，可以替换或去除下面描述的一些步骤。还可以理解，其他部件可以加入到半导体器件200中，并且对于半导体器件200的其他实施例，可以替换或去除下面描述的一些部件。
参照图1和图2，方法100开始于步骤102，其中在衬底210上方形成第一蚀刻终止层(ESL)200。在该实施例中，衬底210是包含硅的半导体衬底。在一些可选的实施例中，衬底210包含元素半导体，包括晶体形式的硅和/或锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP；或它们的组合。合金半导体衬底可以具有梯度SiGe部件，其中Si和Ge成分从梯度SiGe部件的一个位置的一个比率变成另一位置的另一比率。可以在硅衬底上方形成合金SiGe。SiGe衬底可以是应变的。此外，半导体衬底可以是绝缘体上半导体(SOI)。在一些实施例中，半导体衬底可以包括掺杂的外延层。在其他实施例中，硅衬底可以包括多层化合物半导体结构。
取决于设计要求，衬底210可以包括各种掺杂区(例如，p型阱或n型阱)。掺杂区可以掺杂有p型掺杂物，比如硼或BF2；n型掺杂物，比如磷或砷；或它们的组合。可以直接在衬底210中、P阱结构中、N阱结构中、双阱结构中或者采用凸起的结构形成掺杂区。半导体器件200可以包括P沟道场效应晶体管(PFET)器件和/或N沟道场效应晶体管(NFET)器件。因此，衬底210可以包括配置用于PFET器件和/或NFET器件的各种掺杂区。
在上述衬底210上沉积第一蚀刻终止层220，其用于在后续蚀刻工艺过程中控制终点。在一些实施例中，第一蚀刻终止层220包括含有C、Si、N或H的材料。在一些实施例中，第一蚀刻终止层220由氧化硅、氮化硅、碳化硅、氮氧化硅或它们的组合形成。在一些实施例中，第一蚀刻终止层220的厚度是约10埃至约1000埃。在一些实施例中，通过包括低压化学汽相沉积(LPCVD)、大气压化学汽相沉积(APCVD)、等离子体增强化学汽相沉积(PECVD)、物理汽相沉积(PVD)、溅射和将来开发的沉积步骤的各种沉积技术中的任意一种来形成第一蚀刻终止层220。在一些可选的实施例中，通过热工艺形成第一蚀刻终止层220。在一些实施例中，第一蚀刻终止层220的厚度在约100埃至约300埃的范围内。
参照图1和图3，方法100继续到步骤104，其中在第一蚀刻终止层220上方形成第一粘着层230。在一些实施例中，第一粘着层230包含含SiOx材料、含SiCN材料、含SiON材料或它们的组合。在一些实施例中，采用LPCVD工艺、APCVD工艺、PECVD工艺、PVD工艺、溅射或将来开发的沉积步骤形成第一粘着层230。在一些可选的实施例中，采用热工艺形成第一粘着层230。在该实施例中，第一粘着层230是四乙氧基硅烷(TEOS)。在一些实施例中，第一粘着层230的厚度在约100埃至约400埃的范围内。
参照图1和图4，方法100继续到步骤106，其中在第一粘着层230上方形成第二粘着层240。在一些实施例中，采用LPCVD工艺、APCVD工艺、PECVD工艺、PVD工艺、溅射或将来开发的沉积步骤形成第二粘着层240。在一些可选实施例中，采用热工艺形成第二粘着层240。在一些实施例中，第二粘着层240包括含有Si、C、O或H的材料。在一些实施例中，第二粘着层240是基本组分(base composition)中碳含量(C含量)比大于13at％(原子百分比)的含C层。在一些可选的实施例中，第二粘着层240是基本组分中碳含量(C含量)比在约15at％至约30at％的范围内的含C层。在一些实施例中，第二粘着层240的厚度在约5埃至约300埃的范围内。
仍然参照图1和图4，方法100继续到步骤108，其中在第二粘着层240上方形成介电层250。介电层250可以是单层或多层结构。在一些实施例中，采用诸如PECVD工艺、LPCVD工艺的CVD工艺或ALD工艺形成介电层250。在一些实施例中，介电层250包含含有Si、C、O或H的材料。在一些实施例中，介电层250包含与第二粘着层240相同的元素，但是C含量比低于第二粘着层240的C含量比。在一些实施例中，介电层250是C含量比小于13at％的含C层。在一些可选的实施例中，介电层250是C含量比在约10at％至13at％的范围内的含C层。在一些实施例中，介电层250的厚度在约300埃至约2500埃的范围内。
在一些实施例中，通过PECVD连续地形成第二粘着层240和介电层250。在一些实施例中，第二粘着层240和介电层250采用至少一种前体，比如四甲基环四硅氧烷(TMCTS)、八甲基环四硅氧烷(OMCTS)、二乙氧基甲基硅烷(DEMS)、二乙氧基二甲基硅烷(DEDMS)和其他有关的环状和非环状硅烷和硅氧烷。在一些实施例中，前体可以与诸如He或Ar的惰性气体和/或诸如H2O、O2和/或CO2的反应气体一起使用。在一些实施例中，采用相同前体和惰性气体通过PECVD连续地形成第二粘着层240和介电层250。在一些实施例中，采用相同前体和惰性气体但是采用不同的惰性气体流速和/或不同的RF功率通过PECVD连续地形成第二粘着层240和介电层250。在一些实施例中，用于形成第二粘着层240的惰性气体的流速大于用于形成介电层250的惰性气体的流速。在一些可选的实施例中，形成第二粘着层240所采用的RF功率大于形成介电层250所采用的RF功率。在至少一个实施例中，用于形成第二粘着层240的惰性气体的流速大于用于形成介电层250的惰性气体的流速并且用于形成第二粘着层240的RF功率大于用于形成介电层250的RF功率。
在一些实施例中，介电层250是介电常数小于3.0的低介电常数(低k)层并且用作金属间介电(IMD)层。在一些实施例中，介电层250是介电常数在约2.5至约2.8范围内的低k层。根据一些实施例，可以使用广泛多种低k材料，例如旋涂无机电介质、旋涂有机电介质、多孔介电材料、有机聚合物、有机硅玻璃、SiOF系列材料(FSG)、氢倍半硅氧烷(HSQ)系列材料、甲基倍半硅氧烷(MSQ)系列材料或多孔有机系列材料。
在一些实施例中，第二粘着层240的介电常数与介电层250的介电常数基本相同。在一些可选的实施例中，第二粘着层240的介电常数略微大于介电层250的介电常数，例如，介电常数的差值小于2％。在一些实施例中，第二粘着层240充当粘结促进层以提高介电层250和第一粘着层230之间的粘着性。通过采用第二粘着层240可以获得的测量粘结值约为14J/m2以上。所测量的粘结值比介电层250和第一粘着层230之间无其他粘着层的粘结值约高7％以上。
参照图1和图5，方法100继续到步骤110，其中在介电层250中形成开口260。在一些实施例中，形成穿过介电层250、第二粘着层240、第一粘着层230和第一蚀刻终止层220的开口260。在一些实施例中，开口260是用于限定接触区的包括上沟槽部260a和下通孔部260b的双镶嵌开口。虽然实施例示出了位于介电层250中的双镶嵌开口，但本申请中公开的方法适用于在IMD层中具有单镶嵌开口的实施例。在包括“先通孔”图案化方法或“先沟槽”图案化方法的双镶嵌技术中，可以采用典型的光刻与掩模技术和各向异性蚀刻操作(例如，等离子体蚀刻或反应离子蚀刻)形成上沟槽部260a和下通孔部260b。可以任选地在介电层250上或在介电层250中间沉积底部蚀刻终止层、中部蚀刻终止层、抛光终止层或抗反射涂层(ARC)，在结束具体蚀刻工艺时提供明确的指示。
参照图1和图6，方法100继续到步骤112，其中在开口260中形成导体270。在一些实施例中，通过沉积工艺例如电化学镀(ECP)形成导体270。在一些实施例中，导体270包含至少一种主要金属元素，例如铜(Cu)。在一些可选的实施例中，导体270还包含不同于主要金属元素的添加金属元素，比如铝。
仍然参照图6，在形成导体270之前，可以沉积阻挡层(未示出)作为开口260的侧壁的衬垫。在一些实施例中，阻挡层包含Ti、TiN、Ta、TaN、其他适当的材料或它们的组合。在形成导体270之前，还可以在阻挡层上方形成导电晶种层(未示出)。在至少一个实施例中，导电晶种层是包含至少一种主要金属元素例如铜(Cu)的金属合金层。在至少一个实施例中，通过采用PVD、CVD、PECVD、LPCVD或其他公知的沉积技术形成导电晶种层。在形成导体270之后，可以实施化学机械抛光(CMP)工艺以去除导体270位于介电层250上方的多余部分，因而暴露介电层250的顶面并实现平坦化的表面。
参照图1和图7，方法100继续到步骤114，其中在上述平坦化的表面上形成第二蚀刻终止层280。第二蚀刻终止层280可以控制后续蚀刻工艺过程中的终点。第二蚀刻终止层280可以由氧化硅、氮化硅、碳化硅、氮氧化硅或它们的组合形成，厚度为约10埃至约1000埃，第二蚀刻终止层280可以通过包括LPCVD、APCVD、PECVD、PVD、溅射和将来开发的沉积步骤的各种沉积技术中的任意一种形成。
总的来说，所公开的方法和集成电路器件引起改善的器件性能，包括但不限于提高IMD层和下层之间的粘着性，并因而可以抑制剥离问题。而且，其通过在封装工艺期间防止剥离来提高封装能力。
在至少一个实施例中，一种器件包括衬底；位于衬底上方的具有第一碳含量比的粘着层；位于粘着层上方的具有第二碳含量比的介电层；以及位于介电层中的导体。第一碳含量比大于第二碳含量比。
在另一实施例中，一种半导体器件包括半导体衬底；位于半导体衬底上方的第一粘着层；位于第一粘着层上方的第二粘着层；位于第二粘着层上方的低k介电层；以及位于介电层、第二粘着层和第一粘着层中的导体。第二粘着层和低k介电层包含C、Si、O元素。低k介电层中C的原子百分比小于第二粘着层中C的原子百分比。
在又一实施例中，一种方法包括在衬底上方形成第一粘着层；在第一粘着层上方形成第二粘着层；在第二粘着层上方形成低k介电层；在介电层、第二粘着层和第一粘着层中形成开口；以及在开口中形成导体。在第一RF功率下采用具有第一流速的惰性气体形成第二粘着层。在第二RF功率下采用具有第二流速的惰性气体形成低k介电层。第二流速不同于第一流速或者第二RF功率不同于第一RF功率。
尽管已经描述了实施例，但本发明预期并不限于本文中公开的具体实施例。本领域的技术人员在不背离本发明的范围和精神的情况下，可以进行各种变化以及改变。因而，本发明的范围应该由权利要求和它们的等效物进行限定和保护。

Claims (20)

1.一种半导体器件，包括：
衬底；
粘着层，位于所述衬底上方，所述粘着层具有第一碳含量比；
介电层，位于所述粘着层上方并且与所述粘着层直接接触，所述介电层具有第二碳含量比，所述第一碳含量比大于所述第二碳含量比；以及
导体，位于所述介电层中。
2.根据权利要求1所述的器件，其中，所述第一碳含量比大于13at％(原子百分比)。
3.根据权利要求1所述的器件，其中，所述第一碳含量比在15at％至30at％的范围内。
4.根据权利要求1所述的器件，其中，所述第二碳含量比小于13at％。
5.根据权利要求1所述的器件，其中，所述第二碳含量比在10at％至13at％的范围内。
6.根据权利要求1所述的器件，还包括位于所述粘着层下方的含SiOX层、含SiCN层或含SiON层。
7.根据权利要求6所述的器件，还包括设置在所述衬底和所述含SiOX层、所述含SiCN层或所述含SiON层之间的第一蚀刻终止层。
8.根据权利要求6所述的器件，其中，所述粘着层和所述含SiOX层、所述含SiCN层或所述含SiON层之间的粘着强度为14J/m2以上。
9.根据权利要求1所述的器件，还包括位于所述介电层和所述导体上方的第二蚀刻终止层。
10.根据权利要求1所述的器件，其中，所述介电层的介电常数和所述粘着层的介电常数之间的差值小于2％。
11.根据权利要求1所述的器件，其中，所述介电层的厚度在5埃至300埃的范围内。
12.一种半导体器件，包括：
半导体衬底；
第一粘着层，位于所述半导体衬底上方；
第二粘着层，位于所述第一粘着层上方，其中，所述第二粘着层包含C、Si或O；
低k介电层，位于所述第二粘着层上方并且与所述第二粘着层直接接触，其中，所述低k介电层包含C、Si或O，其中，所述低k介电层中的碳的原子百分比小于所述第二粘着层中的碳的原子百分比；以及
导体，位于所述介电层、所述第二粘着层和所述第一粘着层中。
13.根据权利要求12所述的半导体器件，其中，所述低k介电层中的碳的原子百分比在10at％至13at％的范围内。
14.根据权利要求12所述的半导体器件，其中，所述第二粘着层中的碳的原子百分比在15at％至30at％的范围内。
15.根据权利要求12所述的半导体器件，其中，所述第二粘着层的介电常数与所述低k介电层的介电常数基本相同，所述第二粘着层的介电常数介电常数与所述低k介电层的介电常数之间的差值小于2％。
16.根据权利要求12所述的半导体器件，其中，所述第二粘着层的介电常数在2.5至2.8的范围内。
17.根据权利要求12所述的半导体器件，其中，所述第一粘着层和所述第二粘着层之间的粘着强度等于或大于14J/m2。
18.一种形成半导体器件的方法，包括：
在衬底上方形成第一粘着层；
在所述第一粘着层上方形成第二粘着层，其中，在第一RF功率下采用具有第一流速的惰性气体形成所述第二粘着层；
在所述第二粘着层上方形成低k介电层，并且所述低k介电层与所述第二粘着层直接接触，其中，在以下两个条件中的至少一个条件下在第二RF功率下采用具有第二流速的惰性气体形成所述低k介电层：
1)所述第二流速不同于所述第一流速；以及
2)所述第二RF功率不同于所述第一RF功率；
在所述介电层、所述第二粘着层和所述第一粘着层中形成开口；以及
在所述开口中形成导体。
19.根据权利要求18所述的方法，其中，所述第二流速大于所述第一流速。
20.根据权利要求18所述的方法，其中，所述第二RF功率大于所述第一RF功率。
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