CN103367289A - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

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CN103367289A
CN103367289A CN2012102560850A CN201210256085A CN103367289A CN 103367289 A CN103367289 A CN 103367289A CN 2012102560850 A CN2012102560850 A CN 2012102560850A CN 201210256085 A CN201210256085 A CN 201210256085A CN 103367289 A CN103367289 A CN 103367289A
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connection pad
semiconductor package
copper
closing line
protective layer
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李达钧
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明公开一种半导体封装结构，其包括一基板、一半导体元件、一保护层、一接合线以及一封装胶体。基板具有一接垫以及一焊罩层，且接垫自焊罩层暴露。半导体元件配置于基板上。保护层配置于接垫上。接合线连接半导体元件至接垫。接合线的一端贯穿保护层且与接垫的一表面的一部分接合以形成一接合区。保护层除了接合区外覆盖接垫的全部表面。封装胶体覆盖半导体元件、接垫与接合线。

Description

半导体封装结构
技术领域
本发明涉及一种半导体封装结构，且特别是涉及一种半导体封装结构的打线接合（wire bonding）。
背景技术
打线接合是将半导体芯片与基板，例如是印刷电路板（printed circuitboard,PCB）或导线架（lead frame）电连接。常见地，有机保焊剂(OrganicSolderability Preservative，OSP)材料配置于接垫上以防止接垫表面氧化。在传统制作工艺中，有机材料形成于裸露的接垫上以保护接垫不被氧化。当欲接近接垫时，有机材料会从接垫上被移除。然而，在移除有机材料之后，接垫的表面被暴露出来且当它与外界元素，如水气，产生反应时可能会立即被氧化。此将导致后续焊接或接合制作工艺焊接性（solderability）不良。或者是，导电镍-金层可被使用，但所需的材料成本较高因为金很贵。
发明内容
为解决上述问题，本发明的一态样是关于一半导体封装结构。半导体封装结构包括一半导体元件；一基板，包括一接垫且接垫上具有一保护层；一接合线，连接半导体元件至接垫，其中接合线的末端贯穿保护层而与接垫的一表面的一部分接合而形成一接合区；以及一封装胶体，覆盖半导体元件、接垫以及接合线。接垫自一焊罩层暴露且除了接合区外实质上被保护层完全覆盖。在一实施例中，接合线与接垫为铜，且介于接合线贯穿保护层的一端与接垫之间的一接合为一铜-铜接合。于另一实施例中，接合线为镀钯的铜导线，且铜-钯-铜介金属(copper-palladium-copper intermetallic)区位于接合区内。在另一实施例中，接合线可为一金导线。保护层可包括一导电有机金属材料，例如是一电性导电聚合物以及多个贵金属颗粒（例如是纳米级银颗粒）的一组合。有机材料赋予一可看见的涂布，便于检查，以确保可视觉地视察的表面加工。或者是，保护层可包括一陶瓷纳米涂层。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1为本发明一实施例的一种半导体封装结构的一部分的膜层的剖面示意图；
图2为镀钯的铜导线与接垫的接合区的局部放大示意图；
图3为图1的耦接元件的接合至接垫的不连续的放大透视示意图。
主要元件符号说明
100：半导体封装结构
102：基板
104：半导体元件
106：保护层
108：接合线
110：封装胶体
112：接垫
112a：第一区
112b：第二区
114：焊罩层
116：第二端部
118：接合区
119：空孔
具体实施方式
请参考图1，其显示依据本发明的一实施例的一半导体封装结构100。半导体封装结构100包括一基板102、一半导体元件104、一保护层106、一接合线108以及一封装胶体110。
基板102上表面具有一接垫112以及一焊罩层114，其中接垫112自焊罩层114暴露。接垫112的材质主要为铜。接垫112通过基板102的内层导电电路（未示于图中）连接至基板102下表面的接垫（未示于图中）。基板102下表面的接垫可设有锡球（未示于图中）用以进一步连接至一外部印刷电路板（未示于图中）。
半导体元件104配置于基板102上。保护层106配置于接垫112上。于一实施例中，保护层106包括一电性上导电有机金属材料。有机金属材料可包括一电性导电聚合物与多个贵金属颗粒（例如是纳米级银颗粒）的一组合，其可使接垫112的表面改质或钝化，提升接垫112表面的氧化电位，以降低与/或防止表面氧化。此外，有机金属材透赋予一个可见的涂层，便于检查，以确保视觉地视察的表面加工，准备组装。另外，有机金属材料提供一高导电表面处理以给予电路裸板测试电路后直接使用。因此，在电路板组装时需要粘贴的测试点被淘汰。
当然，保护层106也可包括一电性上非导电材料，例如是陶瓷纳米涂层，其排斥水但保留了可被电连接器或打线接合贯穿的能力。
接合线108电连接半导体元件104至接垫112。接合线108可以是主要材质为铜的铜导线，例如裸铜导线（Bare Cu Wire）、镀钯的铜导线（PalladiumCoated Cu Wire），或者是主要材质为金的金导线。
接合线108具有一第一端部以及一第二端部116，其中第一端部与半导体元件104的接垫接合，第二端部116贯穿保护层106而接合至接垫112的一表面的一部分，以形成一接合区118。于一实施例中，若接合线108为铜导线，则可在接垫112的表面与接合线108之间形成具有铜-铜接合界面。铜-铜接合界面是由铜接垫和铜接合线之间的原子扩散所形成。于另一实施例中，若接合线108为一金导线，多层铜-金合金层形成于接垫112的表面与接合线108之间。
在另一实施例中，若接合线108为一镀钯的铜导线，则可在接垫112的表面与接合线108之间形成铜-钯-铜介金属（copper-palladium-copperintermetallic）区。请参考图2，一连续的钯层形成于接垫112的表面与接合线108之间。
值得注意的是，保护层106覆盖接垫112的全部表面，除了接合区118之外，其中接合区118例如是铜-铜接合界面、铜-钯-铜介金属区或铜-金合金层。请参考图3，保护层106覆盖一第一区112a与一第二区112b，其中第一区112a环绕接合区118，而第二区112b被接合区118所环绕。此外，保护层106具有一空孔119（请参考图1），其中空孔119是由接合线108的另一端部116的贯穿保护层106所产生。接合线108通过空孔119接合至接合区118，且铜-铜接合界面、铜-钯-铜介金属区或铜-金合金层形成于在空孔119的位置。封装胶体110覆盖半导体元件104、接垫112以及接合线118。
在进行打线接合制作工艺前，在接垫112上的保护层106大致完整无损的。于打线接合制作工艺中，接合线108穿过保护层106且接合至接垫112，但未打线的表面仍为保护层106所覆盖与保护。详言之，在第二端接合制作工艺，打线接合所使用的工具(例如是一“焊嘴(capillary)”)被移动至第二端接合的位置且停留在有保护层106的接垫112表面上。接着，通过焊嘴传递的超音波能量自接垫表面擦除保护层106并产生一介于接合线108的第二端部116与接垫112之间的冶金接合（metallurgical bond）。于其他实施例中，焊嘴可不用从接垫表面完全地擦除保护层106，而在接合区形成一不连续的残余层。此残余层主要包括未蒸发颗粒，例如是银颗粒（在有机金属材料内）、硅或铝（在陶瓷纳米涂层材料内）。
虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应以附上的权利要求所界定的为准。此外，许多修改可使一事件、方法或过程的特殊情况、材料或合成物来适应本发明的宗旨、精神和范围。这一类的修改也被预期为可能在附加的权利要求中的一些项中陈述。特别是，于此中被揭露的方法描述了关于按特殊顺序进行的特殊操作，这些操作也许可被结合、被细分或者被重新调整而形成一个等效方法，此仍不脱离本发明所教示的范围内。因此，除非此文中明确地说明，否则顺序和编组操作非用以限定本发明。

Claims (20)

1.一种半导体封装结构，包括：
半导体元件；
基板，包括接垫，且该接垫上具有保护层；
接合线，连接该半导体元件至该接垫，其中该接合线的一端贯穿该保护层而与该接垫的一表面的一部分接合以形成一接合区；以及
封装胶体，包覆该半导体元件、该接垫以及该接合线。
2.如权利要求1所述的半导体封装结构，其中该接垫自一焊罩层暴露，且该接垫除了该接合区外实质上被该保护层完全覆盖。
3.如权利要求1所述的半导体封装结构，其中在该接垫上的打线接合为铜-铜接合。
4.如权利要求1所述的半导体封装结构，其中该保护层包括具有多个金属颗粒的导电有机材料。
5.如权利要求4所述的半导体封装结构，其中该导电有机材料包括一电性导电聚合物以及多个贵金属颗粒的一组合。
6.如权利要求1所述的半导体封装结构，其中该保护层包括陶瓷纳米涂层。
7.如权利要求1所述的半导体封装结构，其中该接合线为镀钯的铜导线。
8.如权利要求1所述的半导体封装结构，其中该接合区包括铜-钯-铜介金属。
9.如权利要求1所述的半导体封装结构，其中该接合线包括金导线。
10.如权利要求9所述的半导体封装结构，其中多层铜-金合金层形成于该接垫与该接合线之间。
11.一种半导体封装结构，包括：
基板，包括至少一接垫，其中该接垫的材质主要为铜；
半导体元件，配置于该基板上；
接合线，连接该半导体元件至该接垫，其中该接合线的材质主要为铜；
铜-铜接面，形成于该接垫与该接合线之间；
保护层，除了介于该接垫与该接合线之间的一接合区外实质上完全覆盖该接垫的表面；以及
封胶体，包覆该半导体元件、该接垫以及该接合线。
12.如权利要求11所述的半导体封装结构，其中该保护层包括具有多个金属颗粒的导电有机材料。
13.如权利要求12所述的半导体封装结构，其中该导电有机材料包括一电性导电聚合物以及多个贵金属颗粒的一组合。
14.如权利要求11所述的半导体封装结构，其中该铜-铜接面包括介金属区。
15.如权利要求11所述的半导体封装结构，其中该保护层包括陶瓷纳米涂层。
16.一种半导体封装结构，包括：
基板，包括接垫，其中该接垫的材质主要为铜；
镀钯的铜导线，耦接至该接垫并在该接垫上定义一接合区；
保护材料，环绕该接合区；以及
铜-钯-铜介金属区，位于该接合区内。
17.如权利要求16所述的半导体封装结构，其中该保护层包括具有多个金属颗粒的导电有机材料。
18.如权利要求17所述的半导体封装结构，其中该导电有机材料包括一电性导电聚合物以及多个贵金属颗粒的一组合。
19.如权利要求16所述的半导体封装结构，其中该保护材料钝化该接垫以降低氧化。
20.如权利要求16所述的半导体封装结构，其中该保护材料包括陶瓷纳米涂层。
CN2012102560850A 2012-04-06 2012-07-23 半导体封装结构 Pending CN103367289A (zh)

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Application publication date: 20131023