CN103367179B - 打线方法 - Google Patents

打线方法 Download PDF

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CN103367179B
CN103367179B CN201210088144.8A CN201210088144A CN103367179B CN 103367179 B CN103367179 B CN 103367179B CN 201210088144 A CN201210088144 A CN 201210088144A CN 103367179 B CN103367179 B CN 103367179B
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plastic material
routing
bonding wire
pin
weld pad
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CN103367179A (zh
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陈逸男
徐文吉
叶绍文
刘献文
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Nanya Technology Corp
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Abstract

本发明公开了一种打线方法，包含：(1)将芯片置于一承载件上；(2)将塑性材料点于所述芯片上，其中所述塑性材料位于所述芯片的打线焊垫与所述承载件的引脚间；(3)打线于所述打线焊垫与所述引脚上，使焊线连接于所述打线焊垫与所述引脚间，并埋入所述塑性材料中。本发明所提出的打线方法，可在打线过程中使焊线立即被塑性材料所包埋及固定，因此可避免在打线过程中因振动造成的焊线互碰短路，可提高制作工艺良率。

Description

打线方法
技术领域
本发明涉及一种打线方法，具体涉及一种将焊线埋入塑性材料的打线方法。
背景技术
随着电子构装朝向高容量、高密度及轻巧化的趋势发展，在更小的体积内须满足更多的功能需求及增加更多输出/输入数，当芯片的打线焊垫的尺寸及间距被设计的更小，打线也必须选择更细的焊线。目前业界最常使用的0.9(mil，千分之英时)焊线，已无法使用在50×50(um，微米)以下的芯片的打线焊垫上，0.8(mil，千分之英时)以下的焊线已渐渐成为现今打线制作工艺的主流。
然而，小线径焊线对长距离打线是一大挑战。线径变小焊线更轻更软，在拉线的过程中焊线容易受震动产生焊线飘移，造成焊线偏移或焊线互碰短路，整体封装制品因此产生制作工艺缺陷，其不良率会提升。
公知技艺中有一种打线后进行点胶包埋焊线的方法，使焊线包埋在塑性材料中而受到保护，以解决小线径焊线对长距离打线所造成的问题。如图1所示，焊线10被包埋在塑性材料20中而受到塑性材料20的保护，方法是在打线形成焊线10后再点上塑性材料20固定。
然而，此种作法只能避免封装时，塑料充填过程中的拖曳力对焊线的破坏，但无法避免在打线的过程中的焊线偏移以及焊线互碰短路的问题。并且，由于塑性材料20本身具有重量及黏性，将其点胶于细焊线10上时，会破坏已打好的焊线线弧，甚至压垮焊线10而造成短路或断线。再者，点胶于焊线10上的塑性材料20也会因毛细现象而在焊线10间自由流动。如此，不但不易控制塑性材料20涂布的形状，也容易将气泡包覆于塑性材料20中。另外，塑性材料20中的气泡更会使封装体在后续可靠度测试時，造成脱层而失效。
发明内容
本发明的目的在于提供一种打线方法，先点塑性材料于芯片上，再打线于打线焊垫与引脚上，使焊线在打线时一起埋入塑性材料中。如此，避免打线、点上塑性材料或封装的过程中造成焊线破坏或焊线移动，而能提高良率。
为达上述目的，本发明提供一种打线方法，包含：(1)将芯片置于一承载件上；(2)将塑性材料点于所述芯片上，其中所述塑性材料位于所述芯片的打线焊垫与所述承载件的引脚间；(3)打线于所述打线焊垫与所述引脚上，使焊线连接于所述打线焊垫与所述引脚间，并埋入所述塑性材料中。
进一步的，上述塑性材料为高分子塑性材料。
进一步的，在上述步骤(3)后，包括：硬化所述塑性材料。
进一步的，上述步骤(3)包括：(1)所述焊线位于焊针中，移动所述焊针以将所述焊线的端点与所述引脚进行接合；(2)移动所述焊针至跃过所述塑性材料，使所述焊线经过所述塑性材料的正上方；(3)移动所述焊针以引导所述焊线埋入所述塑性材料中；(4)移动所述焊针以引导所述焊线与所述打线焊垫接合。更进一步的，在移动所述焊针以引导所述焊线埋入所述塑性材料中前，所述焊线不接触所述塑性材料。将所述焊线的端点与所述引脚进行接合后，升起所述焊针至高于所述塑性材料。
基于上述，本发明所提出的打线方法，可在打线过程中使焊线立即被塑性材料所包埋及固定，因此可避免在打线过程中因振动造成的焊线互碰短路，解决先前技术中塑性材料内包覆气泡和不易控制塑性材料形状的缺陷。是以，本发明可提高制作工艺良率，更适用于小尺寸和小间距的打线焊垫，以及高密度化的组件打线制作工艺。
附图说明
图1为公知技术的塑性材料包埋焊线示意图。
图2-4为本发明一实施例的打线方法的立体示意图。
图5-8为图4的打线方法的剖面示意图。
其中，附图标记说明如下：
10、30焊线20塑性材料
32球形接合点40焊针
100芯片110打线焊垫
200承载件220引脚
具体实施方式
为使本发明的目的、特征更明显易懂，下面结合附图对本发明的具体实施方式做进一步的说明。
请参考图2-4，为本发明一实施例的打线方法的立体示意图。如图2所示，将芯片100置于承载件200上。芯片100上具有打线焊垫110，而承载件200上具有引脚220。如图3所示，将塑性材料20点胶(并附着)于芯片100上，且位于打线焊垫110以及引脚220间。塑性材料20为一高分子材料，且优选为具有高黏滞性及高触变性的高分子材料。接着，如图4所示，将焊线30打线于打线焊垫110与引脚220上，使焊线30连接于打线焊垫110与引脚220间，并且埋入塑性材料20中。最后，再以例如烘烤的方式硬化塑性材料20。本实施例中，先以高黏滞性及高触变性的高分子材料作为塑性材料20黏着于芯片100表面，再进行打线，以使焊线30在打线的过程中直接埋入塑性材料20中，最后烘烤硬化塑性材料20并再进行封模工艺。以本实施例所述的方法，塑性材料20使用高黏滞性及高触变性的高分子材料，可在点胶塑性材料20于芯片100表面时，因其流动快速而快速达到预设的位置及形状，而当点胶后的流动性小，促使塑性材料20维持在特定的高/宽比，而不至于坍塌、溢胶，污染打线焊垫110与引脚220等，影响后续打线。
更进一步而言，图4中将焊线30打线于打线焊垫110与引脚220上的步骤，可再详细说明如图5-8，其为图4的打线方法的剖面示意图。如图5所示，芯片100置于承载件200上。芯片100上具有打线焊垫110，而承载件200上具有引脚220。塑性材料20则点胶于芯片100上，且位于打线焊垫110以及引脚220间。移动焊针40，将位于焊针40中的焊线30的端点与引脚220接合，形成一球形接合点32。后，可升起焊针40至高于塑性材料20的位置。如图6所示，移动焊针40至跃过塑性材料20，如此则可引导焊线30跨越过塑性材料20的正上方。在此步骤中需注意不可使焊针40或焊线30碰触到塑性材料20。焊针40碰触到塑性材料20会破坏塑性材料20原有的形状或使塑性材料20污染焊针40或其它位置的组件。焊线30如在此时即沾黏到塑性材料20，可能导致焊线30在拖曳中断裂、损坏或定位在非预期的位置。如图7所示，移动焊针40以引导焊线30埋入塑性材料20中。在本实施例中，焊针40为向下移动，以带动焊线30埋入塑性材料20中，但又不会拉扯到焊线30，或使各焊线30间互相碰触而造成短路。如图8所示，移动焊针40，以引导焊线30，并将焊线30压焊至与打线焊垫110接合。另外，接合的过程中也可将引脚220与打线焊垫110互换。也就是说，先将焊线30与打线焊垫110接合，再连接至引脚220。
综上所述，本发明所提出的打线方法，可在打线过程中使焊线立即被塑性材料所包埋及固定，因此可避免在打线过程中因振动造成的焊线互碰短路。是以，本发明可提高制作工艺良率。再者，由于本发明采先点胶塑性材料再包埋打线的方法，因此本发明可解决现有技术中塑性材料内包覆气泡和不易控制塑性材料形状的缺陷。因而，本发明更适用于小尺寸和小间距的打线焊垫，以及高密度化的组件打线制作工艺。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (6)

1.一种打线方法,其特征在于,包括:
(1)将芯片置于承载件上；
(2)将塑性材料点于所述芯片上,其中所述塑性材料位于所述芯片的打线焊垫与所述承载件的引脚间并且不与所述打线焊垫与所述承载件的引脚直接接触；及
(3)打线于所述打线焊垫与所述引脚上,使焊线连接于所述打线焊垫与所述引脚间,并且使所述焊线介于所述打线焊垫与所述承载件的引脚间的中间部分埋入所述塑性材料中。
2.如权利要求1所述的打线方法,其特征在于,打线于所述打线焊垫与所述引脚上的步骤,包括:
(1)所述焊线位于焊针中,移动所述焊针以将所述焊线的端点与所述引脚进行接合；
(2)移动所述焊针至跃过所述塑性材料,使所述焊线经过所述塑性材料的正上方；
(3)移动所述焊针以引导所述焊线埋入所述塑性材料中；及
(4)移动所述焊针以引导所述焊线与所述打线焊垫接合。
3.如权利要求1所述的打线方法,其特征在于,所述塑性材料为高分子塑性材料。
4.如权利要求1所述的打线方法,其特征在于,在打线于所述打线焊垫与所述引脚上后,更包含:
硬化所述塑性材料。
5.如权利要求2所述的打线方法,其特征在于,在移动所述焊针以引导所述焊线埋入所述塑性材料中前,所述焊线不接触所述塑性材料。
6.如权利要求2所述的打线方法,其特征在于,将所述焊线的端点与所述引脚进行接合后,更包含:
升起所述焊针至高于所述塑性材料。
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CN101552214A (zh) * 2008-04-02 2009-10-07 力成科技股份有限公司 打线工序减半的多芯片堆叠方法与构造
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