CN101894820A - 晶片封装结构及其制作方法 - Google Patents

晶片封装结构及其制作方法 Download PDF

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CN101894820A
CN101894820A CN2009101430218A CN200910143021A CN101894820A CN 101894820 A CN101894820 A CN 101894820A CN 2009101430218 A CN2009101430218 A CN 2009101430218A CN 200910143021 A CN200910143021 A CN 200910143021A CN 101894820 A CN101894820 A CN 101894820A
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bonding wire
base plate
layer
wafer
chip package
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吴重盘
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Xinxing Electronics Co Ltd
Unimicron Technology Corp
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Xinxing Electronics Co Ltd
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Abstract

本发明是有关于一种晶片封装结构及其制作方法。晶片封装结构，包括一线路基板、一晶片、至少一焊线以及一粘着层。线路基板具有一接合面与配置于接合面上的至少一焊垫。晶片配置于线路基板的接合面上，且具有远离线路基板的一主动面与配置于主动面的至少一接垫。焊线连接于接垫与焊垫之间，使晶片藉由焊线与线路基板电性连接。焊线包括一铜层、一镍层以及一金层，其中镍层包覆铜层，金层包覆镍层。粘着层配置于焊垫与焊线之间以及接垫与焊线之间，且分别包覆焊线的两端。藉由本发明，可有效降低制造成本且具有较高的生产良率与可靠度。

Description

晶片封装结构及其制作方法
技术领域
本发明涉及一种半导体结构及其制造方法，特别是涉及一种晶片封装结构及其制造方法。
背景技术
打线技术(wire bonding technology)是一种常见的晶片封装技术，用以将晶片电性连接至承载器(carrier)，其中承载器例如是一线路基板。一般而言，打线技术是利用打线机(stud bump machine)形成一焊线凸块于承载器的焊垫上，并将打线向上延伸一段距离，然后再转向下拉线到晶片接垫后扯线(stitch)抽离。藉由打线技术，晶片与承载器得以藉由焊线彼此电性连接，而讯号才能藉由焊线在晶片与承载器之间传递。
目前常见的焊线的材质包括铝、铜或金，其中以铝作为焊线的技术已经发展的相当成熟了，但由于铝的电阻甚高且有电子迁移(migration)等问题，因此利用铜具有电子迁移阻抗值为铝的30至100倍的特性来取代铝做为焊线的材质。更进一步而言，铜的热传导系数(thermal conductivity)约为394W/m°K，金的热传导系数约为293W/m°K，而铝的热传导系数约为247W/m°K，由上述金属的热传导系数可得知，铜的热传导率相对于铝、金的热传导率较佳，但铜为易氧化的金属，因此若采用铜作为焊线的材质，易产生氧化的现象而造成焊线的可靠度与强度降低等问题。若采用次于铜的热传导率的金作为焊线的材质时，虽然可以克服焊线氧化的问题，但由于金的成本相对于铜、铝高，因此会增加焊线的制造成本。换言之，如何在能降低焊线的制造成本下，仍然能维持焊线的强度与可靠度，实为一亟待解决的课题。
由此可见，上述现有的晶片封装结构及其制作方法在产品结构、制造方法与使用上，显然仍存在有不便与缺陷，而亟待加以进一步改进。为了解决上述存在的问题，相关厂商莫不费尽心思来谋求解决之道，但长久以来一直未见适用的设计被发展完成，而一般产品及方法又没有适切的结构及方法能够解决上述问题，此显然是相关业者急欲解决的问题。因此如何能创设一种新的晶片封装结构及其制作方法，实属当前重要研发课题之一，亦成为当前业界极需改进的目标。
发明内容
本发明的目的在于，克服现有的晶片封装结构及其制作方法存在的缺陷，而提供一种新的晶片封装结构及其制作方法，所要解决的技术问题是使其可有效降低制造成本且具有较高的生产良率与可靠度，非常适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的本发明提出一种晶片封装结构，其包括一线路基板、一晶片、至少一焊线以及一粘着层。线路基板具有一接合面与配置于接合面上的至少一焊垫。晶片配置于线路基板的接合面上，且具有远离线路基板的一主动面与配置于主动面的至少一接垫。焊线连接于接垫与焊垫之间，使晶片藉由焊线与线路基板电性连接。焊线包括一铜层、一镍层以及一金层，其中镍层包覆铜层，金层包覆镍层。粘着层配置于焊垫与焊线之间以及接垫与焊线之间，且分别包覆焊线的两端。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
在本发明的一实施例中，上述的焊线更包括一钯层，配置于镍层与金层之间。
在本发明的一实施例中，上述的粘着层的材质包括一金属或一金属树脂。
在本发明的一实施例中，上述的焊线的铜层的厚度大于焊线的镍层的厚度，焊线的镍层的厚度大于焊线的金层的厚度。
在本发明的一实施例中，上述的晶片封装结构更包括一封装胶体。封装胶体配置于线路基板的接合面上，且包覆部分线路基板、晶片、焊线与粘着层。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的本发明提出一种晶片封装结构的制造方法。首先，提供一线路基板。线路基板具有一接合面与配置于接合面上的至少一焊垫。接着，配置一晶片于线路基板的接合面上。晶片具有远离线路基板的一主动面以及配置于主动面的至少一接垫。之后，形成一粘着层于焊垫与接垫上。最后，形成至少一焊线以连接接垫与焊垫，使晶片藉由焊线与线路基板电性连接。焊线包括一铜层、一镍层以及一金层，其中镍层包覆铜层，金层包覆镍层，粘着层包覆焊线的两端而使焊线两端能与焊垫与接垫结合。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
在本发明的一实施例中，上述的粘着层是藉由点胶的方式所形成。
在本发明的一实施例中，上述的粘着层的材质包括一金属或一金属树脂。
在本发明的一实施例中，上述的焊线更包括一钯层，配置于镍层与金层之间。
在本发明的一实施例中，上述的焊线连接焊垫和接垫且粘着层包覆焊线的两端的方法包括进行一超音波接合制造工艺。
在本发明的一实施例中，上述的形成焊线之后，更包括形成一封装胶体，以包覆部分线路基板、晶片、焊线与粘着层。
借由上述技术方案，本发明晶片封装结构及其制作方法至少具有下列优点及有益效果：
基于上述，由于本发明的晶片封装结构所采用的焊线是由一铜层、一镍层以及一金层所组成，且在焊线与线路基板的焊垫以及晶片的接垫之间具有一粘着层，并利用超音波接合的方式来增加焊线、焊垫、接垫以及粘着层之间的接合力，因此相较于现有习知技术所采用的焊线而言，本发明的焊线除了可有效降低晶片封装结构的制造成本外，亦可有效提高晶片封装结构的强度、可靠度以及生产良率。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
附图说明
图1A为本发明一实施例的一种晶片封装结构的示意图。
图1B为图1A的焊线的俯视示意图。
图1C为本发明另一实施例的一焊线的俯视示意图。
图2A至图2E是本发明一实施例的一种晶片封装结构的制造方法的示意图。
100：晶片封装结构    110：线路基板
112：接合面          114：焊垫
120：晶片            122：主动面
124：接垫            130、130a：焊线
132：铜层            134：镍层
136：金层            138：钯层
140：粘着层          150：封装胶体
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明提出的晶片封装结构及其制作方法的具体实施方式、结构、方法、步骤、特征及其功效，详细说明如后。
图1A为本发明一实施例的一种晶片封装结构的示意图，图1B为图1A的焊线的俯视示意图。请同时参考图1A与图1B所示，在本实施例中，晶片封装结构100包括一线路基板110、一晶片120、至少一焊线130(图1A中仅示意地绘示一条)以及一粘着层140。
详细而言，线路基板110具有一接合面112与至少一焊垫114(图1A中仅示意地绘示一个)，其中焊垫114配置于接合面112上。在本实施例中，线路基板110例如是一印刷电路板(Printed Circuit Board，PCB)，焊垫114的材质例如是金或铜。一般而言，若焊垫114的材质为铜时，焊垫114的表面通常亦会再覆盖一镍层与一金层，以避免受到氧化及其他环境条件的影响。
晶片120配置于线路基板110的接合面112上，且晶片120具有一远离线路基板110的主动面122与至少一接垫124(图1A中仅示意地绘示一个)，其中接垫124配置于主动面122且位于晶片120的外围。
焊线130连接于晶片120的接垫124与线路基板110的焊垫114之间，使晶片120藉由焊线130与线路基板110电性连接。特别是，在本实施例中，焊线130包括一铜层132、一镍层134以及一金层136，其中镍层134包覆铜层132，金层136包覆镍层134，且焊线130的铜层132的厚度大于焊线130的镍层134的厚度，焊线130的镍层134的厚度大于焊线130的金层136的厚度。在较佳实施例中，焊线130的铜层132的厚度例如是介于15微米至30微米之间，焊线130的镍层134的厚度例如是介于1微米至20微米之间，而焊线130的金层136的厚度例如是介于0.1微米至1.0微米之间。
在本实施例中，由于焊线130是由镍层134包覆铜层132、金层136包覆镍层134所组成，且金层136的厚度远小于铜层132的厚度，因此除了可有效降低焊线130的制作成本外，焊线130的最外层的金层136亦具有抗氧化的效果，可有效提高焊线130的可靠度与强度。另外，焊线130中具有相对于金层136的较厚的铜层132，且由于铜的热传导系数(thermalconductivity)高达394W/m°K，因此晶片120在运作的过程中所产生的热量部分能快速且有效地藉由焊线130经由热对流(heat convection)或热辐射(heat radiation)等热传递机制排除至外界环境。此外，镍层134配置于铜层132与金层136之间，可防止铜离子与金离子因接触而产生离子置换的现象。
值得一提的是，本发明并不限焊线130的形态，虽然此处所提及的焊线130具体化是由铜层132、镍层134以及金层136的搭配所组成，但已知的其他能达到同等降低成本及抗氧化效果的结构设计，例如请参考图1C所示，焊线130a更包括一钯层138，配置于镍层134与金层136之间，意即焊线130a是由铜层132、镍层134、金层136以及钯层138的搭配所组成，较佳地，钯层138的厚度例如是介于1纳米至10纳米之间，仍属于本发明可采用的技术方案，不脱离本发明所欲保护的范围。
粘着层140配置于线路基板110的焊垫114与晶片120的接垫124上，且粘着层140分别包覆焊线130的两端。由于线路基板110的焊垫114与焊线130之间以及晶片120的接垫124与焊线130之间配置有粘着层140，因此可在打线接合制造工艺(即制程，以下均称为制造工艺)中有效提高焊线130的接合力。在本实施例中，粘着层140的材质包括一金属或一金属树脂，其中金属包括金或锡，而金属树脂包括金膏或锡膏。在较佳实施例中，粘着层140的材质例如是金膏或锡膏。
此外，本实施例的晶片封装结构100更包括一封装胶体150，其中封装胶体150配置于线路基板110的接合面112上，且包覆部分线路基板110、晶片120、焊线130、焊垫114与粘着层140，以防止晶片120与焊线130受到外界的温度、湿气的影响以及杂尘污染。
简言之，由于本实施例的晶片封装结构100所采用的焊线130是由铜层132、镍层134以及金层136所组成，且于焊线130与线路基板110的焊垫114之间以及焊线130与晶片120的接垫124之间有粘着层140，因此相较于现有习知技术所采用的焊线而言，本实施例的焊线130除了可有效降低晶片封装结构100的制造成本外，亦可有效提高晶片封装结构100的强度、可靠度以及生产良率。
以上仅介绍本发明的晶片封装结构100，并未介绍本发明的晶片封装结构的制作方法。对此，以下将以一实施例来说明晶片封装结构的制作方法，且是以晶片封装结构100为例，并配合图2A至图2E所示，对晶片封装结构的制作方法进行详细的说明。
图2A至图2E是本发明一实施例的一种晶片封装结构的制造方法的示意图。请先参考图2A所示，依照本实施例的晶片封装结构的制作方法，首先，提供一线路基板110，其中线路基板110具有一接合面112与配置于接合面112上的至少一焊垫114(图2A中仅示意地绘示一个)。在本实施例中，线路基板110例如是一印刷电路板，焊垫114的材质例如是金或铜。一般而言，若焊垫114的材质为铜时，焊垫114的表面通常亦会再覆盖一镍层与一金层，以避免受到氧化及其他环境条件的影响。
接着，请参考图2B所示，配置一晶片120于线路基板110的接合面112上，其中晶片120具有远离线路基板110的一主动面122以及配置于主动面122的至少一接垫124(图2B中仅示意地绘示一个)，其中接垫124配置于主动面122且位于晶片120的外围。
接着，请参考图2C所示，形成一粘着层140于线路基板110的焊垫114与晶片120的接垫124上，其中粘着层140是藉由点胶的方式所形成，且粘着层140的材质包括一金属或一金属树脂，而金属包括金属锡，金属树脂包括金膏或锡膏。在较佳实施例中，粘着层140的材质例如金膏或锡膏。在此必须说明的是，粘着层140可与焊垫114及后续制造工艺所形成的焊线130形成共晶接合(eutectic bonding)。
之后，请同时参考图1B与图2D所示，形成至少一焊线130(图2D中仅示意地绘示一条)以连接晶片120的接垫124与线路基板110的焊垫114，使晶片120藉由焊线130与线路基板110电性连接。特别是，在本实施例中，焊线130包括一铜层132、一镍层134以及一金层136，其中镍层134包覆铜层132，金层136包覆镍层134，粘着层140包覆部分焊线130的两端，且焊线130的铜层132的厚度大于焊线130的镍层134的厚度，焊线130的镍层134的厚度大于焊线130的金层136的厚度。
在较佳实施例中，焊线130的铜层132的厚度例如是介于15微米至30微米之间，最佳为20微米至25微米之间，焊线130的镍层134的厚度例如是介于1微米至20微米之间，而焊线130的金层136的厚度例如是介于0.1微米至1.0微米之间。在其他实施例中，请参考图1C所示，焊线130亦可更包括一钯层138，配置于镍层134与金层136之间，意即焊线130a是由铜层132、镍层134、金层136以及钯层138的搭配所组成，较佳地，钯层138的厚度例如是介于1纳米至10纳米之间，仍属于本发明可采用的技术方案，不脱离本发明所欲保护的范围。
更进一步而言，在本实施例中，焊线130连接线路基板110的焊垫114与晶片120的接垫124且粘着层140包覆部分焊线130的方法是采用进行一超音波接合制造工艺，其中进行超音波接合制造工艺的能量介于90mw至110mw之间，压力介于85g/cm2至95g/cm2之间，温度介于215℃至225℃之间(较佳地，温度介于219℃至221℃)，且压合时间介于10毫秒至15毫秒之间。由于焊线130、焊垫114、接垫124与粘着层140是采用超音波接合的方式，所以当焊垫114的材质为金(或金膏)，且粘着层140的材质亦为金时，焊线130、焊垫114、接垫124与粘着层140之间会因金-金共晶接合而彼此电性连接。当焊垫114和接垫124的材质为金，而粘着层140的材质亦为锡(或锡膏)时，焊线130、焊垫114与粘着层140之间会因锡粘着而彼此电性连接。换言之，本实施例可在焊线130、焊垫114与粘着层140的接触面上达到共晶接合的效果，可更进一步提升接合强度。
最后，请参考图2E所示，形成一封装胶体150，以包覆部分线路基板110、晶片120、焊线130、焊垫114与粘着层140，可防止晶片120与焊线130受到外界的温度、湿气的影响以及杂尘污染。至此，已完成晶片封装结构100的制作。
简言之，本实施例的晶片封装结构的制作方法是在形成焊线130电性连接之前，先在线路基板110的焊垫114和晶片120的接垫124上形成粘着层140，之后再利用超音波接合的方式来使焊线130、焊垫114、接垫124与粘着层140的接触面上达到共晶接合的效果，除了可有效提升焊线130与焊垫114以及焊线130与接垫124之间的接合强度外，亦可有效提高制造工艺的良率，并可使晶片封装结构100具有较高的生产良率与可靠度。
综上所述，由于本发明的晶片封装结构所采用的焊线是由铜层、镍层以及金层或铜层、镍层、金层以及钯层所组成，且铜层的厚度远大于金层的厚度，金层位于焊线的最外层，因此相较于现有习知技术所采用的焊线而言，本发明除了可有效降低晶片封装结构的制造成本外，焊线亦具有抗氧化的效果，可有效提高可靠度与强度。此外，由于本发明的晶片封装结构的制作方法采用的超音波接合的方式，来增加焊线、焊垫与粘着层之间的接合力，因此本发明可有效提高制造工艺良率，并使晶片封装结构具有较高的生产良率与可靠度。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (11)

1.一种晶片封装结构，其特征在于其包括：
一线路基板，具有一接合面与配置于该接合面上的至少一焊垫；
一晶片，配置于该线路基板的该接合面上，且具有远离该线路基板的一主动面与配置于该主动面的至少一接垫；
至少一焊线，连接于该接垫与该焊垫之间，使该晶片藉由该焊线与该线路基板电性连接，该焊线包括一铜层、一镍层以及一金层，其中该镍层包覆该铜层，该金层包覆该镍层；以及
一粘着层，置于该焊垫与该焊线以及该接垫与该焊线之间，且包覆该焊线的两端。
2.根据权利要求1所述的晶片封装结构，其特征在于其中所述的焊线更包括一钯层，配置于该镍层与该金层之间。
3.根据权利要求1所述的晶片封装结构，其特征在于其中所述的粘着层的材质包括一金属或一金属树脂。
4.根据权利要求1所述的晶片封装结构，其特征在于其中所述的焊线的该铜层的厚度大于该焊线的该镍层的厚度，该焊线的该镍层的厚度大于该焊线的该金层的厚度。
5.根据权利要求1所述的晶片封装结构，其特征在于其更包括一封装胶体，配置于该线路基板的该接合面上，且包覆部分该线路基板、该晶片、该焊线与该粘着层。
6.一种晶片封装结构的制造方法，其特征在于其包括以下步骤：
提供一线路基板，该线路基板具有一接合面与配置于该接合面上的至少一焊垫；
配置一晶片于该线路基板的该接合面上，该晶片具有远离该线路基板的一主动面以及配置于该主动面的至少一接垫；
形成一粘着层于该焊垫与该接垫上；以及
形成至少一焊线，以连接该接垫与该焊垫，使该晶片藉由该焊线与该线路基板电性连接，该焊线包括一铜层、一镍层以及一金层，其中该镍层包覆该铜层，该金层包覆该镍层，该粘着层包覆该焊线的两端。
7.根据权利要求6所述的晶片封装结构的制造方法，其特征在于其中所述的粘着层是藉由点胶的方式所形成。
8.根据权利要求6所述的晶片封装结构的制造方法，其特征在于其中所述的粘着层的材质包括一金属或一金属树脂。
9.根据权利要求6所述的晶片封装结构的制造方法，其特征在于其中所述的焊线更包括一钯层，配置于该镍层与该金层之间。
10.根据权利要求6所述的晶片封装结构的制造方法，其特征在于其中所述的焊线连接该焊垫和该接垫且该粘着层包覆该焊线的两端的方法，包括进行一超音波接合制造工艺。
11.根据权利要求6所述的晶片封装结构的制造方法，其特征在于其中所述的形成该焊线之后，更包括形成一封装胶体，以包覆部分该线路基板、该晶片、该焊线与该粘着层。
CN2009101430218A 2009-05-22 2009-05-22 晶片封装结构及其制作方法 Pending CN101894820A (zh)

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Cited By (2)

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CN103367179A (zh) * 2012-03-29 2013-10-23 南亚科技股份有限公司 打线方法
CN110729207A (zh) * 2019-10-12 2020-01-24 闳康技术检测(上海)有限公司 一种封装打线的键合方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367179A (zh) * 2012-03-29 2013-10-23 南亚科技股份有限公司 打线方法
CN103367179B (zh) * 2012-03-29 2016-06-15 南亚科技股份有限公司 打线方法
CN110729207A (zh) * 2019-10-12 2020-01-24 闳康技术检测(上海)有限公司 一种封装打线的键合方法
CN110729207B (zh) * 2019-10-12 2021-07-13 闳康技术检测(上海)有限公司 一种封装打线的键合方法

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