CN103339730B - 具有降低的接通电阻的半导体装置 - Google Patents
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Abstract
本发明涉及一种半导体装置，其具有位于第一导电类型的高度掺杂的衬底上的第一导电类型的外延层、施加到所述外延层中的第二导电类型的层和设置在第二导电类型的层的表面上的高度掺杂的第二导电类型的层。在第二导电类型的层和第一导电类型的高度掺杂的衬底之间设置有外延层区域中的多个彼此平行地设置的肖特基接触部，其在浮动状态中。
Description
技术领域
本发明涉及一种具有降低的接通电阻的半导体装置。
背景技术
功率MOS场效应晶体管长时间以来用作用于功率电子装置中的应用的快速开关。除平面双扩散结构(DMOS)以外，越来越多地使用具有沟道结构的功率MOSFET(TrenchMOS：沟槽MOS)。
图1示出沟槽MOS的布置的简化横截面。n掺杂的硅层2(外延层)位于高度n+掺杂的硅衬底1上，在所述n掺杂的硅层中施加多个沟道(沟槽)3，其中在图1中示例性地示出仅仅一个沟槽。在沟道的侧壁处和底部处分别存在一个薄的、大多由二氧化硅构成的介电层4。沟道的内部以导电材料5——例如以掺杂的多晶硅填充。p掺杂的层(p阱)6位于沟道之间。在所述p掺杂的层中，在表面上施加高度n+掺杂的区域8(源极)和高度p+掺杂的区域7(用于p阱的连接)。整个结构的表面以导电层9——例如以铝覆盖，所述导电层与p+或n+掺杂的层7和8建立欧姆接触。厚的介电层10——例如CVD氧化层使导电多晶硅层5与金属化9隔离。多晶硅层5彼此连接并且与未绘出的金属栅极接触部电(galvanisch)连接。为此，在芯片表面上的一个位置处打开介电层10和金属层9。在多晶硅层5上方在所述金属开口中施加另一未示出且与金属层9电绝缘的岛状的金属层。所述岛状的金属层接触多晶硅层5并且用作栅极连接端。
金属化层11同样位于芯片的背侧上。所述金属化层与高度n+掺杂的硅衬底1电接触。金属层9构成源极接触部S，金属层11构成漏极接触部D并且未绘出的岛状的金属层构成栅极接触部G。金属化9或者岛状的金属层可以是在硅技术方面普通的具有铜成份和/或硅成份的铝合金或可以是其他金属体系。在背侧上施加可焊接的金属体系11，其例如由层序列——钛、镍钒和银制成。
漏极接触部11通常位于正电势上，而源极连接端位于地电势上。如果在栅极连接端上相对于源极接触部施加足够高的正栅极电压VG，则在体区域6中在与栅极氧化物4的分界面上形成薄的电子反转通道。栅极电压VG在此必须比晶体管的门限电压VTH更高。反转通道在此从n+掺杂的源极区域8延伸直至n掺杂的外延区域2。因此实现了从源极接触部至漏极接触部的连续的电子路径。晶体管导通。
因为电流仅仅通过涉及电子的多数载流子实现，所以可以快速中断电流。所述构件与传统的双极构件相比非常快速地转换。
n掺杂的区域(外延层)2的掺杂浓度和厚度通过晶体管的反向电压确定。MOSFET的反向电压选择得越高，区域2必须越弱地掺杂并且必须越厚。因为在外延区域处形成欧姆电压降，所以由此整个接通电阻Rdson增大。在高反向电压的情况下，所述份额占主导。因此，MOSFET通常不适于超过200V的反向电压。
已经由US6,621,121B2已知一种垂直的MOSFET，其具有降低的接通电阻。所述已知的MOSFET包含具有多个半导体台面(Mesa)的半导体衬底，所述多个半导体台面通过多个条带形的沟道彼此分离。这些沟道彼此平行地延伸并且在第一方向上在衬底上横向延伸。此外，已知的MOSFET具有多个设置在多个条带形的沟道中的、隐藏的、隔离的源极电极。此外，已知的MOSFET包含多个隔离的栅极电极，所述多个隔离的栅极电极彼此平行地在多个半导体台面上延伸直至平的沟道中，所述平的沟道设在所提到的多个隐藏的隔离的源极电极中。此外，已知的MOSFET在所提到的半导体衬底上具有表面源极电极，其与多个隐藏的、隔离的源极电极接触并且与所述多个半导体台面中的每一个中的至少一个基区具有欧姆接触。
发明内容
根据本发明，提出了一种半导体装置，其具有位于第一导电类型的高度掺杂的衬底上的第一导电类型的外延层、施加到所述外延层中的第二导电类型的层和设置在所述第二导电类型的层的表面上的高度掺杂的第二导电类型的层，其中，在所述第二导电类型的层和所述第一导电类型的高度掺杂的衬底之间设置有多个设置在至少一个沟道中并且在朝向所述高度掺杂的衬底的方向上平行于所述高度掺杂的衬底地且彼此平行地设置的、浮动的肖特基接触部。
根据本发明，还提出了根据上述技术方案所述的半导体装置在机动车发电机的整流器中的应用。
具有在上述技术方案中说明的特征的半导体装置具有以下优点：其能够简单地实现，除接通电阻降低以外，还能够实现反向电压区域的扩展并且尤其还适合于多数载流子构件。根据本发明的半导体装置具有多个浮动(gefloatet)的肖特基接触部，其设置在半导体装置的外延区域的范围中。浮动的肖特基接触部在此理解为以下肖特基接触部：在所述肖特基接触部中肖特基金属不具有与其他接触部的电连接。
基于所述多个浮动的肖特基接触部，在外延层中分别形成周期性均匀的场分布以及几乎线性的电压分布。用于预给定的击穿电压的外延层的掺杂浓度可以选择得比在已知的MOSFET中更高。接通电阻降低。
附图说明
以下根据图2-8详细解释根据本发明的半导体装置的实施例。
图2示出根据本发明的第一实施例的MOSFET的一个单元的截面视图，
图3示出根据第一实施例的MOSFET的截面视图，其中示出MOSFET的三个单元；
图4示出用于说明在根据第一实施例的MOSFET的击穿中电场在台面条带区域中的分布的图，
图5示出用于说明在根据第一实施例的MOSFET的击穿中在台面条带区域中的电压分布的图，
图6示出根据本发明的第二实施例的MOSFET的截面视图，
图7作为本发明的第三实施例示出pn二极管的一个单元的截面视图，
图8作为本发明的第四实施例示出pn二极管的一个单元的截面视图。
具体实施方式
图2示出根据本发明的第一实施例的MOSFET的一个单元的截面视图。MOSFET具有多个这类单元，它们彼此平行地设置，其中这些单元中的每一个在与在绘图平面垂直的方向上延伸。
所示MOSFET包含一个高度n+掺杂的硅衬底1、一个位于其上的n掺杂的硅衬底2(外延层)，在所述n掺杂的硅衬底中施加有多个沟道(沟槽)3。沟道3优选具有矩形形状或U形形状或与其类似的形状。沟道3可以以条带布置或以岛的形式设置，其中岛例如设计成圆形或六角形。优选通过在外延层2中蚀刻来制造沟道3。在上部中，薄的、大多由二氧化硅组成的介电层4位于沟道的侧壁处。在沟道内，由导电材料5——例如掺杂的多晶硅制成的区域连接到侧壁上。氧化层4伸展直至区域5下面，但在那里稍微更厚地实施(区域4a)。p掺杂的层(p阱)6位于沟道之间。在所述p掺杂的层中，在表面上施加高度n+掺杂的区域8(源极)和高度p+掺杂的区域7(用于p阱的电连接)。整个结构的表面以导电层9——例如以铝覆盖，所述导电层与p+或n+掺杂的层7和8建立欧姆接触。厚的介电层10——例如CVD氧化层使导电的多晶硅层5与金属化9隔离。多晶硅层5彼此连接并且与未绘出的金属栅极接触部电连接。金属化层11同样位于芯片的背侧上，所述金属化层与高度n+掺杂的硅衬底1电接触。金属层9构成源极接触部S，金属层11构成漏极接触部D并且未绘出的岛状金属层构成MOSFET的栅极接触部G。
不同于根据图1的布置，沟槽区域3不以氧化层4或者4a结束，而是在4a下面还设置有其他交替的层，其中肖特基金属12和其他氧化层14交替。在此，与在两侧上连接的n掺杂的区域2构成(非欧姆的)肖特基接触部70的所有金属和所有硅化物理解为肖特基金属。例如，材料12可以是镍或镍硅。在所示示例中，5个浮动(floatend)的肖特基层12位于氧化区域4a下面，所述5个浮动的肖特基层分别又通过介电层14彼此绝缘。最后一个浮动的肖特基接触部覆盖沟槽底部。当然还可以设有更多或更少的浮动的肖特基层12。
图3示出根据第一实施例的MOSFET的截面视图，其中示出MOSFET的三个相邻的单元。由图3可以看出，在n外延层2中蚀刻的沟道(沟槽)3具有宽度Wt和至n+衬底1的间距D_epi。相邻的沟道3之间的台面区域的间距是Wm。肖特基接触部12分别具有厚度D_sk并且以彼此的间距D_gap放置。D_gap相应于氧化层14的厚度(见图2)。栅极氧化物4的厚度是t_ox并且下面的更厚的氧化物的厚度是t_oxa。浮动的肖特基区域12的数量是Z。在所示示例中，选择Z＝5。
在足够高的正栅极电压VG(大于阈电压VTH)的情况下接通MOSFET。电子流从源极区域8通过p区域6中的反转通道流到外延区域或者衬底区域2或1中。
在反向方向上，在位于体区域6下面的n外延层2中形成空间电荷区。空间电荷区随着上升的电压在至衬底1的方向上伸展。如果空间电荷区在电压V1时达到浮动的第一肖特基接触部，则由浮动的第一肖特基接触部承担所述电压V1。空间电荷区随着进一步上升的电压在沟槽底部或者衬底的方向上继续伸展。第一浮动的肖特基接触部上的电压保持不变。
类似地，空间电荷区在更高的电压Vn时达到第n个浮动的肖特基接触部。在此，第n个浮动的肖特基接触部承担电压Vn。在继续上升的电压的情况下，在第n个浮动的肖特基接触部上的电压又保持不变。
如果MOSFET结构中的宽度D_sk和间距D_gap对于所有肖特基接触部12选择得相同，则在区域2的台面区域(间距Wm)中出现周期性均匀的场分布。在图4中说明所述场分布，其中沿着横坐标绘出台面区域中沿着沟槽在至衬底1的方向上的路径并且沿着纵坐标绘出电场强度E。横坐标X下方的矩形在此象征性表示浮动的肖特基接触部的位置。可以看出，台面区域中的场分布根据间距(D_sk+D_gap)一直重复，直至达到沟槽底部。
图5示出台面区域中的所属电压分布的图，其中在图5中横坐标X下方的矩形也象征性表示浮动的肖特基接触部的位置。可以看出，台面区域中的电压分布分别是线性的。恒定电压的短区域仅仅位于肖特基接触部的区域中。
与传统的布置不同，反向电压随着浮动的肖特基接触部12的增大的数量Z而增大。由此实现更高的反向电压或者可以在相当的反向电压的情况下选择外延区域2的更高掺杂。因此，欧姆电压降在半导体装置的接通状态中降低。接通电阻Rdson变得更小。因此可能的是，在低的接通电阻的情况下设计用于更高的反向电阻的沟槽MOSFET。
图6示出根据本发明的第二实施例的MOSFET的一个单元的截面视图。所述MOSFET的结构与根据附图2解释的MOSFET的结构一致。在图6中说明的MOSFET与在图2中示出的MOSFET仅仅通过以下方式不同：在MOSFET中根据图2设置的氧化层14通过n掺杂的多晶硅层或通过硅层13取代。层13的掺杂优选相应于n外延层2的掺杂。替代氧化层14，例如还可以使用其他介电材料，如Si3N4，SON或HfO2。
替代先前描述的分别涉及设有沟道的MOSFET的实施例，堆叠的、浮动的肖特基接触部的使用的根据本发明的原理还可以用在其他半导体装置中，例如DMOS晶体管中或IGBT中。随后，以高截止pn二极管为例示出根据本发明的原理。
图7作为本发明的第三实施例示出pn二极管的一个单元的截面视图。所述pn二极管包含高度n+掺杂的硅衬底1和位于其上的n掺杂的硅衬底2(外延层)，在所述n掺杂的硅衬底中施加多个沟道或者沟槽3。p掺杂的层(p阱)6位于沟道之间。在所述p掺杂的层6中，在其表面上施加高度p+掺杂的区域7，其用于p掺杂的层6的电连接。整个结构的表面以导电层9——例如以铝覆盖。所述导电层9与高度p+掺杂的层7形成欧姆接触。同样，与高度n+掺杂的硅衬底1电接触的金属化层11位于芯片的背侧上。
同样在所述实施例中，沟道3以介电层14a或者14和浮动的肖特基接触部12或者70的序列填充。p掺杂的层6和弱n-掺杂的区域2形成二极管的pn结。p掺杂的区域6在其表面上设有高度p+掺杂的层7。与上面描述的工作原理类似，借助这类结构，反向电压可以选择得比在不具有所述结构的普通pn二极管的情况下更高。替代地，可以提高n-掺杂的区域2的掺杂并且因此降低体电阻。
与根据图6的实施例类似地，介电层14可以通过合适的n掺杂的多晶硅层或硅层13取代。
图8作为本发明的第四实施例示出pn二极管的一个单元的截面视图。
所述pn二极管也包含高度n+掺杂的硅衬底1和位于其上的n掺杂的硅衬底2(外延层)。p掺杂的层6位于n掺杂的硅层2上。在所述p掺杂的层6中，在其表面上施加高度p+掺杂的层7，其用于p掺杂的层的电连接。整个结构的表面以导电层9——例如以铝覆盖。所述导电层9与高度p+掺杂的层7形成欧姆接触。同样，与高度n+掺杂的硅衬底电接触的金属化层11又位于芯片的背侧上。
与根据图7的布置不同，在图8中示出的装置不具有沟道。浮动的肖特基接触部70、12位于n掺杂的区域2内，从而在两个相邻的肖特基接触部之间分别存在一个n掺杂的区域2。平面构造的、p掺杂的层6和弱n-掺杂的区域2形成二极管的pn结。平面构造的、p掺杂的层6在其表面上设有同样平面构造的、高度p+掺杂的层7。与上面描述的工作原理类似地，借助这类结构，反向电压可以选择得比在不具有所述结构的普通pn二极管的情况下更高。替代地，可以提高n-掺杂的区域2的掺杂并且因此降低体电阻。
在所有上面描述的实施例中，半导体装置具有可焊接的前侧金属化和背侧金属化，从而所述半导体装置可以以简单的方式焊接在合适的电路环境中或被接通。然后，所述根据图7和8的半导体装置(二极管)分别装配在压入式二极管壳体中。根据本发明的半导体装置的优选应用是机动车发电机的整流器中的应用。
替代上面描述的实施例，所有半导体层可以分别通过相反的导电类型的半导体层取代并且源极连接端和漏极连接端或者阳极连接端和阴极连接端的标记可以交换。
Claims (12)
1.一种半导体装置，其具有位于第一导电类型的高度掺杂的衬底(1)上的第一导电类型的外延层(2)、施加到所述外延层(2)中的第二导电类型的层(6)和设置在所述第二导电类型的层(6)的表面上的高度掺杂的第二导电类型的层(7)，其特征在于，在所述第二导电类型的层(6)和所述第一导电类型的高度掺杂的衬底(1)之间设置有多个设置在至少一个沟道(3)中并且在朝向所述高度掺杂的衬底的方向上平行于所述高度掺杂的衬底地且彼此平行地设置的、浮动的肖特基接触部(70，12)。
2.根据权利要求1所述的半导体装置，其特征在于，在所述第二导电类型的层(6)的表面上还设有第一导电类型的高度掺杂的层(8)和第二导电类型的高度掺杂的层(7)，在所述外延层(2)中施加至少两个以掺杂的多晶硅(5)填充的且以介电层(4，4a)覆盖的沟道(3)，所述介电层(4a)在沟道底部处比所述介电层(4)在所述沟道(3)的侧壁处实施得更厚，并且金属层或者硅层与另外的介电层(14)的交替序列分别位于所述第二导电类型的层(6)和所述第一导电类型的高度掺杂的衬底(1)之间，其中，所述金属层或者硅层与所述外延层(2)分别形成非欧姆的肖特基接触部。
3.根据权利要求2所述的半导体装置，其特征在于，更厚的介电层(4a)位于所述第二导电类型的层(6)下面。
4.根据权利要求2或3所述的半导体装置，其特征在于，所述肖特基接触部(70，12)分别在沟道壁上浮动。
5.根据权利要求2或3所述的半导体装置，其特征在于，最邻近所述第一导电类型的高度掺杂的衬底(1)的肖特基接触部分别覆盖所述沟道底部并且具有至所述第一导电类型的高度掺杂的衬底(1)的间距D_epi。
6.根据权利要求2或3所述的半导体装置，其特征在于，所述浮动的肖特基接触部(70，12)分别具有一个宽度D_sk，并且设置在所述肖特基接触部之间的介电层(14)分别具有一个宽度D-gap。
7.根据权利要求6所述的半导体装置，其特征在于，在所述半导体装置的相邻的沟道(3)之间分别存在一个台面区域，在所述台面区域中场分布以间距D周期性重复，对于所述间距有：
D＝D_sk+D_gap，
其中，D_sk是所述浮动的肖特基接触部(70，12)的宽度，D_gap是所述另外的介电层(14)的宽度。
8.根据权利要求7所述的半导体装置，其特征在于，所述台面区域中的电压分布分别是线性的。
9.根据权利要求1所述的半导体装置，其特征在于，在所述外延层(2)中施加至少两个以介电层(14a)填充的沟道(3)，所述介电层与所述第一导电类型的高度掺杂的衬底(1)的间距比所述第二导电类型的层(6)与所述第一导电类型的高度掺杂的衬底(1)的间距更小，金属层或者硅层与另外的介电层(14)的交替序列分别位于所述介电层(14a)的面向所述第一导电类型的高度掺杂的衬底(1)的端部和所述第一导电类型的高度掺杂的衬底(1)之间，其中，所述金属层或者硅层与所述外延层(2)分别形成非欧姆的肖特基接触部。
10.根据权利要求1至3及9中任一项所述的半导体装置，其特征在于，所述彼此平行地设置的肖特基接触部(70，12)位于DMOS晶体管的体二极管下面或IGBT的体二极管下面。
11.根据权利要求1至3及9中任一项所述的半导体装置，其特征在于，所述半导体装置具有可焊接的前侧金属化(9)和可焊接的背侧金属化(11)。
12.根据权利要求1至11中任一项所述的半导体装置在机动车发电机的整流器中的应用。
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| US6621121B2 (en) | 1998-10-26 | 2003-09-16 | Silicon Semiconductor Corporation | Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes |
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