CN103325670B - 金属栅极半导体器件 - Google Patents
金属栅极半导体器件 Download PDFInfo
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- CN103325670B CN103325670B CN201210418352.XA CN201210418352A CN103325670B CN 103325670 B CN103325670 B CN 103325670B CN 201210418352 A CN201210418352 A CN 201210418352A CN 103325670 B CN103325670 B CN 103325670B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 95
- 239000002184 metal Substances 0.000 title claims abstract description 95
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 91
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims description 56
- 239000000463 material Substances 0.000 claims description 24
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- 239000010410 layer Substances 0.000 description 174
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 239000003989 dielectric material Substances 0.000 description 11
- 239000000203 mixture Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 7
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- 229910021332 silicide Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000005350 fused silica glass Substances 0.000 description 5
- 239000000565 sealant Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 125000001475 halogen functional group Chemical group 0.000 description 3
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- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
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- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910004490 TaAl Inorganic materials 0.000 description 2
- -1 TaAlC Inorganic materials 0.000 description 2
- 229910004200 TaSiN Inorganic materials 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910006501 ZrSiO Inorganic materials 0.000 description 2
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
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- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910016006 MoSi Inorganic materials 0.000 description 1
- 229910005881 NiSi 2 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- 229910006249 ZrSi Inorganic materials 0.000 description 1
- HLFWJMSINGUMDQ-UHFFFAOYSA-N [Ge].[Pt].[Ni] Chemical compound [Ge].[Pt].[Ni] HLFWJMSINGUMDQ-UHFFFAOYSA-N 0.000 description 1
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- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
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- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 208000002173 dizziness Diseases 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
提供了方法和器件,包括设置在衬底上方的多个不同配置的栅极结构。例如,第一栅极结构与第一类型的晶体管相关联,并且包括第一介电层和第一金属层;第二栅极结构与第二类型的晶体管相关联,并且包括第二介电层、第二金属层、多晶硅层、第一介电层和第一金属层;以及伪栅极结构,包括第一介电层和第一金属层。本发明还提供了金属栅极半导体器件。
Description
技术领域
本发明一般地涉及半导体技术领域,更具体地来说,涉及半导体器件及其制造方法。
背景技术
半导体集成电路(IC)工艺经历了指数增长。IC材料和设计中的技术进步产生了多代IC,其中,每一代都具有比前一代更小且更复杂的电路。在IC发展过程中,功能密度(即,每单位芯片面积上的互连器件的数量)通常增加,而几何尺寸(即,使用制造工艺可以创建的最小元件(或线))减小。这种按比例缩小工艺通常通过增加生产效率和降低相关成本来提供优点。这种按比例缩小也增加了处理和制造IC的复杂性,并且对于要实现的这些进步,需要IC处理和制造的类似发展。
在一些IC设计中,作为技术节点缩小所实现的一种进步是通过金属栅电极代替典型的多晶硅栅电极,以通过减小的特征尺寸来提高器件性能。形成金属栅叠层的一种工艺被称为替换栅极或“后栅极”工艺,其中,“最后”制造最终的金属栅叠层,这能够减少在形成栅极之后必须实施的后续工艺(包括高温处理工艺)的数目。然而,在CMOS制造中实施这种部件和工艺具有困难。对于在单个衬底上具有不同类型栅极结构的器件来说这些困难增加。
因此,期望提供一种制造具有不同配置的栅极结构的半导体器件的方法来实现替换栅极方法。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种制造半导体器件的方法,包括:形成包括第一栅极介电层、第一金属层以及上覆所述第一栅极介电层和所述第一金属层的伪层的多个栅极结构;从所述多个栅极结构的第一栅极结构和第二栅极结构中去除所述伪层的至少一部分,其中,去除所述伪层在所述第一栅极结构中提供第一沟槽以及在所述第二栅极结构中提供第二沟槽,其中,所述第二沟槽的深度大于所述第一沟槽的深度;以及在所述第一沟槽和所述第二沟槽中形成第二栅极介电层和第二金属层。
在该方法中,所述第一栅极结构与N型场效应晶体管相关联。
在该方法中,所述第二栅极结构与P型场效应晶体管相关联。
该方法进一步包括:在去除所述伪层的至少一部分之前,在所述多个栅极结构的第三栅极结构上方形成硬掩模层。
该方法进一步包括:在从所述第二栅极结构中去除所述伪层的同时,从所述多个栅极结构的第三栅极结构中去除所述伪层,其中,所述第三栅极结构是非功能性栅极。
在该方法中,从所述第二栅极结构中去除所述伪层进一步包括:去除所述第二栅极结构的第一栅极介电层和第一金属层。
该方法进一步包括:在所述第二沟槽中形成第二介电层和第二金属层。
该方法进一步包括:通过在从所述第二栅极结构中去除所述伪层的同时从所述多个栅极结构的第三栅极结构中去除所述伪层来创建第三沟槽,其中,所述第三栅极结构是非功能性栅极;以及在所述第三沟槽中形成所述第二介电层和所述第二金属层。
在该方法中,所述第一金属层是n型功函材料,而所述第二金属层是p型功函材料。
根据本发明的另一方面,提供了一种半导体器件制造方法,包括:在衬底上形成第一功函金属层和上覆多晶硅层;图案化所述第一功函金属层和所述上覆多晶硅层以形成第一栅极结构、第二栅极结构和第三栅极结构;在所述第一栅极结构上形成掩模元件;实施所述多晶硅层的第一蚀刻,使得从所述第二栅极结构和所述第三栅极结构中去除所述多晶硅层的一部分,同时所述掩模元件设置在所述第一栅极结构上;在去除所述第一栅极结构上的所述掩模元件之后,实施所述多晶硅层的第二蚀刻,使得从所述第一栅极结构中去除所述多晶硅层的一部分以形成第一沟槽,并且从所述第二栅极结构和所述第三栅极结构中去除所述多晶硅层的一部分以形成第二沟槽和第三沟槽;以及在所述第一沟槽、所述第二沟槽和所述第三沟槽中形成第二功函金属层。
在该方法中,所述第三栅极结构与伪晶体管相关联。
在该方法中,所述第二栅极结构与p型场效应晶体管相关联。
该方法进一步包括:在位于所述第一功函层下面的所述衬底上形成第一高k介电层;以及在位于所述第二功函层的下面的所述第一沟槽、所述第二沟槽和所述第三沟槽中形成第二高k介电层。
在该方法中,图案化所述第一功函层和所述多晶硅层进一步形成第四栅极结构,并且不从所述第四栅极结构中去除所述多晶硅层。
根据本发明的又一方面,提供了一种器件,包括:第一栅极结构,与第一类型的晶体管相关联并包括第一介电层和第一金属层;第二栅极结构,与第二类型的晶体管相关联并包括第二介电层、第二金属层、多晶硅层、所述第一介电层和所述第一金属层;以及伪栅极结构,包括所述第一介电层和所述第一金属层。
该器件进一步包括:第三栅极结构,与高阻抗场效应晶体管相关联,并且包括所述第一介电层、所述第一金属层和所述多晶硅层。
在该器件中,所述第三栅极结构的多晶硅层的厚度大于所述第二栅极结构的多晶硅层的厚度。
在该器件中,所述第二类型的晶体管是n型场效应晶体管。
在该器件中,所述第一类型的晶体管是p型场效应晶体管。
在该器件中,所述第一金属层是p型功函金属层,而所述第二金属层是n型功函金属层。
附图说明
当结合附图进行阅读时,根据以下详细描述可以更好地理解本发明的多个方面。应该强调的是,根据工业中的标准实践,各种部件没有被按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意地增加或减少。
图1是示出根据本发明的一个或多个方面制造半导体器件的方法的实施例的流程图。
图2至图17示出了根据图1的方法的一个或多个步骤的制造半导体器件的实施例的截面图。
具体实施方式
应该理解,为了实施本发明的不同部件,以下公开内容提供了许多不同的实施例或实例。以下描述元件和布置的具体实例以简化本公开内容。当然,这些仅仅是示例且并不打算进行限定。此外,以下描述的第一部件形成在第二部件上方可以包括其中第一部件和第二部件以直接接触形成的实施例,并且也可以包括其中以介于第一部件和第二部件之间的方式形成额外的部件,使得第一部件和第二部件不直接接触的实施例。为了简明和清楚,可以任意地以不同比例绘制各个部件。而且,就本公开内容提供平面晶体管的实例来说,本领域技术人员应该意识到,本公开内容也适用于多栅极器件,诸如鳍式场效应晶体管器件。
在图1中示出了制造半导体器件的方法100的流程图。方法100可用于在混合半导体器件上实施替换栅极方法。混合半导体器件包括具有不同配置的栅极结构(例如,具有不同的层成分、厚度等的栅叠层)的多个不同配置的器件。图2至图17是根据图1的方法100制造器件200的截面图。
应该理解,方法100包括具有互补金属氧化物半导体(CMOS)技术工艺流程特征的步骤,因此,本文仅简要地进行描述。可以在方法100之前、之后、和/或期间实施额外的步骤。类似地,一个步骤是可以识别出从本文所述的掺杂方法受益的器件的其他部分。
还应该理解,可以通过互补金属氧化物半导体(CMOS)技术工艺流程来制造半导体器件200的部分,因此,本文仅简要描述了一些工艺。而且,半导体器件200可以包括各种其他器件和部件,诸如,额外的晶体管、双极型晶体管、电阻器、电容器、二极管、熔丝等,但为了更好地理解本公开内容的发明概念而简化了该半导体器件。半导体器件200包括可以互连的多个半导体器件(例如,晶体管)。器件200示出了位于衬底的四个区域的每一区域中的单个栅极结构;这是为了简单和容易理解,而没有必要将实施例限制于任何数量的栅极结构、任何数量的区域、或区域结构的任何布置。
器件200可以是集成电路或其部分处理过程中所制造的中间器件,可以包括:静态随机存取存储器(SRAM)和/或其他逻辑电路;无源元件,诸如电阻器、电容器和电感器;以及有源元件,诸如P沟道场效应晶体管(PFET)、N沟道场效应晶体管(NFET)、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极型晶体管、高压晶体管、高频晶体管、其他存储单元和它们的组合。
方法100从框102开始,在半导体衬底上形成多个栅极结构。多个栅极结构可以包括介电层、金属栅极层(例如,功函材料)和伪层。在一个实施例中,伪层是多晶硅,然而,其他成分也是可能的。伪层可以是用于将被形成在衬底上的至少一个晶体管的牺牲层。伪层可以是用于将被形成在衬底上的至少一个晶体管的最终栅电极。栅极结构可以形成在衬底的不同区域中,例如,限定用于NFET器件的区域、限定用于PFET器件的区域、限定用于高阻晶体管的区域、限定用于非功能性晶体管(也称为伪晶体管)的区域和/或通过集成电路设计限定的其他合适区域。
参考图2的实例,示出了具有衬底202和在其上设置的多个栅极结构204的半导体器件200。
衬底202可以是硅衬底。可选地,衬底202可以包括另一种元素半导体,诸如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟,和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或者其组合。在又一个可选实施例中,衬底202是绝缘体上半导体(SOI)。
衬底202包括第一区域206、第二区域208、第三区域210和第四区域212。隔离结构216介于区域之间。在一个实施例中,第一区域206是n型场效应晶体管区域。在一个实施例中,第二区域208是p型场效应晶体管区域。在一个实施例中,第三区域210是高阻抗电阻器区域。在一个实施例中,第四区域212是伪晶体管(例如,非功能性晶体管)区域。第四区域212可以提供在衬底的导电层、半导体层、或绝缘层(例如,氧化硅)部分上的栅极结构。应该注意,这些区域仅仅是示例性的,并不打算进行类型、结构、布置等限制。
隔离结构216可以由氧化硅、氮化硅、氮氧化硅、掺氟硅酸盐玻璃(FSG)、低k介电材料和/或其他合适的绝缘材料形成。隔离结构216可以是浅沟槽隔离(STI)部件。在一个实施例中,隔离结构216是STI部件并通过在衬底202中蚀刻沟槽来形成。沟槽可以填充有隔离材料,然后进行化学机械抛光(CMP)。诸如场氧化物、LOCOS和/或其他合适结构的其他隔离结构216也是可以的。例如,隔离结构216可以包括具有一个或多个衬里层的多层结构。
栅极结构204包括界面层214、栅极介电层218和金属栅极层220。伪层222(例如,多晶硅)设置在金属栅极层220上。在一个实施例中,例如,栅极结构204可以进一步包括介于栅极介电层218和金属栅极层220之间的保护层。
界面层214可以包括诸如氧化硅层(SiO2)或氮氧化硅(SiON)的介电材料。界面层214可以通过化学氧化、热氧化、原子层沉积(ALD)、CVD、和/或其他合适的电介质形成。
介电层218可以是栅极介电层。栅极介电层218可以包括诸如氧化铪(HfO2)的高k介电层。可选地,高k介电层可以任选地包括其他高k电介质,诸如TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、它们的组合或者其他合适的材料。介电层218可以通过原子层沉积(ALD)和/或其他合适的方法形成。
金属栅极层220包括功函金属。功函值与功函层的材料成分相关联,因此,选择第一功函层的材料以调整其功函值,使得在将要形成在对应区域内的器件中实现期望阈值电压Vt。在一个实施例中,金属栅极层220是n型功函金属。可包括在栅极结构204中的示例性n型功函金属包括:Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其他合适的n型功函材料或者它们的组合。可以通过CVD、PVD、和/或其他合适的工艺沉积金属栅极层220。
多晶硅层222可以通过诸如低压化学气相沉积(LPCVD)和等离子增强CVD(PECVD)的合适的沉积工艺形成。在一个实施例中,硬掩模层设置在栅极结构上。在另一个实施例中,硬掩模层包括第一层224和第二层226。在实例中,第一层224包括氧化硅,在另一个实例中,第二层226包括氮化硅。
然后,方法100继续至框104,其中,形成源极区/漏极区。源极区/漏极区可以包括引入合适的掺杂剂类型:n型或p型掺杂剂。源极区/漏极区可以包括晕环注入或低剂量漏极(LDD)注入、源极/漏极注入、源极/漏极激活和/或其他合适的工艺。在其他实施例中,源极区/漏极区可以包括凸起的源极区/漏极区、应变区、外延生长区、和/或其他合适的技术。在另一个实施例中,源极/漏极激活工艺可以包括诸如在大约1010摄氏度(C)的温度下的快速热退火。参考图3的实例,示出了源极/漏极注入304。源极/漏极注入302可以称为晕环注入或LDD注入。参考图5的实例,示出了源极/漏极注入502。
在一个实施例中,密封层形成在栅极结构上。在诸如晕环注入或低剂量漏极(LDD)注入的源极/漏极形成之前,可以形成密封层。在一个实施例中,密封层包括氮化硅。参考图3的实例,密封层302形成在栅极结构204上。在一个实施例中,密封层302具有约30埃的厚度。此外,图3还示出了晕/LDD注入304。
在一个实施例中,在源极区/漏极区(或其部分)形成之前或之后,可以形成邻接栅极结构的侧壁的隔离元件。可以通过沉积介电材料,随后进行各项同性蚀刻工艺来形成隔离元件,然而,其他实施例也是可以的。在一个实施例中,隔离元件包括氧化硅、氮化硅和/或其他合适的电介质。隔离元件可以包括多个层。例如,在一个实施例中,隔离元件包括约的氧化物和约的氮化硅。
参考图4的实例,形成邻接栅极结构204的侧壁的隔离元件402。隔离元件402还可以称为主隔离壁。隔离元件402可以包括具有均匀厚度的衬里层(例如,氧化物)和诸如D形的隔离件的上面的主隔离层(例如,氮化物)。
在一个实施例中,框104包括硅化掺杂源极区/漏极区。硅化物材料可以包括硅化镍(NiSi)、镍铂硅化物(NiPtSi)、镍铂锗硅化物(NiPtGeSi)、镍锗硅化物(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)、其他合适的导电材料和/或它们的组合。硅化物部件可以通过包括以下步骤的工艺形成:沉积金属层;对金属层进行退火,使得金属层能够与硅发生反应以形成硅化物;然后去除未反应的金属层。在一个实施例中,通过在衬底上方沉积约的镍来形成硅化镍。参考图6的实施例,如上文参考图5所讨论的形成的源极区/漏极区进行硅化以形成硅化物区602。
然后,方法100继续至框106,在多个栅极结构上形成接触蚀刻停止层(CESL)和/或中间介电层。可以用于形成CESL的材料的实例包括氮化硅、氧化硅、氮氧化硅、和/或本领域公知的其他材料。CESL可以通过PECVD和/或其他合适的沉积或氧化工艺来形成。介电层可以包括材料,诸如正硅酸乙酯(TEOS)氧化物、未掺杂的硅玻璃、或者掺杂的氧化硅,诸如掺硼磷硅玻璃(BPSG)、熔融石英玻璃(FSG)、掺磷硅玻璃(PSG)、掺硼硅玻璃(BSG)、和/或其他合适的介电材料。可以通过PECVD工艺或其他合适的沉积技术来沉积介电层。参考图8的实例,CESL802和介电层804设置在衬底202上。
在一个实施例中,在形成CESL和/或中间介电层之前,可以实施隔离元件和/或硬掩模材料的部分去除。可以通过诸如包含高温H3PO4的湿蚀刻工艺的合适的工艺来进行隔离元件的部分去除。在一个实施例中,约120℃的H3PO4用于去除部分隔离元件(例如,SiN)。在一个实施例中,通过干蚀刻工艺去除硬掩模层。参考图7的实例,示出了隔离元件702,其中,减小隔离元件402(图4)的厚度并且去除硬掩模层224和226。CESL802和/或介电层804可以形成在隔离元件702上。
然后,方法100继续至框108,其中,实施平坦化工艺暴露栅极结构的顶面。平坦化工艺可以包括化学机械平坦化(CMP)。参考图9的实例,已实施平坦化工艺以形成表面902并且暴露栅极结构204的多晶硅层222。
然后,方法100继续至框110,在衬底(例如,提供第一类型晶体管的区域)的区域上形成硬掩模的掩模元件。在一个实施例中,形成均匀硬掩模层并且随后使用光刻和蚀刻(例如,干蚀刻)技术进行图案化。在一个实施例中,硬掩模层包括TiN。在一个实施例中,硬掩模层的厚度约为20埃硬掩模的掩模元件可以形成在提供特定晶体管类型(诸如高阻抗电阻)的衬底区域上。
参考图10的实例,硬掩模材料层1002形成在衬底202上。如图11所示,图案化硬掩模层1002以形成掩模元件1104。可以使用光刻胶掩模元件1102形成硬掩模的掩模元件1104。在一个实施例中,掩模元件1104设置在衬底202的第三区域210上。在又一个实施例中,掩模元件1004形成在衬底202提供高阻抗电阻的区域上方。然而,具有与掩模栅极结构相关联的不同功能的晶体管的其他实施例也是可以的。
然后,方法100继续至框112,其中,掩模元件形成在诸如与通过框110的掩模元件所限定的区域不同的衬底的另一区域上。在一个实施例中,框112的掩模元件形成在包括第二类型晶体管的衬底的区域上。在另一个实施例中,掩模元件形成在具有n型场效应晶体管和p型场效应晶体管中的一个的衬底的区域上。掩模元件可以包括使用诸如曝光和显影的合适工艺的图案化的光刻胶。参考图12的实例,光刻胶部件1202设置在衬底202上。光刻胶部件1202提供保护衬底202的第一区域206的掩模元件。在一个实施例中,光刻胶部件1202上覆与NFET器件相关联的栅极结构。
然后,方法100继续至框114,去除栅极结构层的部分。在一个实施例中,去除衬底的一个或多个区域内的栅极结构的部分多晶硅层。在一个实施例中,去除与PFET和/或伪栅极结构相关联的栅极结构的部分多晶硅层。在给定区域中,例如,多晶硅层的厚度可以减小约50%。可以使用合适的湿蚀刻、干蚀刻、等离子体蚀刻、和/或其他工艺来蚀刻多晶硅层。
参考图12的实例,设置在衬底202的第二区域208和第四区域212的栅极结构204中的多晶硅层222的厚度减小,以提供多晶硅层1204。在一个实施例中,第二区域208设置有与PFET器件相关联的栅极结构。在一个实施例中,第四区域212设置有与伪器件相关联的栅极结构。
然后,方法100继续至框116,其中,去除掩模元件。以上参考框112描述的掩模元件(例如,光刻胶)可以从衬底上去除。在一个实施例中,以上参考框110描述的硬掩模的掩模元件可以保持在衬底上。参考图13的实例,从衬底202去除掩模元件1202和1102(参见图12)。去除掩模元件暴露了衬底202的第一区域206、第二区域208和第四区域212的栅极结构。
然后,方法100继续至框118,去除部分栅极结构以形成沟槽。在一个实施例中,可以去除栅极结构在衬底的一个或多个区域中的剩余多晶硅层,并且栅极结构在衬底的另一个区域内的多晶硅层的厚度可以减小。硬掩模的掩模元件可以保护衬底的又一个区域中的栅极结构。参考图13的实例,衬底的第一区域206内的栅极结构204具有通过部分去除多晶硅层222所形成的沟槽1302。衬底的第二区域208内的栅极结构204具有通过去除部分多晶硅层1204(例如,在指定区域内全部去除多晶硅层222)所形成的沟槽1304。衬底的第四区域212内的栅极结构204具有通过部分去除多晶硅层1204(例如,在指定区域内全部去除多晶硅层222)所形成的沟槽1306。应该注意,在去除整个多晶硅层222之后和/或通过去除整个多晶硅层222的位置中,暴露金属层220和介电层218。还可以去除金属层220和介电层218(参见沟槽1304和1306)。在一个实施例中,界面层216保持在沟槽1304和/或1306中,然而,其他实施例是可以的。
然后,方法100继续至框120,其中,在通过方法100的框118和/或112所提供的沟槽中形成金属栅极。形成的金属栅极也可以包括栅极介电层、保护层、填充层和/或其他合适的层。金属栅极包括的功函金属层可以是n型功函层或p型功函层。示例性p型功函材料包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN,其他合适的p型功函材料或者它们的组合。示例性n型功函材料包括Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr,其他合适的n型功函材料或者它们的组合。功函层可以包括多个层。可以通过CVD、PVD、和/或其他合适工艺来沉积功函层。在一个实施例中,形成的金属栅极是包括p型功函层的p型金属栅极。
金属栅极结构的介电层可以包括高k介电层,诸如氧化铪(HfO2)。可选地,高k介电层可以可选地包括其他高k电介质,诸如TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、它们的组合或者其他合适的材料。可以通过ALD和/或其他合适的方法来形成介电层。介电层可以具有与在以上在框102中所述的栅极结构内形成的介电层的相同组成或不同组成。
金属栅极结构的填充层可以包括AL、W、或Cu和/或其他合适的材料。填充金属可以通过CVD、PVD、电镀、和/或其他合适的工艺形成。填充金属可以沉积在功函金属层的上方,从而填充在沟槽或开口的剩余部分中。
参考图14的实例,栅极介电层1402形成在衬底上。栅极介电层1402可以是如以上所讨论的高k电介质。金属层1404形成在栅极介电层1402上。金属层1404可以是功函金属层。在一个实施例中,金属层1404具有与金属栅极层220相反的导电型(n型或p型)。在一个实施例中,金属层1404是p型功函层。填充金属层1406形成在金属层1404上,以填充剩余沟槽(图13中的沟槽1302、1304和1306)。
在形成栅极介电层1402、金属层1404和填充层1406之后,可以实施平坦化工艺。参考图15的实例,平坦化图14的器件,以从介电层804的表面去除金属栅极层。
因此,栅极结构1502形成在衬底202的第一区域206中。栅极结构1502包括界面层214、介电层218、金属层220、多晶硅层222、介电层1402、金属层1404和填充层1406。在一个实施例中,金属栅极层220提供栅极结构1502的功函值。在一个实施例中,栅极结构1502提供用于NFET器件的栅极。
此外,栅极结构1504形成在衬底202的第二区域208内。栅极结构1504包括界面层214、介电层1402、金属层1404和填充层1406。在一个实施例中,金属层1404提供栅极结构1504的功函值。在一个实施例中,栅极结构1504提供用于PFET器件的栅极。
此外,栅极结构1506形成在衬底202的第三区域210中。可以通过平坦化工艺去除硬掩模层1104。栅极结构1506包括界面层214、介电层218、金属层220、多晶硅层222。在一个实施例中,栅极结构1506提供了用于高阻抗器件的栅极。
最后,栅极结构1508形成在衬底202的第四区域212中。栅极结构1508包括界面层214、介电层1402、金属层1404和填充层1406。在一个实施例中,栅极结构1508提供了用于伪器件的栅极。应该注意,栅极结构1504可以形成在衬底202的导电部分上或形成在隔离区上。
应该注意,可以通过图15示出了方法100的一个优点。在平坦化衬底202期间,栅极结构1508提供了合适的平坦化停止层,例如,由于包括在栅极结构1508内的金属层减少了凹陷效果。例如,通过栅极结构1508所设置的材料的强度或硬度来抵消衬底的第四区域212的下压力。
然后,方法100继续至框122,其中,形成层间介电(ILD)层。ILD层可以包括介电材料,诸如正硅酸乙酯(TEOS)氧化物、未掺杂硅玻璃,或掺杂氧化硅(诸如掺硼磷硅玻璃(BPSG)、熔融石英玻璃(FSG)、掺磷硅玻璃(PSG)、掺硼硅玻璃(BSG)和/或其他合适的介电材料。可以通过PECVD工艺或其他合适的沉积技术来沉积ILD层。ILD层可以具有与以上在框106中描述的介电层的相同组成或不同组成。
参考图16的实例,ILD层1602设置在衬底202上。介电层1602包括介电层804和以上参考图15描述的平坦化栅极结构之后沉积的介电材料。介电层1602可以包括一种或多种介电材料组成。ILD层1602的厚度可以是约
然后,方法100继续至框124,其中,形成与衬底202上的一个或多个部件的接触件。接触件可以提供与多层互连件(MLI)的一个或多个互连层的互连。接触可以包括钨或其他合适的导电元素。可以通过在ILD层中蚀刻沟槽或开口并且通过要形成通孔的导电材料填充沟槽来形成接触件。参考图17的实例,接触件1702形成在衬底202上。接触件1702提供与源极区/漏极区和/或栅极结构的电连接。
总之,本文所公开的方法和器件提供在衬底上的具有混合(或不同)布置的栅极结构的方法和器件。在一个实施例中,先栅极工艺用于限定一种类型的晶体管(例如,NFET),而后栅极或替换栅极类型的方法用于限定另一类晶体管(例如,PFET)。在另一个的实施例中,提供伪栅极(或非功能型栅极),然后,用于限定第二晶体管类型的后栅极或替换栅极类型的方法。因此,在一个实施例中,在衬底上设置PFET伪器件。在这种情况下,本公开内容提供了可以优于现有技术器件的优点的实施例。例如,使用图1中方法的实施例可以改善穿过衬底和/或衬底区域的栅极高度变化、CMP引起的过抛光、CMP引起的欠抛光(例如,参见传统替换栅极方法)。一种类型的栅极结构(例如,PFET)的整体图案化密度可以增加(有源器件和伪器件)。在一个实施例中,具有使用替换栅极方法形成的金属栅极(例如,栅极形成在源极/漏极和/或通过填充由去除第一栅极结构提供的沟槽之后)的器件的整体图案化密度增加。应该理解,本文公开的不同实施例提供了不同公开内容,并且可以在不背离本公开内容的主旨和范围的情况下,本文可以进行各种改变、替换和更改。
Claims (18)
1.一种制造半导体器件的方法,包括:
形成包括第一栅极介电层、第一金属层以及上覆所述第一栅极介电层和所述第一金属层的伪层的多个栅极结构;
在第三栅极结构上形成掩蔽元件;
从所述多个栅极结构的第一栅极结构和第二栅极结构中去除所述伪层的第一部分,同时所述掩蔽元件设置在所述第三栅极结构上;
在去除所述伪层的第一部分之后,从所述第三栅极结构处去除所述掩蔽元件;
在去除所述掩蔽元件之后,去除所述伪层的第二部分,其中,所述第二部分包括所述第一栅极结构和所述第二栅极结构中所述伪层的剩余部分,其中,去除所述伪层的第二部分在所述第一栅极结构中提供第一沟槽以及在所述第三栅极结构中提供第二沟槽,其中,所述第一沟槽的深度大于所述第二沟槽的深度;以及
在所述第一沟槽和所述第二沟槽中形成第二栅极介电层和第二功函金属层。
2.根据权利要求1所述的方法,其中,所述第三栅极结构与N型场效应晶体管相关联。
3.根据权利要求2所述的方法,其中,所述第一栅极结构与P型场效应晶体管相关联,并且所述第二栅极结构是伪栅极结构。
4.根据权利要求1所述的方法,进一步包括:
在去除所述伪层的第一部分之前,在所述多个栅极结构的第四栅极结构上方形成硬掩模层和所述掩蔽元件。
5.根据权利要求1所述的方法,其中,从所述第一栅极结构和第二栅极结构中去除所述伪层的第二部分进一步包括:去除所述第一栅极结构和所述第二栅极结构的第一栅极介电层和第一金属层。
6.根据权利要求1所述的方法,进一步包括:
通过从所述第二栅极结构中去除所述伪层的第二部分来创建第三沟槽,其中,所述第二栅极结构是非功能性栅极;以及
在所述第三沟槽中形成所述第二栅极介电层和所述第二功函金属层。
7.根据权利要求1所述的方法,其中,所述第一金属层是n型功函材料,而所述第二功函金属层是p型功函材料。
8.一种半导体器件制造方法,包括:
在衬底上形成第一功函金属层和上覆多晶硅层;
图案化所述第一功函金属层和所述上覆多晶硅层以形成第一栅极结构、第二栅极结构和第三栅极结构;
在所述第一栅极结构上形成掩模元件;
实施所述多晶硅层的第一蚀刻,使得从所述第二栅极结构和所述第三栅极结构中去除所述多晶硅层的一部分,同时所述掩模元件设置在所述第一栅极结构上;
在去除所述第一栅极结构上的所述掩模元件之后,实施所述多晶硅层的第二蚀刻,使得从所述第一栅极结构中去除所述多晶硅层的一部分以形成第一沟槽,并且从所述第二栅极结构和所述第三栅极结构中去除所述多晶硅层的一部分以形成第二沟槽和第三沟槽;以及
在所述第一沟槽、所述第二沟槽和所述第三沟槽中形成第二功函金属层。
9.根据权利要求8所述的方法,其中,所述第三栅极结构与伪晶体管相关联。
10.根据权利要求9所述的方法,其中,所述第二栅极结构与p型场效应晶体管相关联。
11.根据权利要求8所述的方法,进一步包括:
在位于所述第一功函层下面的所述衬底上形成第一高k介电层;以及
在位于所述第二功函层的下面的所述第一沟槽、所述第二沟槽和所述第三沟槽中形成第二高k介电层。
12.根据权利要求8所述的方法,其中,图案化所述第一功函层和所述多晶硅层进一步形成第四栅极结构,并且不从所述第四栅极结构中去除所述多晶硅层。
13.一种器件,包括:
第一栅极结构,与第一类型的晶体管相关联并包括第一介电层和第一金属层;
第二栅极结构,与第二类型的晶体管相关联并包括第二介电层、第二金属层、多晶硅层、所述第一介电层和所述第一金属层;以及
伪栅极结构,包括所述第一介电层和所述第一金属层,其中,所述伪栅极结构与所述第一栅极结构和所述第二栅极结构彼此隔离,以作为平坦化停止层。
14.根据权利要求13所述的器件,进一步包括:
第三栅极结构,与高阻抗场效应晶体管相关联,并且包括所述第一介电层、所述第一金属层和所述多晶硅层。
15.根据权利要求14所述的器件,其中,所述第三栅极结构的多晶硅层的厚度大于所述第二栅极结构的多晶硅层的厚度。
16.根据权利要求13所述的器件,其中,所述第二类型的晶体管是n型场效应晶体管。
17.根据权利要求15所述的器件,其中,所述第一类型的晶体管是p型场效应晶体管。
18.根据权利要求13所述的器件,其中,所述第一金属层是p型功函金属层,而所述第二金属层是n型功函金属层。
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