CN103311231B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103311231B
CN103311231B CN201310074887.4A CN201310074887A CN103311231B CN 103311231 B CN103311231 B CN 103311231B CN 201310074887 A CN201310074887 A CN 201310074887A CN 103311231 B CN103311231 B CN 103311231B
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terminal
housing
semiconductor devices
wiring terminals
circuit
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CN103311231A (zh
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铃木健司
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

提供了一种半导体器件及其制造方法，通过该半导体器件及其制造方法，有可能确保结合强度和耐压并且减小该器件的外形尺寸。在左右方向上，在壳体的正面侧的端子组装部在从壳体底部凸起的部分中对齐，以使端子组装部的开口面位于电路形成区上方。布线端子板被引出到端子组装部中，并且彼此相邻地设置。在每一布线端子板通过激光焊接连接到与盖子一体地形成的一个外部连接端子板的一端之后，这些焊接部用由凝胶或者诸如环氧树脂之类的绝缘树脂制成的第二模制树脂部密封。通过这样做，即使在端子组装部中的各端子结之间的端子结合面积和距离小时，也有可能增加各端子的结合强度并且还确保耐压。

Description

半导体器件及其制造方法
技术领域
本发明涉及在壳体中具有包括多个半导体元件的电路形成区的半导体元件以及该半导体器件的制造方法，具体地涉及其中多个半导体元件从嵌入壳体的布线端子板通过外部连接端子板电连接到在壳体的外周部上形成的外部端子的半导体器件以及该半导体器件的制造方法。
背景技术
近年来，已尝试了减少使用诸如绝缘栅双极晶体管（IGBT）之类的多个半导体元件来转换高电功率的逆变器电路的大小和重量。在JP-A-08-148645中描述了诸如使用公共IGBT模块的功率模块之类的半导体器件（例如，参考段落[0003]和图1）。
即，首先，诸如IGBT之类的半导体芯片或者二极管芯片通过焊料等连接到在绝缘基板上形成的铜图案，并且此外，绝缘基板连接到冷却底板。随后，预定壳体安装在冷却底板周围，并且半导体芯片的电极和绝缘基板上的铜图案通过接合铝线连接到结合在壳体中的金属端子板，从而在金属端子板与电极和铜图案之间进行电连接。由热塑树脂制成的包封绝缘基板的外封壳体通过粘合剂固定到冷却底板，并且此外，为了保护半导体芯片和接合铝线，诸如凝胶或环氧树脂之类的绝缘材料被注入壳体并固化。最后，外部连接端子板通过激光焊接等连接到结合在壳体中的金属端子板和外部端子，从而在金属端子板和外部端子之间进行连接。
同样，JP-A-2009-141000（例如，参考段落[0024]至[0042]以及图1）公开了具有由树脂壳体容纳的多个半导体元件的半导体器件，其中有可能容易地改变布线端子的设置。半导体器件包括固定和支撑在树脂壳体中的多个外部连接端子、容纳在树脂壳体中的至少一个半导体元件、以及在其上设置有电连接半导体元件和外部连接端子的至少一个布线端子的至少一个端子块。通过该半导体器件，由于固定在树脂壳体中的外部连接端子和金属箔通过端子块电连接，因此有可能容易地实现树脂壳体中的布线端子的走线。同样，即使在外部连接端子固定和支撑在树脂壳体中的情形中，也有可能通过使用在布线图案中改变的布线端子预先制备一些种类的端子块来自由地改变从外部连接端子走线的布线端子的设置。
此外，JP-A-2010-103343（例如，参考段落[0009]至[0037]以及图1和2）中的半导体器件包括树脂壳体、容纳在树脂壳体中的半导体元件、容纳在树脂壳体中的包括用于控制半导体元件的动作的控制单元的印刷电路板、以及覆盖容纳在树脂壳体中的半导体元件和印刷电路板的盖部，其中印刷电路板的外周被树脂壳体和盖部夹持。通过这种配置，有可能实现对来自外部的振动以及冷热周期具有足够抗性的可靠性高的半导体器件。
通过已知半导体器件的配置，期望减小壳体的大小，并且同时可根据来自用户的需求自由地确定壳体的形状和大小、外部端子的位置等。在此情况下，从半导体器件设计的立场，从密封在壳体内部的半导体芯片直接取出外部连接端子不是优选的。
因此，如上述JP-A-2009-141000所示，采用了其中半导体元件经由内部连接布线端子电连接到设置在壳体的外周部上的外部连接端子的配置。然而，在需要如在IGBT模块中的多个外部连接端子的半导体器件中，端子必须彼此间隔开特定距离以确保各端子之间的绝缘。为此，在具有其中多个内部布线端子板连接到壳体内部的外部连接端子的配置的半导体器件中，需要将壳体本身的大小增加到特定程度。
响应于此，有可能通过预先将内部布线端子板引导到壳体外部来减小壳体的大小，并且内部布线端子板和外部连接端子在壳体外部通过激光焊接刚性地连接。然而，当内部布线端子板的连接部在壳体外部露出时，这些连接部可能使结合强度劣化。为此，已知配置为通过增加激光焊接部的焊接面积来确保结合强度，并且同时还防止连接部因在半导体芯片中产生的热而劣化。同样，为了维持引导到壳体外部的各布线端子板之间的绝缘，需要使各布线端子板的结彼此较宽地间隔开。
发明内容
鉴于这些观点而构想的本发明的目的在于，提供半导体器件及其制造方法，通过该半导体器件及其制造方法有可能确保结合强度和耐压，并且同时减小该器件的外部尺寸。
本发明提供了在壳体中具有包括多个半导体元件的电路形成区的半导体器件。半导体器件包括：多个布线端子板，每一布线端子板电连接到多个半导体元件之一；端子组装部，其中组装有从电路形成区引出的多个布线端子板；多个外部连接端子板，每一外部连接端子板的一端连接到端子组装部中的多个布线端子板之一，且其他端延伸到设置在壳体上的外部端子部；以及模制树脂部，该模制树脂部通过填充端子组装部的树脂对布线端子板和外部连接端子板的连接部进行绝缘和保护。
同样，本发明的半导体器件制造方法是在壳体中具有包括多个半导体元件的电路形成区的半导体的制造方法。该半导体器件制造方法包括：将半导体元件焊接到构成电路形成区的绝缘基板的步骤；在绝缘基板上安装与多个布线端子板一体配置的壳体、设置在壳体的外表面中的彼此相邻的端子组装部、以及在壳体的外周部上的预定位置处的外部端子部的步骤；电连接半导体元件和布线端子板的引线接合步骤；通过模制树脂对电路形成区中的引线和半导体元件进行绝缘和保护的第一密封步骤；使用与延伸形成到外部端子部的外部连接端子板一体地形成的盖体来覆盖壳体中的所述电路形成区的步骤；以及将外部连接端子板连接到端子组装部中的布线端子板、并且通过模制树脂对这些连接部进行绝缘和密封的第二密封步骤。
根据本发明，有可能确保各布线端子的结的结合强度以及各外部连接端子之间的耐压，并且同时减小半导体器件的外部尺寸。
附图说明
图1是示出根据本发明的一个实施例的半导体器件的平面俯视图；
图2是沿着图1中的半导体器件的截面II-II取得的截面图；
图3是沿着图1中的半导体器件的截面III-III取得的截面图；以及
图4是示出本发明的半导体器件的制造工艺的示图。
具体实施方式
在下文中，将参考附图给出对本发明的一个实施例的描述。图1是示出根据本发明的实施例的半导体器件的平面俯视图。
半导体器件具有通过将矩形壳体1内部分成例如六个区域而设置的由点划线示出的电路形成区A至F，并且由诸如IGBT之类的半导体元件构成的逆变器电路设置在电路形成区A至F中的每一个电路形成区中。针对壳体1中的每一对电路形成区A和D、B和E、以及C和F，形成一对逆变器电路。
控制端子2是通过其向电路形成区A至F中的逆变器电路供应控制信号的端子，并且嵌入与其对应电路形成区A至C以及D至F相邻的壳体1的相应前后方向的外周侧壁11和13。壳体1还包括左右方向的外周侧壁12和14，并且壳体1的外形基本上是长方体。在电路形成区A至C以及D至F之间的壳体1内部的中间部分中，端子组装部31至33在从壳体1的底部凸起的部分中形成，并且如从壳体1的顶部侧可见，端子组装部31至33的开口面在左右方向上对齐地设置。另外，在这些端子组装部31至33中，端子组装部32形成在与两个相邻的电路形成区B和E等距的位置处，并且从相应电路形成区B和E引出的布线端子板4a、4b和4c彼此相邻地设置在端子组装部32中。
同样，端子组装部31形成在与两个相邻的电路形成区A和D等距的位置处，并且以相同的方式，端子组装部33形成在与两个相邻的电路形成区C和F等距的位置处，其中相同的布线端子板4a、4b和4c还设置在端子组装部31和33中的每一端子组装部中。在图1中，只示出引出到其中的端子组装部32以及布线端子板4a、4b和4c的形状，并且只有端子组装部31和33的外形由虚线示出，同时省略与端子组装部31和33相对应的布线端子板4a、4b和4c的图示。
以此方式，电连接到在每一电路形成区A至F中形成的半导体元件的布线端子板4a、4b和4c中的每一布线端子板的一端被引出到每一端子组装部31至33中的壳体1的外表面。通过电路形成区A至F上方的顶部有盖5的壳体1的各开口部分，除端子组装部31至33以外的壳体1中的电路形成区A至F的各部分最终全部与外部屏蔽开。由图1中的点划线示出的外部连接端子板5a、5b和5c一体地嵌入盖5。即，通过将盖5设置在壳体1的顶部，外部连接端子板5a、5b和5c连接到从相应电路形成区B和E引出到端子组装部32中的三个布线端子板4a、4b和4c。
外部连接端子板5a的一端通过多个（例如，如图1所示的10个）激光焊接部Lb连接到从电路形成区B和E引出到端子组装部32中的布线端子板4a、4b和4c中的布线端子板4a。此外，外部连接端子板5a的另一端构成壳体1的正向侧壁11的外周部上的外部端子部6a。同样，外部连接端子板5b的一端通过激光焊接部Lb连接到从电路形成区B引出到端子组装部32中的布线端子板4b。此外，外部连接端子板5b的另一端在壳体1的背向上经由构成侧壁13的外周部上的外部端子部6b的电路形成区D和E之间的部分延伸。以相同的方式，外部连接端子板5c的一端通过激光焊接部Lb连接到从电路形成区E引出到端子组装部32中的布线端子板4c。此外，外部连接端子板5c的另一端在壳体1的背向上经由构成侧壁13的外周部上的外部端子部6c的电路形成区E和F之间的部分延伸。
在此，在图1中只示出与端子组装部32相对应的外部连接端子板5a、5b和5c，但是同样在端子组装部31和33中，与其相对应的外部连接端子与盖5一体地形成并且彼此绝缘。
接着，将给出对容纳在半导体器件的壳体1内部的半导体电路的描述。
图2是沿着图1中的半导体器件的截面II-II取得的截面图，并且图3是沿着图1中的半导体器件的截面III-III取得的截面图。
半导体芯片22通过焊料23a接合到绝缘基板24的一侧。导电层24a、24b和24c接合到绝缘基板24的每一相应表面，并且构成用于散热的冷却底板7的铜板等通过焊料23b接合到与半导体芯片22相对的一侧。壳体1通过粘合剂固定到冷却底板7以包围绝缘基板24，并且诸如前述布线端子板4a、4b和4c之类的金属板以及控制端子2结合到壳体1中。
半导体芯片22的一个电极和绝缘基板24的导电层24a通过铝线25等连接，半导体芯片22的控制电极和控制端子2通过铝线25等连接，并且此外，导电层24a和布线端子板4a通过铝线25等连接。以此方式，壳体1的底部由冷却底板7构成，并且多个半导体元件设置在如电路形成区B的底部的上表面上。在图2中只示出与特定半导体元件（诸如IGBT）相关的在电路形成区B中形成的逆变器电路的配置。
随后，壳体1的电路形成区A至C中的每一电路形成区用由凝胶或者诸如环氧树脂之类的绝缘树脂制成的第一模制树脂部8密封。铸造到壳体1内部中的凝胶或者诸如环氧树脂之类的绝缘树脂固化，由此保护半导体芯片的内部结构、铝线等。
接着，在壳体12的顶部设置有盖5之后，与盖一体地形成的外部连接端子板5a至5c中的每一外部连接端子板的一端与端子组装部32中的其对应的布线端子板4a至4c接触。即，如前所述，位于壳体1的正面侧的端子组装部31至33在从壳体1底部高高凸起的凸起部15的顶部侧形成，并且端子组装部31至33的周壁部被配置成与盖5的上表面齐平。
此时，图3所示的端子组装部32中的布线端子板4a至4c为其连接部在不同的高度处嵌入壳体1的凸起部15，从而相应的外部连接端子板5a、5b和5c可在彼此不同的高度方向位置处连接到布线端子板4a至4c。在图3中的截面图中，省略与端子组装部32相邻的端子组装部31和33中的布线端子板4a至4c等。
以此方式，即使在布线端子板4a至4c被设置成在端子组装部32中在左右方向上彼此接近时，连接有外部连接端子板5a至5c的布线端子板4a至4c也可通过在高度方向上彼此相距一距离而彼此间隔开足够的绝缘距离。因此，由于即使在壳体1中形成的端子组装部31至33的面积被设计成较小时也有可能确保各端子之间的耐压，因此容易减小半导体器件的壳体1的大小。
同样，上述半导体器件使得在单个端子组装部32中，外部连接端子板5a至5c通过激光焊接连接到多个布线端子板4a至4c等，并且此外，这些焊接部用由凝胶或者诸如环氧树脂之类的绝缘树脂制成的第二模制树脂部9密封。通过这样做，即使在半导体器件的布线端子板4a至4c彼此接近时，也有可能确保耐压。
此外，由于焊接部受第二模制树脂部9保护，因此有可能确保外部连接端子板5a、5b和5c与布线端子板4a、4b和4c之间的连接的机械强度的大小足够。由于树脂提供了一部分机械强度，因此有可能减少各端子板之间的连接所需的焊接面积，并且由此有可能减少激光焊接部Lb的结合点的数量。因此，有可能在不减小连接到外部电子设备的外部端子部6a、6b和6c与经由布线端子板4a至4c电连接的半导体芯片22之间的连接强度的情况下减小半导体器件的整体大小。
在半导体器件的上述示例中，配置为在其顶部侧具有开口的空间部在壳体1的凸起部15中形成、且构成第二模制树脂部9的绝缘树脂被铸造到该空间部中，但是配置也可以是开口部设置在盖5中、且构成第二模制树脂部9的绝缘树脂被铸造到该开口部中。
同样，在上述示例中，配置为外部连接端子板5a、5b和5c中的每一外部连接端子板的一端通过激光焊接部Lb连接到其对应的布线端子板4a、4b和4c，但是配置也可以是容纳在端子组装部中的布线端子板的数量为至少一个且第一外部连接端子板连接到第一布线端子板。同样，配置可以是布线端子板的数量为至少两个且第一外部连接端子板和第二外部连接端子板分别连接到第一布线端子板和第二布线端子板。此外，配置可以是外部连接端子板的基本中央部（而非一端）连接到布线端子板且外部连接端子板的每一端设置在该壳体的侧壁上。当容纳在端子组装部中的布线端子板的数量也是一个或两个时，通过绝缘树脂确保各外部连接端子之间的耐压和结的结合强度。
图4是示出本发明的半导体器件的制造工艺的示图。
在步骤ST1，将半导体芯片22焊接到每一绝缘基板24上的导电层24b等，由此构成形成逆变器电路的多个电路形成区A至F。此时，绝缘基板24可设置在冷却底板7上且焊接到冷却底板7。
在步骤ST2，制备与多个布线端子板4a、4b和4c、在外表面中设置成彼此接近的端子组装部31至33、以及在外周部上的预定位置处的外部端子部6a、6b和6c一体地配置的壳体1，并且将其安装在绝缘基板24上（参考图1和2）。此时，作为用于将设置在电路形成区A至F中的半导体芯片22所产生的热散发到外部的散热金属板的冷却底板7被用作壳体1的底板。配置可以是使用例如粘合剂将壳体1固定到冷却底板7。
在步骤ST3，半导体芯片22的一个电极和绝缘基板24的导电层24a通过铝线25等连接，半导体芯片22的控制电极和控制端子2通过铝线25等连接，并且此外，导电层24a和布线端子板4a通过铝线25等连接（参考图2）。
在步骤ST4，通过模制树脂对电路形成区A-F中的铝线25、半导体芯片22等进行绝缘和密封（第一密封步骤）。
在步骤ST5，在壳体1的顶部设置盖5。通过这样做，覆盖壳体1中的电路形成区A至F，并且分散地设置在壳体1的外周部上的外部端子部6a、6b和6c以及设置在端子组装部31至33中的布线端子板4a至4c经由与盖5一体形成的外部连接端子板5a、5b和5c相接触。
在步骤ST6，外部连接端子板5a、5b和5c通过激光焊接连接到其与布线端子板4a至4c的连接部（参考图2和3）。
在步骤ST7，通过模制树脂对端子组装部31至33中的激光焊接连接部进行绝缘和密封（第二密封步骤）。
上述制造工艺是其中外部连接端子板5a至5c与覆盖电路形成区A至F的盖5一体地配置的一个示例，但是本发明不限于此。例如，当与盖5分开地制备外部连接端子板5a至5c时，通过省略在壳体1的顶部设置盖5的步骤ST5，壳体1的整体也可在第二密封步骤（步骤ST7）之后用该盖覆盖。

Claims (10)

1.一种半导体器件，所述半导体器件在壳体中具有包括多个半导体元件的电路形成区，所述半导体器件包括：
多个布线端子板，每一布线端子板电连接到所述多个半导体元件之一；
端子组装部，其中组装有从所述电路形成区引出的所述多个布线端子板；
多个外部连接端子板，每一外部连接端子板的一端连接到所述端子组装部中的所述多个布线端子板之一，且其他端延伸到设置在所述壳体上的外部端子部；以及
模制树脂部，所述模制树脂部通过填充端子组装部的树脂对所述布线端子板和外部连接端子板的连接部进行绝缘和保护。
2.如权利要求1所述的半导体器件，其特征在于，
所述外部端子部分散地设置在所述壳体的外周部上。
3.如权利要求1所述的半导体器件，其特征在于，
所述多个布线端子板具有用于在所述端子组装部中在高度方向的彼此不同的位置处与所述外部连接端子板连接的连接部。
4.如权利要求1所述的半导体器件，其特征在于，
所述多个布线端子板各自与所述壳体一体地构成。
5.如权利要求1所述的半导体器件，其特征在于，
所述端子组装部形成在所述壳体的正面侧，并且所述端子组装部的开口面位于所述电路形成区上方。
6.如权利要求1所述的半导体器件，其特征在于，
当在所述壳体中形成分成多个区域的所述电路形成区时，组装有从相应电路形成区引出的所述多个布线端子板的所述端子组装部形成在与所述多个电路形成区等距的位置处。
7.如权利要求1所述的半导体器件，其特征在于，
所述外部连接端子板与覆盖所述电路形成区的盖部一体地构成。
8.如权利要求1所述的半导体器件，其特征在于，
在所述端子组装部中，所述外部连接端子板通过激光焊接连接到所述布线端子板。
9.如权利要求1所述的半导体器件，其特征在于，
所述壳体包括用于将设置在所述电路形成区中的所述半导体元件所产生的热散发到外部的散热金属板作为其底板。
10.一种用于制造半导体器件的方法，所述半导体器件在壳体中具有包括多个半导体元件的电路形成区，所述方法包括：
将半导体元件焊接到构成所述电路形成区的绝缘基板；
在所述绝缘基板上安装与多个布线端子板一体地构成的壳体、设置在所述壳体的外表面中的彼此相邻的端子组装部、以及在所述壳体的外周部上的预定位置处的外部端子部；
使所述半导体元件和所述布线端子板电连接的引线接合步骤；
通过模制树脂对所述电路形成区中的引线和半导体元件绝缘和密封的第一密封步骤；
使用与延伸形成到所述外部端子部的外部连接端子板一体地形成的盖体来覆盖所述壳体中的所述电路形成区；以及
将所述外部连接端子板连接到所述端子组装部中的所述布线端子板、并且通过模制树脂对所述连接部进行绝缘和密封的第二密封步骤。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5398160A (en) * 1992-10-20 1995-03-14 Fujitsu General Limited Compact power module with a heat spreader
US5621243A (en) * 1993-12-28 1997-04-15 Hitachi, Ltd. Semiconductor device having thermal stress resistance structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3274926D1 (en) * 1981-05-12 1987-02-05 Lucas Ind Plc A multi-phase bridge arrangement
JPH08148645A (ja) 1994-11-25 1996-06-07 Hitachi Ltd 樹脂封止型半導体装置
JP2002246515A (ja) * 2001-02-20 2002-08-30 Mitsubishi Electric Corp 半導体装置
US7149088B2 (en) * 2004-06-18 2006-12-12 International Rectifier Corporation Half-bridge power module with insert molded heatsinks
JP5176507B2 (ja) * 2007-12-04 2013-04-03 富士電機株式会社 半導体装置
JP5256994B2 (ja) 2008-10-24 2013-08-07 富士電機株式会社 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5398160A (en) * 1992-10-20 1995-03-14 Fujitsu General Limited Compact power module with a heat spreader
US5621243A (en) * 1993-12-28 1997-04-15 Hitachi, Ltd. Semiconductor device having thermal stress resistance structure

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