CN103227156A - 用于带有失效开放机构的电子封装的系统和方法 - Google Patents

用于带有失效开放机构的电子封装的系统和方法 Download PDF

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CN103227156A
CN103227156A CN2013100355447A CN201310035544A CN103227156A CN 103227156 A CN103227156 A CN 103227156A CN 2013100355447 A CN2013100355447 A CN 2013100355447A CN 201310035544 A CN201310035544 A CN 201310035544A CN 103227156 A CN103227156 A CN 103227156A
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semiconductor packages
thermally expansible
circuit board
expansible material
temperature
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CN103227156B (zh
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K.K.古
C.B.马贝拉
陈爱敏
G.韦特里韦尔佩里亚萨米
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Infineon Technologies AG
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Abstract

本发明涉及用于带有失效开放机构的电子封装的系统和方法。根据一个实施例,一种半导体封装包括:被配置为被安装在电路板上的第一表面;和可热膨胀材料的区域,该可热膨胀材料的区域被配置为当可热膨胀材料的温度超过第一温度时将半导体封装的第一表面推离电路板。

Description

用于带有失效开放机构的电子封装的系统和方法
技术领域
本发明的实施例一般地涉及电子构件封装,并且更加具体地涉及一种用于带有失效开放(fail-open)机构的电子封装的系统和方法。 
背景技术
功率半导体器件诸如功率金属氧化物半导体场效应晶体管(MOSFET)器件在从工业应用诸如重型机械到消费者应用诸如暖通空调(HVAC)系统、配电系统和汽车系统的各种各样的应用中已经变得普遍。功率半导体器件是有用的,因为它们能够利用具有小的形状因子的全固态器件替代机械开关和继电器。然而,在某些情况中,功率半导体器件可能由于器件失效而造成安全风险。例如,功率MOSFET器件可能在由于导致低欧姆状态的介质击穿或者金属化短路引起的短路条件中失效。在这个低欧姆状态中,在延长的持续时间中失去了对MOSFET的栅极的控制,从而导致器件的局部电阻性加热,这可以在器件内形成热斑。随着时间,这个加热可以导致MOSFET器件的封装、在其上安装器件的印刷电路板(PCB)和/或在其中安设器件的系统的、非期望的热引燃。 
在其中安全性是主要的顾虑的系统中,诸如在汽车中,功率半导体器件的热引燃是特别地危险的。如果在功率半导体中的局部加热引起热引燃,则封装引燃,这继而引燃在其上安装该封装的PCB。燃烧PCB然后可以使汽车着火。 
检测热过载条件的开始是挑战性的,因为热过载的开始并不是必要地伴随着可容易地检测的高电流条件。如果在特定器件内的局部加热由在器件半导体材料的小区域中的电流拥挤引起,则可以不带明显电流地在器件内实现高温。如果器件在使得器件不可控的短路条件中失效,则控制或者停止热过载条件还可能是困难的。某些系统通过将可回流热保护器件(RTP)与功率半导体器件的栅极串联耦合而已经解决了这个问题,这被设计成当RTP器件的温度超过临界温度时创建开路。 
发明内容
根据一个实施例,一种半导体封装包括:被配置为被安装在电路板上的第一表面;和可热膨胀材料的区域,该可热膨胀材料的区域被配置为当可热膨胀材料的温度超过第一温度时远离电路板地推动半导体封装的第一表面。 
在以下的附图和说明中阐述了本发明的一个或者多个实施例的细节。根据说明和附图并且根据权利要求,本发明的其它特征、目的和优点将是明显的。 
附图说明
在以下的附图和说明中阐述了本发明的一个或者多个实施例的细节。根据说明和附图并且根据权利要求,本发明的其它特征、目的和优点将是明显的。在图中,贯穿各个视图,相同的附图标记一般地标注为了简洁起见而一般地将不被重复描述的相同的构件。为了更加完整地理解本发明,现在参考与附图相结合进行的以下说明,其中: 
图1a-1b示意实例汽车电池开关系统;
图2a-b示意实施例封装的截面;
图3a-d示意实施例TO 263-7封装;
图4a-b示意实施例多层条;
图5a-5e示意进一步的实施例封装;
图6a-c示意根据可替代实施例的封装;
图7a-c示意根据进一步的实施例的封装;
图8a-d示意根据另一个进一步的实施例的封装;
图9a-d示意根据进一步的实施例的封装;并且
图10示意根据可替代实施例的各种双金属条。
具体实施方式
以下详细地讨论了目前优选的实施例的实现和使用。然而,应该理解,本发明提供能够在各种各样的具体背景中体现的很多可应用的创造性概念。所讨论的具体实施例仅仅示意了用于实现和使用本发明的具体方式,而非限制本发明的范围。 
将关于在具体背景(即用于在功率半导体器件内带有失效开放机构的电子封装的系统和方法)中的示例性实施例描述本发明。实施例系统和方法还可以被应用于倾向于热过载的其它类型的电子构件。 
图1a使用汽车电池开关系统100作为实例示意了在功率半导体器件中的过热的问题。汽车电池开关系统100经由熔丝102和功率晶体管106从电池104向负载电阻110供应电力。控制集成电路108控制功率晶体管106的栅极。在正常操作条件下,一旦驾驶员激活点火开关,控制集成电路108便可以激活功率晶体管106。当功率晶体管106被打开时,电流从电池106通过负载电阻110流动。一种典型的汽车系统可以具有控制流向汽车的各种系统的电力的大约十二个功率晶体管开关。例如,系统诸如刮水器电动机、内部照明、汽车音频系统和其它系统可以每一个均具有向该具体系统供应电力的专用开关。 
在正常操作期间,可以作为n沟道MOSFET实现的功率晶体管106具有低漏极-源极电阻。功率晶体管106可以在各种各样的电压和频率下操作,并且可以甚至在功率晶体管的封装内具有另外的电路,该另外的电路在正常操作条件期间提供静电放电(ESD)保护和高温保护。然而,在用于功率晶体管106的寿命终止情形中,可能发生介质击穿或者金属化短路,从而导致功率晶体管106被置于低欧姆状态中。在某些情况中,引起源极-漏极短路,从而使得不能经由它的栅极端子控制功率晶体管106,导致在局部热斑中的电阻性加热,这可以引起封装、PCB或者在其中置放PCB和封装的系统的热引燃。 
因为在器件内的局部热斑内产生热量,所以功率晶体管106的热引燃可以导致低电流失效条件。换言之,高温可能由小于熔丝102的跳变点的电流引起。如果功率晶体管开关106在低欧姆条件中失效,则严重的电过载可以引燃器件。 
在本发明的一个实施例中,通过使用可热膨胀材料或者可热变形材料以由于高的热条件在功率晶体管或者其它构件的端子和电路板之间创建开路而避免了热引燃。例如,在一个实施例中,使用由具有不同的热膨胀系数(CTE)的两种相异的金属制成的双金属条在源极插脚处提升封装构件,这导致开路。在低欧姆状态中,芯片加热封装并且增加引线的温度。当焊料材料由于温度增加而处于熔融状态中时,在封装下面的双金属条或者其它可热变形材料翘曲,并且将封装提升到电路板上方,从而导致解焊的引线接头。在实施例中,可热变形材料在优选地高于焊料的熔点的特定温度处翘曲。在一个实施例中,当构件达到它的260℃的温度时形成开路。可替代地,根据具体实施例及其规格,可以使用其它温度。 
在一个实施例中,通过从印刷电路板物理地移位集成电路(IC)封装例如表面安装IC封装以便断开在IC封装和印刷电路板之间的电气路径而终止短路条件。在某些实施例中,移位在高于被用于将封装焊接到印刷电路板的焊料的熔化温度的温度下发生。在某些实施例中,焊料熔化温度可以例如处于或者高于280℃。在某些实施例中,可以通过使用作为对热影响的响应而改变它的形状的热敏材料以机械方式影响封装移位。这种热敏材料可以是恒温金属双金属(或者多层金属)弹簧。在本发明的某些实施例中,这个形状变化受所使用的材料的类型、所使用的材料的热膨胀系数及其几何形状影响。 
在某些实施例中,热敏材料可以是电路封装的一体部分,或者可联结到电路封装或者可与电路封装拆离的单独构件。热敏材料的位置可以位于多个不同的位置中。例如,热敏材料可以位于电路构件的顶部上、电路构件的侧面上、在电路封装下面和/或任何其它可以影响预期物理移位的位置。在本发明的某些实施例中,热敏材料的变形被配置为是不可逆的动作以防止如果温度降至低于热触发温度则热敏材料返回至它的初始位置。在某些实施例中,可以在构件中使用锁定机构和/或弹簧以防止器件采取它的初始位置。 
图1b是示出其中实施例可热膨胀材料能够被用于切断被封装电路121的电连接性的各种位置的实施例系统120的图。这里,被封装电路121具有被置放在传导基板122上的MOSFET芯片124。控制集成电路126被置放在MOSFET芯片124上。MOSFET 124的漏极被电连接到传导基板122,并且MOSFET芯片124的源极经由接合线140和插脚138而被耦合到电路板120。控制芯片126具有被耦合到MOSFET芯片124的栅极的接合线137。 
在一个实施例中,可以在点130处或者在点132处切断到电池104的连接。在进一步的实施例中,可以在点136处切断在板120和10 138之间的连接。在进一步的实施例中,可以自身在点134处切断到插脚138的连接。应该理解,在图1b中示意的实施例只是一个实例实施例。在本发明的可替代实施例中,该系统的其它部分可以被配置为提供其它的电断开点。 
图2a示意在正常操作条件下实施例封装200的截面。封装200具有使用管芯联结216在引线框架214上安装的集成电路212。芯片被与联结到插脚206的焊线204接合。密封材料202包围集成电路212、引线框架214、焊线204和插脚206。在一个实施例中,集成电路212可以是功率晶体管诸如功率MOSFET晶体管。在某些实施例中,集成电路212可以是垂直功率MOSFET器件诸如具有被耦合到集成电路212的后侧的漏极的横向扩散金属氧化物半导体(LDMOS)器件。在这种实施例中,通过引线框架214到在板210上的导电线路制成漏极连接。管芯联结216可以是使用但是不限于使用高铅或者无铅成分的软焊料、扩散焊接和环氧树脂管芯联结膏的传导热管芯联结。密封材料212可以是密封剂诸如但是不限于环氧树脂模制化合物。应该理解,被用于集成电路212的集成电路的类型、管芯联结216和密封材料212只是代表很多可能的实施例的一个实例。在本发明的可替代实施例中,可以使用其它集成电路类型、管芯联结材料和密封材料。 
在一个实施例中,可热膨胀和/或可热变形材料208被置放在封装200电路板210的空腔内。在图2a中,为了示意的意图,可热变形材料208被表示成压缩弹簧。可以使用双金属条、热敏聚合物或者其它可热膨胀和/或可热变形材料实现可热变形材料208。 
在一个实施例中,在高温短路条件下,集成电路212加热封装200并且激活可热变形材料208。当这发生时,如在图2b中所示意地,可热变形材料208将封装200推离板210。在一个实施例中,如上所述,可热变形材料208被配置为在大于大致260℃时变形。在某些实施例中,材料208膨胀或者变形所处的温度高于被用于将插脚206耦合到电路板208的焊料的熔点。应该理解,在可替代实施例中,可变形材料208可以被配置为在大于或者小于260℃的温度下变形,并且可以根据具体实施例及其规格而改变。 
图3a-d示意实施例TO 263-7封装,诸如被用于容纳功率晶体管的封装。图3a示意具有金属基板/引线框架306、插脚304和密封剂302的实施例封装300的顶视图。图3b示意侧视图,并且图3c和3d示意底视图。在图3c中,封装300被示为具有在密封剂302内置放的空腔308。图3d示意被置放在空腔308内的双金属条310。应该理解,在本发明的可替代实施例中,可以使用除了如在以下描述地使用空腔308之外的其它安装方法在封装300内安装和/或安设双金属条310。应该进一步理解,空腔308的形状可以根据具体应用及其规格而不同。 
图4a示意处于冷条件402和热条件408这两种条件中的双金属条的侧视图。双金属条具有附着到第二层406的第一层404。在一个实施例中,第一层404具有比第二层406更大的线性膨胀系数。在一个实施例中,当双金属条402是冷的时,这个双金属条是平面的。然而,当该条加热时,该条沿着具有更小线性膨胀系数的第二层406的方向弯曲。在某些实施例中,双金属条的一端被固定在空腔208内。可替代地,例如在以下描述的进一步的实施例中,双金属条可以被以不同的方式固定。在某些实施例中,具有更大线性膨胀系数的层404可以是铜层,而具有更小线性膨胀系数的层406可以是铁层。可替代地,层404和406可以例如包括在层404上的Ni、Fe-Ni-Mn或者Fe-Ni-Cr和在层406上的Fe-Ni。在某些实施例中,这些材料被配置为在小于400℃(例如在大约280℃和大约350℃之间)的温度下变形。根据具体应用及其规格,可以使用对相同和不同的温度范围敏感的金属的其它组合。 
在一个实施例中,材料的厚度和类型被选择为影响在特定温度下的变形。在一个实施例中,通过在可热膨胀材料上使用的材料的组合来设定变形温度。在某些实施例中,可以使用在特定温度下解锁的锁定机构以当材料达到触发温度时促使更快的膨胀。在某些实施例中,这个锁定机构可以是与特定构件的设计成一体的。 
图4b示意实施例多层金属条的热状态430和八个冷状态432。在一个实施例中,层412具有比层414更大的线性膨胀系数。另外,多层金属条还具有倾向于在低温下以及在高温下变形的层416。在利用锁定机构的实施例中,使用倾向于在低温下变形的金属层能够被用于提供不可逆的动作以防止如果温度下降至低于触发温度则电子构件返回至它的初始位置。在本发明的某些实施例中,这个不可逆的动作防止一旦构件已经冷却便再次发生短路。 
图5a-d示意根据本发明的另一个实施例的构件500。构件500包括被置放于在构件500的下侧处的空腔内的多层热敏金属条502。在某些实施例中,弹簧类型层506被置放在多层热敏金属条502的至少一个部分之上。夹子504在它被热触发之前保持金属条502处于紧凑环。当金属条502达到它的触发温度时,夹子504释放金属条502的端部,由此使得构件502从在其上安装构件500的电路板向上卡扣(snap)。使用弹簧类型层506和/或夹子504的实施例采用防止构件500实现它的初始物理位置的热不可逆过程,由此确保在构件冷却之后不重建短路。 
图5d和5e示意在热事件之前的安设/运行状态500a中和在热事件随后的松开(tripped)状态500b中被置放在电路板530上的构件500。 
图6a-c示意根据进一步的实施例的构件600。构件600包括从构件的表面延伸并且与插脚610并排向下朝向构件600的基部成环的多层热敏金属条602。在某些实施例中,弹簧类型层606被置放在多层热敏金属条602的至少一个部分之上以提供对达到触发温度的热不可逆响应。在一个实施例中,当多层热敏金属条602达到它的触发温度时,该条膨胀并且从在其上置放构件600的电路板的表面上推插脚610。 
图6c示意在热事件之前的安设/运行状态600a中和在热事件随后的松开状态600b中被置放在电路板630上的构件600。 
图7a-c示意根据另一个实施例的构件700。构件700包括从构件的表面延伸并且与插脚710并排朝向构件700的基部盘旋的卷绕多层热敏金属条702。在一个实施例中,当多层热敏金属条702达到它的触发温度时,螺旋形条膨胀并且从在其上置放构件700的电路板的表面上推插脚710。在某些实施例中,条702的卷绕结构产生比非卷绕的条更大的偏转。 
图7c示意在热事件之前的安设/运行状态700a中和在热事件随后的松开状态700b中被置放在电路板730上的构件700。 
图8a-e示意根据另一个实施例的构件800。构件800包括被置放在构件800的顶部上的热敏材料802。突出杆部810被联结到热敏材料802并且被置放在构件800邻近于插脚810的一侧上。当热敏材料802达到它的触发温度时,材料收缩并且朝向在其上置放构件800的电路板推动杆部812。在某些实施例中,夹子804被置放成紧靠热敏材料802以便保持材料802靠近构件800的顶部。 
图8d和8e示意在热事件之前的安设/运行状态800a中和在热事件随后的松开状态800b中被置放在电路板830上的构件800。 
图9a-d示意根据本发明的进一步的实施例的构件900。构件900包括被置放在构件900的顶部上并且被耦合到突出杆部910的热敏材料902。插脚短柱916经由传导电桥914而被电耦合到插脚918。在一个实施例中,插脚短柱916被电连接到在封装900内的电路并且插脚918被断开。插脚910可以是正常连接的封装插脚。在某些实施例中,可以从使用热敏焊料被联结到插脚短柱916和插脚918的焊料材料或者铜材料构造电桥914。图9d示意插脚短柱916电桥914和插脚918的一种可能的实施例实现。可替代地,可以使用其它材料和配置。 
在正常操作期间,在构件900达到热临界温度之前,插脚918经由电桥914和插脚短柱916而被耦合到在封装900内部的电路。当封装900达到热阈值温度时。热材料902收缩并且针对电桥914上推杆912。因为构件914是热的,所以用于将插脚910和插脚918附着到电路板的焊料以及用于将电桥914附着到插脚短柱916和插脚918的焊料被液化。杆912克服焊料的表面张力/润湿力并且将电桥914推离插脚短柱916和插脚918,由此从封装900内部的电路断开插脚918。 
在本发明的可替代实施例中,可以替代双金属条地使用其它类型的热变形或者可扩张材料,例如可热膨胀聚合物。进而,如在图10中所示,还可以使用其它形状的可热变形和/或膨胀材料。 
根据一个实施例,半导体封装包括:被配置为被安装在电路板上的第一表面,和被配置为当可热膨胀材料的温度超过第一温度时将半导体封装的第一表面推离电路板的可热膨胀材料的区域。在一个实施例中,这个第一温度可以是大约260℃。可替代地,可以使用大于或者小于这个温度的其它温度。在一个实施例中,可热膨胀材料的区域包括多层金属条。 
在本发明的某些实施例中,多层金属条包括具有第一线性膨胀系数的内表面和具有第二线性膨胀系数的外表面。在一个实施例中,内表面与外表面相对,内表面面对半导体封装的第一表面地被置放在半导体封装上,并且第一线性膨胀系数大于第二线性膨胀系数。内表面可以包括铜和外表面。在一个实施例中,半导体封装还可以包括被置放在多层金属条的至少一个部分上的弹簧层。 
在一个实施例中,可热膨胀材料的区域被置放在第一表面内。在某些实施例中,半导体封装包括被置放在第一表面内的空腔,并且可热膨胀材料被置放在空腔内。半导体封装可以进一步包括多个表面安装引线,从而空腔被邻近于该多个表面安装引线地置放。 
在某些实施例中,可热膨胀材料包括可热膨胀聚合物。半导体封装可以进一步包括半导体功率晶体管器件。进而,半导体封装还可以包括仅仅在半导体封装的第一边缘上置放的单行表面安装触点,并且可热膨胀材料的区域被邻近于该单行表面安装触点地置放。可热膨胀材料可以被配置为当可热膨胀材料超过第一温度时将表面安装触点推离电路板的平面。在某些实施例中,可热膨胀材料可以包括被置放于在半导体封装的第一表面中置放的通道内的双金属条。在某些实施例中,双金属条包括第一端和第二端,使得第一端被固定地联结到通道的第一端。可热膨胀材料可以被配置为当可热膨胀材料超过第一温度时经历不可逆的物理变形。在某些实施例中,可热膨胀材料包括被配置为当可热膨胀材料超过第一温度时被释放的夹子。 
根据进一步的实施例,该电子系统包括电路板和被置放在电路板上的半导体封装。该半导体封装可以包括第一表面和被置放在第一表面内的可热膨胀材料的区域。可热膨胀材料的区域可以被配置为当可热膨胀材料的温度超过第一温度时将半导体封装的第一表面推离电路板。在一个实施例中,这个第一温度可以是大约260℃。可替代地,可以使用大于或者小于这个温度的其它温度。 
在某些实施例中,可热膨胀材料的区域是包括内表面和外表面的双金属条。在一个实施例中,内表面具有第一线性膨胀系数并且外表面具有第二线性膨胀系数。内表面可以与外表面相对并且内表面可以面对半导体封装的第一表面地被置放在半导体封装上。进而,第一线性膨胀系数大于第二线性膨胀系数。 
在一个实施例中,半导体封装包括被配置为被耦合到电路板的一行触点并且可热膨胀材料的区域邻近于该行触点地被置放在空腔中。可热膨胀材料可以被配置为当可热膨胀材料超过第一温度时将该行触点推离电路板的平面。在某些实施例中,半导体封装可以包括功率半导体器件。 
根据本发明的另一个实施例,一种为半导体器件提供热保护的方法包括提供在电路板上安装的半导体封装。该半导体封装包括触点,该触点在邻近于触点地被耦合到半导体封装的可热变形材料中被耦合到电路板。该方法还包括当可热变形材料超过第一温度时经由可热变形材料的热膨胀将触点从电路板解耦。在一个实施例中,这个第一温度可以是大约260℃。可替代地,可以使用大于或者小于这个温度的其它温度。 
在一个实施例中,将触点解耦包括使双金属条变形从而当可热变形材料超过第一温度时双金属条将可安装表面推离电路板。在某些实施例中,将触点从电路板解耦包括熔化将触点耦合到电路板的焊料以允许双金属条将可安装表面推离电路板。在一个实施例中,焊料具有小于第一温度的熔点。 
某些实施例的优点包括如下能力:具有被集成到功率晶体管的封装中的高温跳变点而无需另外的构件,由此降低消费者和/或制造商的构件成本以及使得更多的板空间可用于其它构件。某些实施例的进一步的优点包括在其中跳变机构不需要任何另外的测试的实施例中降低测试成本。某些实施例的进一步的优点包括更低的开关电阻,因为无任何另外的串联电阻被添加到电流路径。某些实施例进一步适合于快速的开关应用。 
虽然已经主要地结合具体示例性实施例示出并且描述了本发明,但是本领域技术人员应该理解,能够在不偏离如由以下权利要求限定的本发明的实质和范围的情况下进行在其配置和细节方面的各种改变。本发明的范围因此由所附权利要求确定,并且意图在于落入权利要求的含义范围和等价范围内的所有更改均被权利要求所涵盖。 

Claims (24)

1.一种半导体封装,包括:
被配置为被安装在电路板上的第一表面;和
可热膨胀材料的区域,被配置为当所述可热膨胀材料的温度超过第一温度时将所述半导体封装的所述第一表面推离所述电路板。
2.根据权利要求1所述的半导体封装,其中所述可热膨胀材料的区域包括多层金属条。
3.根据权利要求2所述的半导体封装,其中所述多层金属条包括:
具有第一线性膨胀系数的内表面;和
具有第二线性膨胀系数的外表面,其中
    所述内表面与所述外表面相对,
    所述内表面面对所述半导体封装的所述第一表面地被置放在所述半导体封装上,并且
    所述第一线性膨胀系数大于所述第二线性膨胀系数。
4.根据权利要求3所述的半导体封装,其中所述内表面包括铜并且所述外表面包括铁。
5.根据权利要求3所述的半导体封装,进一步包括被置放在所述多层金属条的至少一个部分上的弹簧层。
6.根据权利要求1所述的半导体封装,其中所述可热膨胀材料的区域被置放在所述第一表面内。
7.根据权利要求6所述的半导体封装,其中所述半导体封装包括被置放在所述第一表面内的空腔,并且所述可热膨胀材料被置放在所述空腔内。
8.根据权利要求7所述的半导体封装,其中:
所述半导体封装进一步包括多个表面安装引线;并且
所述空腔被邻近于所述多个表面安装引线地置放。
9.根据权利要求1所述的半导体封装,其中所述可热膨胀材料包括可热膨胀聚合物。
10.根据权利要求1所述的半导体封装,其中所述半导体封装进一步包括半导体功率晶体管器件。
11.根据权利要求1所述的半导体封装,其中所述半导体封装进一步包括:
仅仅在所述半导体封装的第一边缘上置放的单行表面安装触点;并且
所述可热膨胀材料的区域被邻近于所述单行表面安装触点地置放,其中所述可热膨胀材料被配置为当所述可热膨胀材料超过所述第一温度时将所述表面安装触点推离所述电路板的平面。
12.根据权利要求11所述的半导体封装,其中所述可热膨胀材料包括被置放于在所述半导体封装的所述第一表面中置放的通道内的双金属条。
13.根据权利要求12所述的半导体封装,其中所述双金属条包括第一端和第二端,所述第一端被固定地联结到所述通道的第一端。
14.根据权利要求1所述的半导体封装,其中所述可热膨胀材料被配置为当所述可热膨胀材料超过所述第一温度时经历不可逆的物理变形。
15.根据权利要求1所述的半导体封装,其中所述可热膨胀材料包括被配置为当所述可热膨胀材料超过所述第一温度时被释放的夹子。
16.一种电子系统,包括:
电路板;和
被置放在所述电路板上的半导体封装,所述半导体封装包括
    第一表面,和
    被置放在所述第一表面内的可热膨胀材料的区域,所述可热膨胀材料的区域被配置为当所述可热膨胀材料的温度超过第一温度时将所述半导体封装的第一表面推离所述电路板。
17.根据权利要求16所述的电子系统,其中所述可热膨胀材料的区域是双金属条,所述双金属条包括:
具有第一线性膨胀系数的内表面;和
具有第二线性膨胀系数的外表面,其中
    所述内表面与所述外表面相对,
    所述内表面面对所述半导体封装的所述第一表面地被置放在所述半导体封装上,并且
    所述第一线性膨胀系数大于所述第二线性膨胀系数。
18.根据权利要求16所述的电子系统,其中:
所述半导体封装包括被配置为被耦合到所述电路板的一行触点;并且
所述可热膨胀材料的区域邻近于所述一行触点地被置放在空腔中。
19.根据权利要求18所述的电子系统,其中所述可热膨胀材料被配置为当所述可热膨胀材料超过所述第一温度时将所述一行触点推离所述电路板的平面。
20.根据权利要求16所述的电子系统,其中所述半导体封装包括功率半导体器件。
21.一种为半导体器件提供热保护的方法,所述方法包括:
提供在电路板上安装的半导体封装,所述半导体封装包括被耦合到所述电路板的触点,和邻近于所述触点地被耦合到所述半导体封装的可热变形材料;和
当所述可热变形材料超过第一温度时经由所述可热变形材料的热膨胀将所述触点从所述电路板解耦。
22.根据权利要求21所述的方法,其中将所述触点解耦包括当所述可热变形材料超过所述第一温度时使双金属条变形从而所述双金属条将可安装表面推离所述电路板。
23.根据权利要求22所述的方法,其中将所述触点从所述电路板解耦包括熔化将所述触点耦合到所述电路板的焊料以允许所述双金属条将所述可安装表面推离所述电路板,其中所述焊料具有小于所述第一温度的熔点。
24.根据权利要求21所述的方法,其中所述第一温度是大约260℃。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103872001A (zh) * 2014-02-26 2014-06-18 江西创成半导体有限公司 一种主动式芯片封装方式
CN104078430A (zh) * 2012-11-15 2014-10-01 英飞凌科技股份有限公司 用于具有故障时打开机构的电子封装的系统和方法
CN110520987A (zh) * 2017-03-28 2019-11-29 罗姆股份有限公司 半导体器件和半导体器件的制造方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009053145A1 (de) 2009-11-05 2011-05-12 Phoenix Contact Gmbh & Co. Kg Überspannungsschutzelement
DE102010036909B3 (de) * 2010-08-06 2012-02-16 Phoenix Contact Gmbh & Co. Kg Thermische Überlastschutzvorrichtung
ITTO20120854A1 (it) * 2012-09-28 2014-03-29 Stmicroelectronics Malta Ltd Contenitore a montaggio superficiale perfezionato per un dispositivo integrato a semiconduttori, relativo assemblaggio e procedimento di fabbricazione
CN104867900B (zh) * 2014-02-26 2017-08-15 江西创成微电子有限公司 一种芯片封装方法
DE102014008021B4 (de) 2014-05-27 2021-06-10 Hkr Automotive Gmbh Schaltungsanordnung zum thermischen Schutz eines Leistungshalbleiters
DE102014111772B4 (de) * 2014-08-18 2016-03-24 Borgwarner Ludwigsburg Gmbh Sicherung für einen elektrischen Stromkreis sowie Leiterplatte mit einer Sicherung
KR20160083408A (ko) 2014-12-31 2016-07-12 삼성전자주식회사 퓨즈 패키지 및 이를 이용한 발광소자 모듈
US9620764B2 (en) 2015-01-05 2017-04-11 Johnson Controls Technology Company Battery module cooling fins and footings system and method
DE102016104424B4 (de) * 2016-03-10 2023-12-07 Borgwarner Ludwigsburg Gmbh Bestückte Leiterplatte und Verfahren zur Bestückung einer Leiterplatte
EP3817518A1 (en) 2019-10-31 2021-05-05 Aptiv Technologies Limited A method for manufacturing a circuit board, and associated circuit board
US11935844B2 (en) * 2020-12-31 2024-03-19 Texas Instruments Incorporated Semiconductor device and method of the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5039844A (en) * 1986-03-31 1991-08-13 Nippon Mektron, Ltd. PTC devices and their preparation
US5763929A (en) * 1994-03-18 1998-06-09 Kabushiki Kaisha Tokai Rika Denki Seisakusho Transistor package having a series connected thermistor for protection from thermal destruction
US6504467B1 (en) * 1999-07-31 2003-01-07 Mannesmann Vdo Ag Switch integral in a semiconductor element
CN1675764A (zh) * 2002-08-16 2005-09-28 Abb瑞士有限公司 短路失效模式预制件的功能涂层
US20080180871A1 (en) * 2007-01-25 2008-07-31 Alpha & Omega Semiconductor, Ltd Structure and method for self protection of power device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2550886B1 (fr) 1983-08-17 1986-10-24 Radiotechnique Compelec Procede de realisation de transistors de puissance incluant des moyens de protection contre les surcharges et dispositifs ainsi obtenus
US6100745A (en) * 1998-08-10 2000-08-08 Johnson Controls Technology Company Combination positive temperature coefficient resistor and metal-oxide semiconductor field-effect transistor devices
US6255141B1 (en) 1999-09-07 2001-07-03 National Semiconductor Corporation Method of packaging fuses
JP3506233B2 (ja) * 2000-06-28 2004-03-15 シャープ株式会社 半導体装置及びその製造方法
KR100443504B1 (ko) * 2001-06-12 2004-08-09 주식회사 하이닉스반도체 볼 그리드 어레이 패키지 구조 및 그 제조방법
DE102007014339A1 (de) * 2007-03-26 2008-10-02 Robert Bosch Gmbh Thermosicherung für den Einsatz in elektrischen Modulen
JP2009194203A (ja) * 2008-02-15 2009-08-27 Fujitsu Ltd 電子機器
US8581686B2 (en) 2009-03-24 2013-11-12 Tyco Electronics Corporation Electrically activated surface mount thermal fuse
EP2315285B1 (en) * 2009-10-22 2014-06-04 Nxp B.V. Apparatus for regulating the temperature of a light emitting diode

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5039844A (en) * 1986-03-31 1991-08-13 Nippon Mektron, Ltd. PTC devices and their preparation
US5763929A (en) * 1994-03-18 1998-06-09 Kabushiki Kaisha Tokai Rika Denki Seisakusho Transistor package having a series connected thermistor for protection from thermal destruction
US6504467B1 (en) * 1999-07-31 2003-01-07 Mannesmann Vdo Ag Switch integral in a semiconductor element
CN1675764A (zh) * 2002-08-16 2005-09-28 Abb瑞士有限公司 短路失效模式预制件的功能涂层
US20080180871A1 (en) * 2007-01-25 2008-07-31 Alpha & Omega Semiconductor, Ltd Structure and method for self protection of power device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104078430A (zh) * 2012-11-15 2014-10-01 英飞凌科技股份有限公司 用于具有故障时打开机构的电子封装的系统和方法
CN104078430B (zh) * 2012-11-15 2017-07-07 英飞凌科技股份有限公司 用于具有故障时打开机构的电子封装的系统和方法
CN103872001A (zh) * 2014-02-26 2014-06-18 江西创成半导体有限公司 一种主动式芯片封装方式
CN103872001B (zh) * 2014-02-26 2017-04-19 深圳市创成微电子有限公司 一种主动式芯片封装方式
CN110520987A (zh) * 2017-03-28 2019-11-29 罗姆股份有限公司 半导体器件和半导体器件的制造方法
CN110520987B (zh) * 2017-03-28 2023-10-27 罗姆股份有限公司 半导体器件和半导体器件的制造方法

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