CN103219242A - 调节多栅结构器件阈值电压的方法 - Google Patents

调节多栅结构器件阈值电压的方法 Download PDF

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CN103219242A
CN103219242A CN201310103272XA CN201310103272A CN103219242A CN 103219242 A CN103219242 A CN 103219242A CN 201310103272X A CN201310103272X A CN 201310103272XA CN 201310103272 A CN201310103272 A CN 201310103272A CN 103219242 A CN103219242 A CN 103219242A
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CN103219242B (zh
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黎明
樊捷闻
李佳
许晓燕
黄如
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Abstract

本发明公布了一种调节多栅结构器件阈值电压的方法，其特征是，制备多栅结构器件，使之形成表面高掺杂内部低掺杂的沟道杂质分布，利用杂质掺杂在调节阈值电压的同时，尽量减小库伦杂质散射对于载流子的影响，使得载流子的迁移率维持在较高水平。首先，该方案能够使得多栅器件获得较大范围的多阈值电压，方便IC设计人员在电路设计过程中对于器件的不同需求。其次，在引入杂质掺杂以调整阈值电压过程中，尽量减小了库伦杂质散射对于沟道载流子的影响，使得载流子的迁移率维持在较高水平，保证器件拥有较高的驱动电流。最后，该方案可以通过与传统CMOS兼容的工艺方法实现，具备大规模生产的潜力。

Description

调节多栅结构器件阈值电压的方法
技术领域
本发明涉及一种调节多栅结构器件阈值电压的方法，属于超大规模集成电路制造技术领域。
背景技术
当今半导体制造业在摩尔定律的指导下迅速发展，不断提高集成电路的性能和集成密度，同时需要尽可能的减小功耗。制备高性能，低功耗的超短沟器件是未来半导体制造业的焦点。当进入到22纳米技术节点以后，传统平面场效应晶体管由于日益严重的短沟道效应导致泄漏电流不断增加，不能满足半导体制造的发展。为了克服上述问题，多栅结构器件由于其优秀的栅控性能和输运特性，在克服短沟道效应的同时提高单位面积的驱动电流密度，因而逐渐引起广泛的关注。
虽然由于多栅结构器件本身的特殊几何结构，使得其拥有出色的栅控性能，但是这会使得它的体效应因子下降。因此，相比于传统平面器件，多栅结构器件更难实现多阈值器件。在同一种工艺条件下实现多阈值器件的传统方法是进行沟道掺杂，多栅结构器件需要更高的沟道掺杂浓度才能实现阈值电压的变化。而由于存在库伦杂质散射，沟道掺杂浓度提高会严重影响器件中载流子的迁移率，最终使得驱动电流大幅下降。这是多栅结构器件在大规模集成电路产品中应用的主要困难和挑战之一。
发明内容
本发明的目的在于针对多栅结构器件更难实现多阈值的问题，提供了一种调节多栅结构器件阈值电压的方法。该方案在多栅器件获得较大范围多阈值电压的同时，又减小了库伦杂质散射对于沟道载流子的影响，使得载流子的迁移率维持在较高水平，保证器件拥有较高的驱动电流。而且，该方案可以通过与传统CMOS兼容的工艺方法实现。
本发明的技术方案如下：
一种调节多栅结构器件阈值电压的方法，其特征是，制备多栅结构器件，使之形成表面高掺杂内部低掺杂的沟道杂质分布，以SOI衬底上的三栅结构器件为例，如图1所示（图2为采用本发明方案的三栅器件沟道杂质浓度分布示意图）：
其主要思路是利用杂质掺杂在调节阈值电压的同时，尽量减小库伦杂质散射对于载流子的影响，使得载流子的迁移率维持在较高水平：
对于小尺寸（22nm技术节点以后）的多栅结构器件，由于全耗尽和体反型的特征，使得载流子分布与传统平面器件不同。全耗尽多栅结构器件载流子在沟道中的分布，集中在体区，而与沟道表面具有一定距离。
将载流子浓度较低的区域（沟道表面处）进行高掺杂，将载流子浓度较高的区域（沟道体区）进行低掺杂。这使得掺杂杂质调节阈值电压的同时，尽可能地减小了对载流子的杂质库伦散射。
与传统沟道整体进行杂质掺杂的方案相比，在改变相同阈值电压的条件下，该方案的载流子平均迁移率较高，从而保证了多栅器件拥有更高的驱动电流。同时，两个方案对于短沟道效应的控制能力相当，器件模拟结果如图3-图6所示。
制备表面高掺杂内部低掺杂沟道的工艺方法如下：
其主要思路是通过类似传统CMOS工艺兼容的超浅结工艺，来制备三维结构上杂质分布均匀的超浅高低结沟道。
1)杂质掺杂，形成1nm的超浅杂质分布。该步骤可以通过等离子体杂质掺杂技术、硅外延原位掺杂技术或者单分子层掺杂技术实现。
2)钝化层淀积，形成一定厚度（20nm）的钝化层，使得在之后的退火工艺中，尽量减小掺杂杂质的损失。该步骤可以通过常见的各种淀积方式形成，如原子层淀积、低压化学气相淀积等。
3)退火，形成1～2nm的超浅结。该步骤可以通过Spike退火、Flash退火或激光退火等先进退火技术实现，在保证激活杂质浓度的条件下，尽量减小杂质的扩散。
本发明具有如下技术效果：
首先，该方案能够使得多栅器件获得较大范围的多阈值电压，方便IC设计人员在电路设计过程中对于器件的不同需求。其次，在引入杂质掺杂以调整阈值电压过程中，尽量减小了库伦杂质散射对于沟道载流子的影响，使得载流子的迁移率维持在较高水平，保证器件拥有较高的驱动电流。最后，该方案可以通过与传统CMOS兼容的工艺方法实现，具备大规模生产的潜力。
附图说明
图1为SOI衬底上的三栅器件结构图；
图2为采用本发明方案的三栅器件沟道杂质浓度分布示意图；
图3为采用传统沟道杂质分布在不同沟道长度下杂质浓度对阈值电压的调整；
图4为采用本发明方案的沟道杂质分布在不同沟道长度下杂质浓度对阈值电压的调整图；
图5为两种方案的沟道杂质分布，不同阈值电压下的驱动电流情况；
图6为两种方案的沟道杂质分布，驱动电流和泄漏电流的情况。
具体实施方式
下面结合具体实施例对本发明进行详细说明，具体给出一实现本发明提出的多栅结构器件多阈值电压的工艺方案，并以三栅结构器件为例（显而易见地，本发明所述方案完全对其他多栅结构适用），但不以任何方式限制本发明的范围。
根据下列步骤制备Fin条宽度约为10纳米，高度为30纳米，沟道长度约为25纳米的n型三栅场效应晶体管：
1)通过等离子体杂质掺杂技术，硅外延原位掺杂技术或者单分子层掺杂技术实现沟道表面高掺杂，掺杂剂量为1e15cm-2；
2)原子层淀积
Figure BDA00002977640600031
氧化硅；
3)沟道区杂质激活，激光退火，1100度，1纳秒；
4)HF溶液各项同性湿法腐蚀氧化硅；
上面描述的实施例并非用于限定本发明，任何本领域的技术人员，在不脱离本发明的精神和范围内，可做各种的更动和润饰，因此本发明的保护范围视权利要求范围所界定。

Claims (6)

1.一种调节多栅结构器件阈值电压的方法，其特征是，制备多栅结构器件，使之形成表面高掺杂内部低掺杂的沟道杂质分布：对于小尺寸的多栅结构器件，由于全耗尽和体反型的特征，使得载流子分布与传统平面器件不同，全耗尽多栅结构器件载流子在沟道中的分布，集中在体区，而与沟道表面具有一定距离；将载流子浓度较低的区域即沟道表面处进行高掺杂，将载流子浓度较高的区域即沟道体区进行低掺杂，这使得掺杂杂质调节阈值电压的同时，尽可能地减小了对载流子的杂质库伦散射。
2.如权利要求1所述的调节多栅结构器件阈值电压的方法，其特征是，所述多栅结构器件的制备方法为：
1)杂质掺杂，形成1nm的超浅杂质分布；
2)钝化层淀积，形成一定厚度的钝化层，使得在之后的退火工艺中，尽量减小掺杂杂质的损失；
3)退火，形成1～2nm的超浅结。
3.如权利要求2所述的调节多栅结构器件阈值电压的方法，其特征是，步骤1）通过等离子体杂质掺杂技术、硅外延原位掺杂技术或者单分子层掺杂技术实现。
4.如权利要求2所述的调节多栅结构器件阈值电压的方法，其特征是，步骤2）通原子层淀积、低压化学气相淀积方法实现。
5.如权利要求2所述的调节多栅结构器件阈值电压的方法，其特征是，步骤3）通过Spike退火、Flash退火或激光退火实现，在保证激活杂质浓度的条件下，尽量减小杂质的扩散。
6.如权利要求2所述的调节多栅结构器件阈值电压的方法，其特征是，步骤2）中所述钝化层的厚度为20nm。
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