CN103201825A - 应用确定波长的光通量处理衬底的工艺以及相应衬底 - Google Patents

应用确定波长的光通量处理衬底的工艺以及相应衬底 Download PDF

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Publication number
CN103201825A
CN103201825A CN2011800433924A CN201180043392A CN103201825A CN 103201825 A CN103201825 A CN 103201825A CN 2011800433924 A CN2011800433924 A CN 2011800433924A CN 201180043392 A CN201180043392 A CN 201180043392A CN 103201825 A CN103201825 A CN 103201825A
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CN
China
Prior art keywords
layer
ground floor
technology
substrate
embeding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011800433924A
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English (en)
Chinese (zh)
Inventor
M·布吕尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of CN103201825A publication Critical patent/CN103201825A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H10P54/50—Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving
    • H10P54/52—Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving by cleaving
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/11—Separation of active layers from substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Laser Beam Processing (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
CN2011800433924A 2010-09-10 2011-09-05 应用确定波长的光通量处理衬底的工艺以及相应衬底 Pending CN103201825A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1057211A FR2964788B1 (fr) 2010-09-10 2010-09-10 Procédé de traitement d'un substrat au moyen d'un flux lumineux de longueur d'onde déterminée, et substrat correspondant
FR1057211 2010-09-10
PCT/EP2011/065259 WO2012031998A1 (en) 2010-09-10 2011-09-05 Process for treating a substrate using a luminous flux of determined wavelength, and corresponding substrate

Publications (1)

Publication Number Publication Date
CN103201825A true CN103201825A (zh) 2013-07-10

Family

ID=43920828

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011800433924A Pending CN103201825A (zh) 2010-09-10 2011-09-05 应用确定波长的光通量处理衬底的工艺以及相应衬底

Country Status (7)

Country Link
US (2) US9190314B2 (https=)
EP (1) EP2614519B1 (https=)
JP (1) JP5952281B2 (https=)
KR (1) KR101918166B1 (https=)
CN (1) CN103201825A (https=)
FR (1) FR2964788B1 (https=)
WO (1) WO2012031998A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2964788B1 (fr) 2010-09-10 2015-05-15 Soitec Silicon On Insulator Procédé de traitement d'un substrat au moyen d'un flux lumineux de longueur d'onde déterminée, et substrat correspondant
FR2978600B1 (fr) 2011-07-25 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de fabrication de couche de materiau semi-conducteur

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR757986A (fr) 1932-07-04 1934-01-05 Thomson Houston Comp Francaise Perfectionnements aux tubes électroniques et à leurs circuits
US4234356A (en) * 1979-06-01 1980-11-18 Bell Telephone Laboratories, Incorporated Dual wavelength optical annealing of materials
US4456490A (en) * 1983-03-09 1984-06-26 Westinghouse Electric Corp. Laser annealing of MIS devices by back surface laser treatment
JP2008135436A (ja) * 2006-11-27 2008-06-12 Seiko Epson Corp 剥離方法、半導体デバイス及び電子機器
JP5286684B2 (ja) * 2007-03-28 2013-09-11 セイコーエプソン株式会社 薄膜層の剥離方法、薄膜デバイスの転写方法
FR2921752B1 (fr) * 2007-10-01 2009-11-13 Aplinov Procede de chauffage d'une plaque par un flux lumineux.
FR2938116B1 (fr) * 2008-11-04 2011-03-11 Aplinov Procede et dispositif de chauffage d'une couche d'une plaque par amorcage et flux lumineux.
FR2964788B1 (fr) 2010-09-10 2015-05-15 Soitec Silicon On Insulator Procédé de traitement d'un substrat au moyen d'un flux lumineux de longueur d'onde déterminée, et substrat correspondant

Also Published As

Publication number Publication date
KR101918166B1 (ko) 2018-11-13
US20160056247A1 (en) 2016-02-25
US20130154065A1 (en) 2013-06-20
US9190314B2 (en) 2015-11-17
EP2614519B1 (en) 2015-07-01
JP2013541197A (ja) 2013-11-07
US9564496B2 (en) 2017-02-07
JP5952281B2 (ja) 2016-07-13
FR2964788B1 (fr) 2015-05-15
FR2964788A1 (fr) 2012-03-16
WO2012031998A1 (en) 2012-03-15
KR20140019281A (ko) 2014-02-14
EP2614519A1 (en) 2013-07-17

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PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130710