CN103199014B - Method for thinning and polishing InP material - Google Patents

Method for thinning and polishing InP material Download PDF

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CN103199014B
CN103199014B CN201310068641.6A CN201310068641A CN103199014B CN 103199014 B CN103199014 B CN 103199014B CN 201310068641 A CN201310068641 A CN 201310068641A CN 103199014 B CN103199014 B CN 103199014B
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inp material
polishing
thinning
silicon chip
inp
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CN103199014A (en
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汪宁
苏永波
金智
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Abstract

The invention discloses a method for thinning and polishing an InP material, which comprises the following steps: manufacturing a silicon wafer grinding liner for thinning the InP material; thinning InP materials by using the silicon wafer grinding pad; carrying out chemical mechanical polishing on the InP material; cleaning the InP material subjected to the chemical mechanical polishing; and putting the cleaned InP material into an ICP etching machine for plasma polishing. The invention greatly improves the thinning effect, realizes the thinning and polishing of the substrate with no pollution, low damage, high efficiency and mirror surface effect, and solves the technical problem of the InPMMIC back-end.

Description

A kind of method that is thinning and polishing is carried out to InP material
Technical field
The present invention relates to InPMMIC preparing technical field, what particularly relate to a kind of improvement carries out method that is thinning and polishing to InP material.
Background technology
Along with new and high technology is constantly applied to military field, frequency microwave signal frequency is more and more higher, and frequency range is more and more wider, and the disposal ability of digit chip is more and more stronger, and modern war has progressed into information age and digital times.The fast development of electronic device makes the transmission rate of signal more and more faster; III-V relies on its excellent frequency characteristic, and its semiconductor device and relevant very high speed digital/Digital Analog Hybrid Circuits are becoming one of core component of the modernization defence equipments such as military communication, radar, guidance, space defense, high-speed intelligent weapon and electronic countermeasures.Particularly in Terahertz research field, the use of InP material is in the ascendant.
In numerous Group III-V compound semiconductor devices, InP material has unique advantage, this mainly has benefited from its excellent material behavior, such as very little between InGaAs and InP lattice mismatch, and very high electron saturation velocities etc., no matter so HEMT-structure or HBT structure, there are very excellent high frequency, high-power performance.But the physical property of InP material is very poor, very frangible, very little collision or vibration all can cause that wafer is cracked and all that has been achieved is spoiled, and therefore InP material volume manufacture processing just faces an a lot of technologic difficult problem.
For ultra-high frequency, powerful InPMMIC, its heat dissipation problem is difficult to good solution always, the solution of comparative maturity makes large-area heat radiating metal at the InP wafer substrate back side, front MMIC circuit and backside heat metal are passed through metallic communication, realizes effective release of heat.
Based on this solution, carry out thinning to InP wafer substrate, make it to reach very thin thickness, and thinning surface to realize mirror effect to meet the strongly adherent of back metal.But the physical property of InP fragility causes the technology difficulty of low reduced thickness and mirror effect polishing very large, and the thinning and glossing therefore improving the low thickness of low damage of InP material is significant.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is that providing a kind of carries out method that is thinning and polishing to InP material.
(2) technical scheme
For achieving the above object, the invention provides and a kind of method that is thinning and polishing be carried out to InP material, comprising: make and thinning silicon chip grinding liner is carried out to InP material; This silicon chip grinding liner is utilized to carry out thinning to InP material; Chemico-mechanical polishing is carried out to InP material; The InP material completing chemico-mechanical polishing is cleaned; And the InP material after cleaning is put into ICP etching machine and carried out plasma polishing.
In such scheme, described making carries out the step of thinning silicon chip grinding liner to InP material, comprising: carry out standard RCA clean technique to silicon chip; And use sputtering unit surface, silicon wafer polishing face after cleaning to adopt RF plasma sputtering Ti/Al 2o 3nano particle film layer structure, forms silicon chip grinding liner.
In such scheme, described step of silicon chip being carried out to standard RCA clean technique, comprising: clean silicon chip at 100 ~ 130 DEG C of temperature with SC-3 reagent: in SC-3 reagent, each composition volume ratio is H 2sO 4: H 2o 2: H 2o=1: 3: 20,10 minutes time; Clean silicon chip at 65 ~ 80 DEG C of temperature with SC-1 reagent, in SC-1 reagent, each composition volume ratio is NH 4oH: HO 2: H 2o=1: 1: 5,10 minutes time; Clean silicon chip at 20 ~ 25 DEG C of temperature with DHF, in DHF, each composition volume ratio is HF: H 2o=1: 10,10 minutes time; Clean silicon chip at 65 ~ 80 DEG C of temperature with SC-2 reagent, in SC-2 reagent, each composition volume ratio is HCl: H 2o 2: H 2o=1: 1: 6,10 minutes time; And rinse well with deionized water (DI), N2 dries up.
In such scheme, described use sputtering unit surface, silicon wafer polishing face after cleaning adopts RF plasma sputtering Ti/Al 2o 3in the step of nano particle film layer structure, Ti thickness is 50nm ~ 80nm, Al 2o 3thickness is 5 μm ~ 6 μm, film thickness uniformity ± 3%.
In such scheme, described this silicon chip grinding liner that utilizes carries out thinning step to InP material, comprising: utilize this silicon chip grinding liner, by treating that thinning InP material is loaded on grinding clamp, starts thinning; This silicon chip grinding liner rotating speed 30rpm ~ 60rpm, InP material rotation 80rpm ~ 200rpm, grinding milk adopts aqueous sodium hypochlorite solution and 3 μm of Al 2o 3powder, pH value 11 ~ 12.5, pressure 0.1kg/cm 2.The thinning final thickness of described InP material is 60 μm.
In such scheme, described step of InP material being carried out to chemico-mechanical polishing, comprising: use polyimide resin polishing pad, polishing slurries composition is: 30nm particle diameter SiO 2powder and Tetramethylammonium hydroxide 5 ~ 10% (volume ratio) aqueous solution, pH value 12, polishing pad rotating speed 40rpm ~ 50rpm, InP material rotation 100rpm ~ 120rpm, pressure 0.15kg/cm 2, the thickness after InP material finish is less than 30 μm, terminates CMP (Chemical Mechanical Polishing) process.
In such scheme, described step of cleaning the InP material completing chemico-mechanical polishing, comprising: the fatty alcohol-ether sodium sulfate aqueous solution of adoption rate 1: 10 cleans the InP material completing chemico-mechanical polishing, solution temperature 40 DEG C, after having cleaned, hot nitrogen is used to dry up.
In such scheme, described by cleaning after InP material put into the step that ICP etching machine carries out plasma polishing, comprising: adopt Cl 2gas 30sccm, Ar gas 2sccm, RF power 20W ~ 40W, ICP power 200W ~ 300W, etch 10 minutes ~ 15 minutes, then etch 10 ~ 15 minutes with He gas 5sccm, RF10W.
(3) beneficial effect
As can be seen from technique scheme, the present invention has following beneficial effect:
Of the present inventionly this method that is thinning and polishing is carried out to InP material, effectively raise the surface topography after InP substrate polishing.The thinning course of processing adopts Slag coating Al 2o 3rete, as thinning grinding carrier, sputters Al 2o 3nano particle rete uniformity is good, and compactness is high, and the thinning surface uniformity of the InP substrate therefore prepared is outstanding, and InP substrate damage is little, thinningly itself does not introduce other impurity, pollution-free.Al 2o 3again can sputter new rete after rete consumption completes to continue to use, efficiency is high, reproducible.The precision that the plasma polishing process of final stage achieves surface roughness significantly promotes, and reaches the mirror effect of extension rank, can remove the residual impurity on InP surface with He.InP substrate final thickness is less than 30 μm, thickness error ± 1 μm, and surface roughness Ra is less than 2nm.
Accompanying drawing explanation
Fig. 1 provided by the inventionly carries out method flow diagram that is thinning and polishing to InP material;
Fig. 2 adopts Slag coating deposit Ti/Al according to the present invention 2o 3the schematic diagram of nano particle film layer structure;
Fig. 3 adopts Ti/Al according to the present invention 2o 3nano particle rete carries out thinning schematic diagram.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Provided by the invention method that is thinning and polishing is carried out to InP material, comprises the following steps:
Step 1: standard RCA clean technique is carried out to silicon chip:
(1), silicon chip is cleaned at 100 DEG C ~ 130 DEG C temperature with SC-3 reagent: in SC-3 reagent, each composition volume ratio is H 2sO 4: H 2o 2: H 2o=1: 3: 20,10 minutes time;
(2), with SC-1 reagent clean silicon chip at 65 ~ 80 DEG C of temperature, in SC-1 reagent, each composition volume ratio is NH 4oH: HO2: H2O=1: 1: 5,10 minutes time;
(3), with DHF clean silicon chip at 20 ~ 25 DEG C of temperature, in DHF, each composition volume ratio is HF: H 2o=1: 10,10 minutes time;
(4), with SC-2 reagent clean silicon chip at 65 ~ 80 DEG C of temperature, in SC-2 reagent, each composition volume ratio is HCl: H 2o 2: H 2o=1: 1: 6,10 minutes time;
(5), with deionized water (DI) rinse well, N 2dry up;
Step 2: use the silicon wafer polishing face surface of sputtering unit after step 1 is cleaned to adopt RF plasma sputtering Ti/Al 2o 3nano particle film layer structure, Ti thickness 50nm ~ 80nm, Al 2o 3thickness 5 μm ~ 6 μm, film thickness uniformity ± 3%, shown in Fig. 2;
Step 3: carry out reduction process to InP material: using the silicon chip of step 2 as polishing pad, will treat that thinning InP substrate is loaded on grinding clamp, starts thinning (shown in Fig. 3).Silicon chip grinding liner rotating speed 30rpm ~ 60rpm, InP substrate rotation 80rpm ~ 200rpm, grinding milk adopts aqueous sodium hypochlorite solution and 3 μm of Al 2o 3powder, pH value 11 ~ 12.5, pressure 0.1kg/cm 2.The thinning final thickness of InP substrate is about 60 μm.
Step 4: chemico-mechanical polishing (CMP) technique is carried out to InP material: use polyimide resin polishing pad, polishing slurries composition is: 30nm particle diameter SiO 2powder and Tetramethylammonium hydroxide 5 ~ 10% (volume ratio) aqueous solution, pH value 12, polishing pad rotating speed 40rpm ~ 50rpm, InP substrate rotation 100rpm ~ 120rpm, pressure 0.15kg/cm 2, the thickness after InP substrate polishing is less than 30 μm, terminates CMP.
Step 5: cleaning is carried out to the InP material completing CMP: adopt volume ratio be 1: 10 the fatty alcohol-ether sodium sulfate aqueous solution the carrying out of step 4 is cleaned, solution temperature 40 DEG C, after clean, use hot nitrogen dry up.
Step 6: the InP substrate of step 5 being cleaned end is put into ICP etching machine and carried out plasma polishing process.Adopt Cl 230sccm, Ar2sccm, RF power 20W ~ 40W, ICP power 200W ~ 300W, etch 10 minutes ~ 15 minutes, then etch 10 minutes ~ 15 minutes with He gas 5sccm, RF10W.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (7)

1. a method that is thinning and polishing is carried out to InP material, it is characterized in that, comprising:
Make and thinning silicon chip grinding liner is carried out to InP material;
This silicon chip grinding liner is utilized to carry out thinning to InP material;
Chemico-mechanical polishing is carried out to InP material;
The InP material completing chemico-mechanical polishing is cleaned; And
InP material after cleaning is put into ICP etching machine and carries out plasma polishing;
Wherein, described making carries out the step of thinning silicon chip grinding liner to InP material, comprising: carry out standard RCA clean technique to silicon chip; And use sputtering unit surface, silicon wafer polishing face after cleaning to adopt RF plasma sputtering Ti/Al 2o 3nano particle film layer structure, forms silicon chip grinding liner;
Described by cleaning after InP material put into the step that ICP etching machine carries out plasma polishing, comprising: adopt Cl 2gas 30sccm, Ar gas 2sccm, RF power 20W ~ 40W, ICP power 200W ~ 300W, etch 10 minutes ~ 15 minutes, then etch 10 minutes ~ 15 minutes with He gas 5sccm, RF10W.
2. according to claim 1ly carry out method that is thinning and polishing to InP material, it is characterized in that, described step of silicon chip being carried out to standard RCA clean technique, comprising:
Silicon chip is cleaned at 100 DEG C ~ 130 DEG C temperature with SC-3 reagent: in SC-3 reagent, each composition volume ratio is H 2sO 4: H 2o 2: H 2o=1:3:20,10 minutes time;
Clean silicon chip at 65 DEG C ~ 80 DEG C temperature with SC-1 reagent, in SC-1 reagent, each composition volume ratio is NH 4oH:H 2o 2: H 2o=1:1:5,10 minutes time;
Clean silicon chip at 20 ~ 25 DEG C of temperature with DHF, in DHF, each composition volume ratio is HF:H 2o=1:10,10 minutes time;
Clean silicon chip at 65 DEG C ~ 80 DEG C temperature with SC-2 reagent, in SC-2 reagent, each composition volume ratio is HCl:H 2o 2: H 2o=1:1:6,10 minutes time; And
Clean with deionized water rinsing, N 2dry up.
3. according to claim 1ly carry out method that is thinning and polishing to InP material, it is characterized in that, described use sputtering unit surface, silicon wafer polishing face after cleaning adopts RF plasma sputtering Ti/Al 2o 3in the step of nano particle film layer structure, Ti thickness is 50nm ~ 80nm, Al 2o 3thickness is 5 μm ~ 6 μm, film thickness uniformity ± 3%.
4. according to claim 1ly carry out method that is thinning and polishing to InP material, it is characterized in that, described this silicon chip grinding liner that utilizes carries out thinning step to InP material, comprising:
Utilizing this silicon chip grinding liner, by treating that thinning InP material is loaded on grinding clamp, starting thinning; This silicon chip grinding liner rotating speed 30rpm ~ 60rpm, InP material rotation 80rpm ~ 200rpm, grinding milk adopts aqueous sodium hypochlorite solution and 3 μm of Al 2o 3powder, pH value 11 ~ 12.5, pressure 0.1kg/cm 2.
5. according to claim 4ly carry out method that is thinning and polishing to InP material, it is characterized in that, the thinning final thickness of described InP material is 60 μm.
6. according to claim 1ly carry out method that is thinning and polishing to InP material, it is characterized in that, described step of InP material being carried out to chemico-mechanical polishing, comprising:
Use polyimide resin polishing pad, polishing slurries composition is: volume ratio is the 30nm particle diameter SiO of 5 ~ 10% 2powder and tetramethylammonium hydroxide aqueous solution, pH value 12, polishing pad rotating speed 40rpm ~ 50rpm, InP material rotation 100rpm ~ 120rpm, pressure 0.15kg/cm 2, the thickness after InP material finish is less than 30 μm, terminates CMP (Chemical Mechanical Polishing) process.
7. according to claim 1ly carry out method that is thinning and polishing to InP material, it is characterized in that, described step of cleaning the InP material completing chemico-mechanical polishing, comprising:
Employing volume ratio is that the fatty alcohol-ether sodium sulfate aqueous solution of 1:10 cleans the InP material completing chemico-mechanical polishing, and solution temperature 40 DEG C, after having cleaned, uses hot nitrogen to dry up.
CN201310068641.6A 2013-03-05 2013-03-05 Method for thinning and polishing InP material Active CN103199014B (en)

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TWI650392B (en) 2016-02-16 2019-02-11 美商卡博特微電子公司 Method for polishing III to V materials
CN105914137B (en) * 2016-06-23 2019-07-26 北京知投家知识产权运营有限公司 A kind of wet process silicon wafer cleaning method
CN106346318A (en) * 2016-11-09 2017-01-25 苏州长光华芯光电技术有限公司 InP (indium phosphide) wafer thinning and polishing method and chemical corrosion device

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CN101256952A (en) * 2008-03-27 2008-09-03 薛松生 Method and device for polishing wafer
CN102011106A (en) * 2010-09-07 2011-04-13 天津理工大学 Method for flattening diamond film by using composite process
CN102543665A (en) * 2010-12-07 2012-07-04 中国科学院微电子研究所 Improved rapid thinning method for gallium arsenide substrate

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JP2004337992A (en) * 2003-05-13 2004-12-02 Disco Abrasive Syst Ltd Fixed abrasive grain polishing pad, and method of polishing silicon wafer using fixed abrasive grain polishing pad

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101256952A (en) * 2008-03-27 2008-09-03 薛松生 Method and device for polishing wafer
CN102011106A (en) * 2010-09-07 2011-04-13 天津理工大学 Method for flattening diamond film by using composite process
CN102543665A (en) * 2010-12-07 2012-07-04 中国科学院微电子研究所 Improved rapid thinning method for gallium arsenide substrate

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