CN103180934A - 用于提高bjt电流增益的低温注入 - Google Patents
用于提高bjt电流增益的低温注入 Download PDFInfo
- Publication number
- CN103180934A CN103180934A CN2011800512790A CN201180051279A CN103180934A CN 103180934 A CN103180934 A CN 103180934A CN 2011800512790 A CN2011800512790 A CN 2011800512790A CN 201180051279 A CN201180051279 A CN 201180051279A CN 103180934 A CN103180934 A CN 103180934A
- Authority
- CN
- China
- Prior art keywords
- dosage
- substrate
- integrated circuit
- individual atom
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000007943 implant Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000001816 cooling Methods 0.000 claims abstract description 13
- 239000002019 doping agent Substances 0.000 claims abstract description 12
- 238000002513 implantation Methods 0.000 claims description 28
- 238000002347 injection Methods 0.000 claims description 23
- 239000007924 injection Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 229910052785 arsenic Inorganic materials 0.000 claims description 14
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052787 antimony Inorganic materials 0.000 claims description 7
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000002826 coolant Substances 0.000 description 2
- 239000012809 cooling fluid Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26593—Bombardment with radiation with high-energy radiation producing ion implantation at a temperature lower than room temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
Abstract
本发明涉及一种形成包括双极结晶体管（BJT）（1002）和金属氧化物半导体（MOS）（1004）晶体管的集成电路的工艺，其通过冷却集成电路衬底至5℃或更低温度，并且同时根据核素种类以指定的最小剂量将掺杂剂注入到BJT的发射极区域和MOS晶体管的源极和漏极中来实现。
Description
技术领域
本发明涉及集成电路领域，且更具体地，本发明涉及集成电路中的离子注入层。
背景技术
集成电路可包含npn双极结晶体管（BJT）和n沟道金属氧化物半导体（NMOS）晶体管，例如用以分别提供模拟功能和逻辑功能。NMOS晶体管的源极和漏极区域和npn BJT的发射极区域可同时形成以降低制造成本。形成源极和漏极区域和发射极区域的工艺步骤可包括离子注入大于6×1013个原子/cm2剂量的砷，例如用以在NMOS晶体管中获得理想的电阻。离子注入的砷可在发射极区域形成密度高于1×107个缺陷/cm2的射程末端（end-of-range）缺陷，有时被称为位错环（dislocation loops）。射程末端缺陷可能例如通过减小电流增益（也被称为hfe）不利地影响npn双极结晶体管的性能。后续热退火可能不足以减小射程末端缺陷至期望水平，因为在NMOS晶体管实例中获得期望的性能水平和成品率可通过在砷离子注入步骤后限制集成电路的总体热曲线来实现。接收产生高于l×107个射程末端缺陷/cm2的剂量的离子注入以便例如提供电活性掺杂剂或非晶化集成电路的衬底的集成电路中的其它装置可能由于射程末端缺陷而遭受性能参数的退化。
发明内容
一种包括npn双极结晶体管（BJT）和NMOS晶体管的集成电路可以通过以下步骤形成：冷却集成电路的衬底至5℃或更低温度，并且同时穿过注入屏蔽介电层以至少6×1013个原子/cm2的剂量离子注入砷到npn BJT的发射极区域和NMOS晶体管的源极和漏极中。一种包括pnp BJT和p沟道金属氧化物半导体（PMOS）晶体管的集成电路可以通过以下步骤形成：冷却集成电路的衬底至5℃或更低温度，并且同时穿过注入屏蔽介电层以至少6×1013个原子/cm2的剂量离子注入镓和/或铟到pnp BJT的发射极区域和PMOS晶体管的源极和漏极中。一种包括注入区域的集成电路可以通过以下步骤形成：冷却集成电路的衬底至5℃或更低温度，并且穿过注入屏蔽介电层以可在冷却到20℃到25℃的衬底中产生至少l×107个射程末端缺陷/cm2的剂量离子注入核素到注入区域中。
附图说明
图1描述了根据实施本发明原理的示例性实施例的形成集成电路的工艺。
图2是示出双极结晶体管（BJT）中作为衬底温度的函数的hfe的提高的图表。
图3描述了根据经修改实施例的形成集成电路的工艺。
具体实施方式
一种集成电路可通过以下步骤形成：冷却集成电路的衬底至5℃或更低温度，并且穿过注入屏蔽介电层以可在冷却到20℃到25℃的衬底中产生至少l×107个射程末端缺陷/cm2的剂量离子注入核素到衬底的区域中。
在一个实施例中，离子注入步骤可包括以至少l×1016个原子/cm2的剂量注入硼。在另一个实施例中，离子注入步骤可包括以至少8×1014个原子/cm2的剂量注入磷。在进一步的实施例中，离子注入步骤可包括以至少7×1013个原子/cm2的剂量注入镓。在另一个实施例中，离子注入步骤可包括以至少6×1013个原子/cm2的剂量注入锗。在进一步的实施例中，离子注入步骤可包括以至少6×1013个原子/cm2的剂量注入砷。在另一个实施例中，离子注入步骤可包括以至少6×1013个原子/cm2的剂量注入铟。在进一步的实施例中，离子注入步骤可包括以至少6×1013个原子/cm2的剂量注入锑。
在第一实施例中，一种包括npn BJT和NMOS晶体管的集成电路可通过以下步骤形成：冷却集成电路的衬底至5℃或更低温度，并且穿过注入屏蔽介电层同时以上面列出的剂量离子注入磷、砷和/或锑到npn BJT的发射极区域和NMOS晶体管的源极和漏极中。
在第二实施例中，一种包括pnp BJT和p沟道金属氧化物半导体（PMOS）晶体管的集成电路可通过以下步骤形成：冷却集成电路的衬底至5℃或更低温度，并且穿过注入屏蔽介电层同时以上面列出的剂量离子注入硼、镓和/或铟到pnp BJT的发射极区域和PMOS晶体管的源极和漏极中。
在第三实施例中，一种包括注入区域的集成电路可通过以下步骤形成：冷却集成电路的衬底至5℃或更低温度，并且穿过注入屏蔽介电层以上面列出的剂量离子注入硼、磷、镓、锗、砷、铟和/或锑到注入区域中。
图1描述了根据第一或第二实施例的形成集成电路的工艺。集成电路1000包括为BJT1002定义的区域和为金属氧化物半导体（MOS）1004晶体管定义的区域。在第一实施例中，BJT1002为npn BJT且MOS晶体管1004为NMOS晶体管。在第二实施例中，BJT1002为pnp BJT且MOS晶体管1004为PMOS晶体管。集成电路1000被形成在包括硅顶部区域1008的衬底中且在其上面。衬底1006可以是单晶硅晶片、绝缘体上的硅（SOI）晶片、具有不同晶体取向的硅区域的混合取向技术（HOT）晶片，或适用于制造集成电路1000的具有硅顶部区域1008的其他结构。
BJT1002包括在硅顶部区域1008中的基底扩散区域1010。在第一实施例中，基底扩散区域1010为p型。在第二实施例中，基底扩散区域1010为n型。MOS晶体管1004包括栅极结构1012（其包含栅极和栅极介电层）和可能的栅极侧壁隔板。未示出的轻掺杂漏极（LDD）区域可以邻近栅极在衬底1006的顶表面形成。注入屏蔽介电层1014在衬底1006的顶表面上方形成。注入屏蔽介电层1014的厚度至少为5纳米。在一个实施例中，注入屏蔽介电层1014的厚度可至少为15纳米。注入屏蔽介电层1014可以或可以不延伸至衬底1006的侧边。在一个实施例中，注入屏蔽介电层1014可包括至少80%的二氧化硅。二氧化硅可以通过硅的热氧化在衬底1006的顶表面上形成，可以例如通过正硅酸乙酯（也被称为四乙氧基硅烷或TEOS）的分解被沉积在衬底1006上，或者可以通过其他工艺形成。
注入掩模1016在注入屏蔽介电层1014上方形成，使得暴露出BJT1002中的发射极区域1018并且暴露出MOS晶体管1004中的源极和漏极区域1020。注入掩模1016可利用光刻工艺由光刻胶或其他光敏复合物形成，或者例如通过掩模和刻蚀工艺由其他介电材料形成。
衬底1006的背表面接触衬底卡盘1022。衬底卡盘1022被冷却至5℃或更低温度，例如通过使冷却液流体1024流经衬底卡盘1022，如图1中冷却液流向箭头1026所示，直到衬底1006被冷却至5℃或更低温度。冷却衬底卡盘1022的其他手段也在本实施例的范围之内。
当衬底1006被冷却至5℃或更低温度时，执行离子注入工艺1028，其将掺杂核素种类注入到发射极区域1018和源极和漏极区域1020中。在第一实施例中，离子注入工艺1028可以注入剂量至少为8×1014个原子/cm2的磷，和/或可以注入剂量至少为6×1013个原子/cm2的砷，和/或可以注入剂量至少为6×1013个原子/cm2的锑。在第一实施例的一个版本中，离子注入工艺1028可以注入剂量至少为4×1014个原子/cm2的砷。在第一实施例的另一个版本中，离子注入工艺1028可以注入剂量至少为1×1015个原子/cm2的砷。在第二实施例中，离子注入工艺1028可以注入剂量至少为1×1016个原子/cm2的硼，和/或可以注入剂量至少为7×1013个原子/cm2的镓，和/或可以注入剂量至少为6×1013个原子/cm2的铟。在第一和第二实施例的一个版本中，发射极区域1018和源极和漏极区域1020中的硅顶部区域1008中的硅衬底材料可在衬底1006的顶表面处被非晶化到至少15纳米的深度。如参考图1所描述的形成发射极区域1018相比在衬底冷却至20°C到25°C期间利用具有同样剂量和能量的发射极注入工艺形成的类似BJT可提供具有提高的hfe的BJT1002。
图2示出npn双极结晶体管（BJT）中作为衬底温度（在图2中示为“注入机冷却器温度”）的函数的hfe的提高。平均数据点2000描述用如参考图1描述的发射极注入形成的一组npn BJT的hfe的平均值。范围条2002描述在每个衬底温度值下的hfe值的+/-3标准偏差范围。趋势线2004被提供作为指引以通过插值估算hfe值。
图3描述了根据第三实施例的形成集成电路的工艺。集成电路3000被形成在包括硅顶部区域3004的衬底3002中和其上。衬底3002和硅顶部区域3004具有如参考图1所描述的衬底1006和硅顶部区域1008的特性。注入屏蔽介电层3006在衬底3002的顶面上方形成。注入屏蔽介电层3006具有如参考图1所描述的注入屏蔽介电层1014的特性。注入掩模3008被形成在注入屏蔽介电层3006上方，使得暴露出集成电路3000中的注入区域3010。注入掩模3008具有如参考图1所描述的注入掩模1016的特性。
衬底3002的背表面接触衬底卡盘3012。衬底卡盘3012被冷却至5℃或更低温度，例如通过使冷却液流体3014流经衬底卡盘3012，如图3中冷却液流向箭头3016所示，直到衬底3002被冷却至5℃或更低温度。冷却衬底卡盘3012的其他手段也在本实施例的范围之内。
当衬底3002被冷却至5℃或更低温度时，执行离子注入工艺3018，其将一种或更多种掺杂剂和/或非晶化原子种类注入到注入区域3010中。在本（第三）实施例中，离子注入工艺3018可以注入剂量至少为1×1016个原子/cm2的硼，和/或可以注入剂量至少为8×1014个原子/cm2的磷，和/或可以注入剂量至少为7×1013个原子/cm2的镓，和/或可以注入剂量至少为6×1013个原子/cm2的锗，和/或可以注入剂量至少为6×1013个原子/cm2的砷，和/或可以注入剂量至少为6×1013个原子/cm2的铟，和/或可以注入剂量至少为6×1013个原子/cm2的锑。在本（第三）实施例的一个版本中，注入区域3010中的硅顶部区域3004中的硅衬底材料可以在衬底3002的顶表面上被非晶化到至少15纳米的深度。如参考图3所描述的形成注入区域3010相比利用在衬底冷却至20°C到25°C期间具有同样剂量和能量的注入工艺（其导致大于1×107个缺陷/cm2）所形成的类似注入区域可导致小于1×107个缺陷/cm2。
本发明涉及领域的技术人员将理解，可对所描述的示例性实施例和在本发明的保护范围之内实现的其它实施例做出修改。
Claims (9)
1.一种形成包括npn双极结晶体管BJT和n沟道金属氧化物半导体NMOS晶体管的集成电路的工艺，其包括：
在所述npn BJT的发射极区域和所述NMOS晶体管的源极和漏极区域之上，在所述集成电路的衬底的硅顶部区域的顶表面上方形成注入屏蔽介电层；
在所述注入屏蔽介电层上方形成注入掩模，使得暴露出所述发射极区域和所述源极和漏极区域；
使所述集成电路的所述衬底与衬底卡盘接触；
冷却所述衬底卡盘，使得所述集成电路的所述衬底被冷却至5℃的温度或更低温度；以及
当所述衬底被冷却至5℃或更低温度时，同时将n型掺杂剂离子注入到所述发射极区域和所述源极和漏极区域中，其中所述n型掺杂剂和所述n型掺杂剂的剂量选自由以下各项组成的群组：
剂量至少为8×1014个原子/cm2的磷，
剂量至少为6×1013个原子/cm2的砷，
剂量至少为6×1013个原子/cm2的锑，以及
其任意组合。
2.根据权利要求1所述的工艺，其中所述n型掺杂剂包括剂量至少为4×1014个原子/cm2的砷。
3.根据权利要求1所述的工艺，其中所述n型掺杂剂包括剂量至少为1×1015个原子/cm2的砷。
4.根据权利要求1所述的工艺，其中所述注入屏蔽介电层包括至少80%的二氧化硅。
5.根据权利要求1所述的工艺，其中离子注入所述n型掺杂剂的步骤将所述发射极区域和所述源极和漏极区域中的硅顶部区域的顶表面处的硅材料非晶化到至少15纳米的深度。
6.一种形成包括pnp双极结晶体管BJT和p沟道金属氧化物半导体PMOS晶体管的集成电路的工艺，其包括：
在所述pnp BJT的发射极区域和所述PMOS晶体管的源极和漏极区域之上，在所述集成电路的衬底的硅顶部区域的顶表面上方形成注入屏蔽介电层；
在所述注入屏蔽介电层上方形成注入掩模，使得暴露出所述发射极区域和所述源极和漏极区域；
使所述集成电路的所述衬底与衬底卡盘接触；
冷却所述衬底卡盘，使得所述集成电路的所述衬底被冷却至5℃的温度或更低温度；以及
当所述衬底被冷却至5℃或更低温度时，同时将p型掺杂剂离子注入到所述发射极区域和所述源极和漏极区域中，其中所述p型掺杂剂和所述p型掺杂剂的剂量选自由剂量至少为l×1016个原子/cm2的硼、剂量至少为7×1013个原子/cm2的镓、剂量至少为6×1013个原子/cm2的铟及其任意组合所组成的群组。
7.根据权利要求6所述的工艺，其中所述注入屏蔽介电层包括至少80%的二氧化硅。
8.根据权利要求6所述的工艺，其中离子注入所述p型掺杂剂的步骤将所述发射极区域和所述源极和漏极区域中的硅顶部区域的顶表面处的硅材料非晶化到至少15纳米的深度。
9.一种形成包含注入区域的集成电路的工艺，其包括：
在所述注入区域之上，在所述集成电路的衬底的硅顶部区域的顶表面上方形成注入屏蔽介电层；
在所述注入屏蔽介电层上方形成注入掩模，使得暴露出所述注入区域；
使所述集成电路的所述衬底与衬底卡盘接触；
冷却所述衬底卡盘，使得所述集成电路的所述衬底被冷却至5℃的温度或更低温度；以及
当所述衬底被冷却至5℃或更低温度时，离子注入原子到所述注入区域中，其中所述原子和所述原子的剂量选自由以下各项组成的群组：
剂量至少为l×1016个原子/cm2的硼，
剂量至少为8×1014个原子/cm2的磷，
剂量至少为7×1013个原子/cm2的镓，
剂量至少为6×1013个原子/cm2的锗，
剂量至少为6×1013个原子/cm2的砷，
剂量至少为6×1013个原子/cm2的铟，
剂量至少为6×1013个原子/cm2的锑，以及
其任意组合。
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US40636410P | 2010-10-25 | 2010-10-25 | |
| US61/406,364 | 2010-10-25 | ||
| US13/246,362 US8772103B2 (en) | 2010-10-25 | 2011-09-27 | Low temperature implant scheme to improve BJT current gain |
| US13/246,362 | 2011-09-27 | ||
| PCT/US2011/057679 WO2012061130A2 (en) | 2010-10-25 | 2011-10-25 | Low temperature implant to improve bjt current gain |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103180934A true CN103180934A (zh) | 2013-06-26 |
Family
ID=45973373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011800512790A Pending CN103180934A (zh) | 2010-10-25 | 2011-10-25 | 用于提高bjt电流增益的低温注入 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8772103B2 (zh) |
| JP (1) | JP2013545303A (zh) |
| CN (1) | CN103180934A (zh) |
| WO (1) | WO2012061130A2 (zh) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9299698B2 (en) * | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
| US10128113B2 (en) * | 2016-01-12 | 2018-11-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
| US9923083B1 (en) | 2016-09-09 | 2018-03-20 | International Business Machines Corporation | Embedded endpoint fin reveal |
| US10243048B2 (en) * | 2017-04-27 | 2019-03-26 | Texas Instruments Incorporated | High dose antimony implant through screen layer for n-type buried layer integration |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5244820A (en) * | 1990-03-09 | 1993-09-14 | Tadashi Kamata | Semiconductor integrated circuit device, method for producing the same, and ion implanter for use in the method |
| US6030864A (en) * | 1996-04-12 | 2000-02-29 | Texas Instruments Incorporated | Vertical NPN transistor for 0.35 micrometer node CMOS logic technology |
| KR20100074625A (ko) * | 2008-12-24 | 2010-07-02 | 주식회사 하이닉스반도체 | 반도체 소자의 채널 정션 형성 방법 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH027422A (ja) * | 1988-06-24 | 1990-01-11 | Ricoh Co Ltd | レーザによる高温熱処理方法 |
| JP3638424B2 (ja) * | 1997-01-20 | 2005-04-13 | 株式会社東芝 | 半導体装置の製造方法及び半導体製造装置 |
| JP2001068427A (ja) * | 1999-08-26 | 2001-03-16 | Ulvac Japan Ltd | 基板冷却装置 |
| JP2001210735A (ja) * | 2000-01-27 | 2001-08-03 | Mitsumi Electric Co Ltd | Ｃｍｏｓデバイス及びｃｍｏｓデバイスの製造方法 |
| US7993698B2 (en) * | 2006-09-23 | 2011-08-09 | Varian Semiconductor Equipment Associates, Inc. | Techniques for temperature controlled ion implantation |
| JP2011508436A (ja) * | 2007-12-21 | 2011-03-10 | アプライド マテリアルズ インコーポレイテッド | 基板の温度を制御するための方法及び装置 |
-
2011
- 2011-09-27 US US13/246,362 patent/US8772103B2/en active Active
- 2011-10-25 JP JP2013536721A patent/JP2013545303A/ja active Pending
- 2011-10-25 WO PCT/US2011/057679 patent/WO2012061130A2/en active Application Filing
- 2011-10-25 CN CN2011800512790A patent/CN103180934A/zh active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5244820A (en) * | 1990-03-09 | 1993-09-14 | Tadashi Kamata | Semiconductor integrated circuit device, method for producing the same, and ion implanter for use in the method |
| US6030864A (en) * | 1996-04-12 | 2000-02-29 | Texas Instruments Incorporated | Vertical NPN transistor for 0.35 micrometer node CMOS logic technology |
| KR20100074625A (ko) * | 2008-12-24 | 2010-07-02 | 주식회사 하이닉스반도체 | 반도체 소자의 채널 정션 형성 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012061130A3 (en) | 2012-06-28 |
| JP2013545303A (ja) | 2013-12-19 |
| US8772103B2 (en) | 2014-07-08 |
| WO2012061130A2 (en) | 2012-05-10 |
| US20120100680A1 (en) | 2012-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7816237B2 (en) | Ultra shallow junction formation by epitaxial interface limited diffusion | |
| KR101811109B1 (ko) | 스크리닝층을 갖는 깊게 공핍된 mos 트랜지스터 및 그 방법 | |
| US8530961B2 (en) | Compatible vertical double diffused metal oxide semiconductor transistor and lateral double diffused metal oxide semiconductor transistor and manufacture method thereof | |
| US6063682A (en) | Ultra-shallow p-type junction having reduced sheet resistance and method for producing shallow junctions | |
| TWI232546B (en) | Manufacturing method of semiconductor device and semiconductor device | |
| CN103180934A (zh) | 用于提高bjt电流增益的低温注入 | |
| CN104752419B (zh) | 集成电路及其制造方法 | |
| US7691714B2 (en) | Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor | |
| US10068802B2 (en) | Threshold mismatch and IDDQ reduction using split carbon co-implantation | |
| TWI496219B (zh) | 金屬氧化物半導體場效應電晶體及其製造方法 | |
| US20160190237A1 (en) | Latchup reduction by grown orthogonal substrates | |
| CN101996885A (zh) | Mos晶体管及其制作方法 | |
| TW200935522A (en) | Transistor and fabricating method thereof | |
| CN107393872B (zh) | 一种bcd工艺中寄生型npn三极管的制作方法 | |
| KR20120062367A (ko) | 반도체 소자의 제조방법 | |
| CN111696854B (zh) | 半导体器件的制造方法 | |
| US20070034949A1 (en) | Semiconductor device having multiple source/drain extension implant portions and a method of manufacture therefor | |
| JPH11274090A (ja) | 浅い接合を有するデバイスの製造方法 | |
| CN114496760B (zh) | 一种mos晶体管的形成方法 | |
| US7479438B2 (en) | Method to improve performance of a bipolar device using an amorphizing implant | |
| CN102544080A (zh) | 锗硅异质结双极晶体管及制造方法 | |
| JPH06350086A (ja) | 半導体装置の製造方法 | |
| CN116206959A (zh) | 一种半导体器件及其制造方法和电子装置 | |
| KR101191156B1 (ko) | 반도체 소자의 형성 방법 | |
| CN115101416A (zh) | 一种鳍式场效应晶体管的制造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130626 |