CN103151279A - 一种半导体封装方法 - Google Patents
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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Abstract
本发明公开了一种半导体封装方法,包括以下步骤:在基板或框架上制作凸点,将芯片倒装焊接在凸点基板或凸点框架上。所述倒装焊接为热压或倒装回流的方式。还包括:通过回流将凸点固化,然后在芯片和基板之间填充胶水。本发明是由基板或框架厂利用自身的技术优势在基板或框架上预制凸点,相比芯片上制作凸点更容易,也更好操,芯片上无需再制作凸点,封装只需完成倒装工艺。采用本发明的方式省去了封装过程中芯片凸点制造的工艺流程,减少生产投入,减少制造周期,节约了封装成本,提高封装合格率。
Description
技术领域
本发明涉及封装领域,具体涉及一种半导体封装方法。
背景技术
半导体封装倒装焊接的常规做法是圆片厂提供带有焊点的圆片,封装厂根据功能需要在芯片上制作凸点,凸点一般为铜柱或金凸点,再将带有凸点的芯片通过回流或热压的方式倒装焊接在基板或框架上。现有的方式在芯片上制作凸点,生产成本高,封装厂投入大,工艺流程长。
发明内容
在下文中给出关于本发明的简要概述,以便提供关于本发明的某些方面的基本理解。应当理解,这个概述并不是关于本发明的穷举性概述。它并不是意图确定本发明的关键或重要部分,也不是意图限定本发明的范围。其目的仅仅是以简化的形式给出某些概念,以此作为稍后论述的更详细描述的前序。
本发明实施例的目的是针对上述现有技术的缺陷,提供一种减少封装流程,降低封装成本及周期的半导体封装方法。
为了实现上述目的,本发明采取的技术方案是:
一种半导体封装方法,包括以下步骤:
在基板或框架上制作凸点,将芯片倒装焊接在凸点基板或凸点框架上。
所述倒装焊接为热压或倒装回流的方式。
本发明提供的优选方案:一种半导体封装方法,包括以下步骤:
在基板上设置基板焊盘,在基板焊盘上预制铜柱,然后在铜柱上印刷焊锡膏,得到凸点基板;
再将不导电连接胶涂覆在凸点基板正面;
最后通过热压焊接的方式将芯片倒装焊接在凸点基板上。
本发明提供的另一优选方案:在框架上预制铜柱,然后在铜柱上印刷焊锡膏,得到凸点框架;
再通过热压焊接的方式将芯片倒装焊接在框架上。
本发明的技术方案:还包括:
通过回流将凸点固化,然后在芯片和基板之间填充胶水。
与现有技术相比,本发明的有益效果是:
本发明是由基板或框架厂利用自身的技术优势在基板或框架上预制凸点,相比芯片上制作凸点更容易,也更好操,芯片上无需再制作凸点,封装只需完成倒装工艺。采用本发明的方式省去了封装过程中芯片凸点制造的工艺流程,减少生产投入,减少制造周期,节约了封装成本,提高封装合格率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1是现有Flip Chip(倒装封装)基板结构示意图。
图2是本发明实施例提供的含凸点的FC基板结构示意图;
图3是涂覆有NCP胶的凸点基板结构示意图;
图4是芯片倒装焊接于凸点基板的结构示意图;
图5是现有框架结构示意图;
图6是本发明实施例提供的含凸点的框架结构示意图;
图7是芯片倒装焊接于凸点框架的结构示意图;
图8是本发明实施例提供的工艺流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意,为了清楚的目的,附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。基于本发明中的实施例,本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明提供一种半导体封装方法,包括以下步骤:
在基板或框架上制作凸点,将芯片倒装焊接在凸点基板或凸点框架上。
本发明的方法在基板或框架上制作凸点,相比于在芯片上制作凸点更容易,省去了封装过程中芯片凸点制造的工艺流程,减少生产投入,减少制造周期,节约了封装成本。
优选的,可以采用为热压或倒装回流的方式进行倒装焊接。
参见图1、图2、图3、图4和图8,本发明提供的一种方案:一种半导体封装方法,包括以下步骤:
在基板100上设置基板焊盘101,在基板焊盘101上预制铜柱102,然后在铜柱102上印刷焊锡膏103,得到凸点基板10;
再将不导电连接胶104涂覆在凸点基板10正面;
最后通过热压焊接的方式将芯片1倒装焊接在凸点基板10上。
参见图8,一种半导体封装方法,包括以下步骤:
在基板或框架上预制铜柱,然后在铜柱上印刷焊锡膏,得到凸点基板或凸点框架;
将圆片芯片与凸点基板倒装焊接,然后通过回流将凸点固化,再进行底部填充,在芯片和基板之间填充胶水,当为框架时,在芯片和框架之间填充胶水,最后进行后续的工序。
参见图5、图6和图7,本发明提供的另一方案:一种半导体封装方法,包括以下步骤:
在框架200上预制铜柱201,然后在铜柱201上印刷焊锡膏202,得到凸点框架20;
再通过热压焊接的方式将芯片1倒装焊接在凸点框架20上。
本发明通过基板或框架厂在基板或框架上完成铜柱(含焊料)或焊球的制作;芯片的焊盘上不再需要传统的铝层;封装工序采用点NCP(不导电连接胶)胶热压或倒装回流的方式将芯片倒装焊接于凸点基板或凸点框架上。添加NCP胶或底部填充胶水,增加了整体强度。本发明在基板/框架上完成凸点,芯片焊盘表面取消铝层,后工序完成倒装的方法,可以发挥基板/框架厂在凸点制作方面的优势,减少芯片成本,降低封装厂制作芯片凸点的成本,减少封装流程,提高封装合格率、降低封装的成本及周期。
在本发明上述各实施例中,实施例的序号仅仅便于描述,不代表实施例的优劣。对各个实施例的描述都各有侧重,某个实施例中没有详述的部分,可以参见其他实施例的相关描述。
在本发明的装置和方法等实施例中,显然,各部件或各步骤是可以分解、组合和/或分解后重新组合的。这些分解和/或重新组合应视为本发明的等效方案。同时,在上面对本发明具体实施例的描述中,针对一种实施方式描述和/或示出的特征可以以相同或类似的方式在一个或更多个其它实施方式中使用,与其它实施方式中的特征相组合,或替代其它实施方式中的特征。
应该强调,术语“包括/包含”在本文使用时指特征、要素、步骤或组件的存在,但并不排除一个或更多个其它特征、要素、步骤或组件的存在或附加。
最后应说明的是:虽然以上已经详细说明了本发明及其优点,但是应当理解在不超出由所附的权利要求所限定的本发明的精神和范围的情况下可以进行各种改变、替代和变换。而且,本发明的范围不仅限于说明书所描述的过程、设备、手段、方法和步骤的具体实施例。本领域内的普通技术人员从本发明的公开内容将容易理解,根据本发明可以使用执行与在此所述的相应实施例基本相同的功能或者获得与其基本相同的结果的、现有和将来要被开发的过程、设备、手段、方法或者步骤。因此,所附的权利要求旨在在它们的范围内包括这样的过程、设备、手段、方法或者步骤。
Claims (5)
1.一种半导体封装方法,其特征在于,包括以下步骤:
在基板或框架上制作凸点,将芯片倒装焊接在凸点基板或凸点框架上。
2.根据权利要求1所述的半导体封装方法,其特征在于,所述倒装焊接为热压或倒装回流的方式。
3.根据权利要求1所述的半导体封装方法,其特征在于,包括以下步骤:
在基板上设置基板焊盘,在基板焊盘上预制铜柱,然后在铜柱上印刷焊锡膏,得到凸点基板;
再将不导电连接胶涂覆在凸点基板正面;
最后通过热压焊接的方式将芯片倒装焊接在凸点基板上。
4.根据权利要求1所述的半导体封装方法,其特征在于,包括以下步骤:
在框架上预制铜柱,然后在铜柱上印刷焊锡膏,得到凸点框架;
再通过热压焊接的方式将芯片倒装焊接在凸点框架上。
5.根据权利要求1所述的半导体封装方法,其特征在于,还包括:
通过回流将凸点固化,然后在芯片和基板之间填充胶水。
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CN108598254A (zh) * | 2018-04-19 | 2018-09-28 | 嘉盛半导体(苏州)有限公司 | 滤波器封装方法及封装结构 |
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US20070099348A1 (en) * | 2005-11-01 | 2007-05-03 | Nirmal Sharma | Methods and apparatus for Flip-Chip-On-Lead semiconductor package |
TW200941651A (en) * | 2008-03-21 | 2009-10-01 | Chipmos Technologies Inc | Flip chip package structure and process thereof |
US20120252168A1 (en) * | 2011-04-01 | 2012-10-04 | International Business Machines Corporation | Copper Post Solder Bumps on Substrate |
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US20070099348A1 (en) * | 2005-11-01 | 2007-05-03 | Nirmal Sharma | Methods and apparatus for Flip-Chip-On-Lead semiconductor package |
TW200941651A (en) * | 2008-03-21 | 2009-10-01 | Chipmos Technologies Inc | Flip chip package structure and process thereof |
US20120252168A1 (en) * | 2011-04-01 | 2012-10-04 | International Business Machines Corporation | Copper Post Solder Bumps on Substrate |
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CN108598254A (zh) * | 2018-04-19 | 2018-09-28 | 嘉盛半导体(苏州)有限公司 | 滤波器封装方法及封装结构 |
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