200941651 iu-ζυυ/u»004 26543twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝结構及其製程，且特別 是有關於一種可防止配置於晶片承載器上的晶片傾斜的晶 片封裝結構及其製程。 【先前技術】 在現今的資訊社會中，均追求高速度、高品質、多工 能性的產品’而就產品外觀而言，係朝向輕、薄、短、小 的趨勢邁進。一般電子產品均具有晶片及與晶片連接的基 板（例如晶片承載器），晶片主要可藉由打線接合(wire bonding，WB)技術、覆晶接合(fup Chip，FC)技術或是捲帶 自動接合(tape automated bonding，TAB)技術與基板電性連 接。而習知覆晶接合及捲帶自動接合封裝技術中，晶片的 主動表面上主要配置有多個凸塊，晶片透過凸塊與基板電 性連接’然後在晶片與基板之間會填充一封膠體 (encapsulant)以保護凸塊且增加晶片和基板之接合度。 因晶片是藉由凸塊從基板接收到訊號或傳送訊號到 基板，所以凸塊與基板之間接合的可靠度對於晶片與基板 之間的訊號傳輸品質有決定性的影響。一般而言，凸塊可 視需求而配置於晶片之主動表面的中^區域或者是周邊區 域。當凸塊需置於晶片之主動表面的中心區域時，凸 將位於晶片的多個中心焊墊上。 圖1繪示習知之具有中心焊塾的覆晶封裝結構的剖面 200941651 ID-200708004 26543twf.doc/n 圖。請參照圖1，覆晶封裝結構100具有一晶片承載器110、 一晶片120、多個凸塊130 (於圖1中僅繪示一個凸塊13〇 做為代表）以及一封膠體140。其中，晶片120配置於晶 片承載器110上。晶片120具有多個中心焊墊122，這些 中心焊墊122配置於晶片12〇之主動表面124的一中心區 域F内。凸塊130配置於中心焊墊122上，並電性連接於 晶片120以及晶片承載器110之間，也就是說凸塊13〇也200941651 iu-ζυυ/u»004 26543twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a chip package structure and a process thereof, and more particularly to a device for preventing placement on a wafer Wafer-on-wafer wafer package structure and its process. [Prior Art] In today's information society, products that pursue high speed, high quality, and versatility are being pursued. In terms of product appearance, the trend is toward light, thin, short, and small. Generally, electronic products have a wafer and a substrate (for example, a wafer carrier) connected to the wafer. The wafer can be mainly bonded by wire bonding (WB) technology, flip chip (FC) technology, or tape and tape bonding. (tape automated bonding, TAB) technology is electrically connected to the substrate. In the conventional flip chip bonding and tape automated bonding package technology, a plurality of bumps are mainly disposed on the active surface of the wafer, and the wafer is electrically connected to the substrate through the bumps, and then a colloid is filled between the wafer and the substrate. Encapsulant to protect the bumps and increase the degree of bonding between the wafer and the substrate. Since the wafer receives signals or signals from the substrate to the substrate by bumps, the reliability of bonding between the bumps and the substrate has a decisive influence on the quality of signal transmission between the wafer and the substrate. In general, the bumps can be disposed in the middle region of the active surface of the wafer or in the peripheral region as desired. When the bumps are to be placed in the central region of the active surface of the wafer, the bumps will lie on a plurality of center pads of the wafer. 1 is a cross-sectional view of a conventional flip-chip package structure having a center solder bump 200941651 ID-200708004 26543twf.doc/n. Referring to FIG. 1, the flip chip package structure 100 has a wafer carrier 110, a wafer 120, a plurality of bumps 130 (only one bump 13 is shown in FIG. 1), and a gel 140. The wafer 120 is disposed on the wafer carrier 110. The wafer 120 has a plurality of center pads 122 disposed in a central region F of the active surface 124 of the wafer 12. The bumps 130 are disposed on the center pad 122 and electrically connected between the wafer 120 and the wafer carrier 110, that is, the bumps 13
是配置於晶片120之主動表面124的中心區域f内。封膠 體140配置於晶片120以及晶片承載器11〇之間並包覆凸 塊 130 〇 於習知技術中，封膠體140的材質為液態膠材時，製 作覆晶封裝結構100的方法為先將晶片120與晶片承載器 11〇接合，之後再以點膠方式塗佈於晶片12〇周邊，並利 用毛細作用使其流入晶片120與晶片承載器n〇之間。然 而，以此種方法需先將晶片12〇固定於晶片承載器11〇^ 才填入封膠體14G，且凸塊13G配置於晶片12Q之主動表 面124的中心區域F内，因此將晶片12〇與晶片承載器^ 接合時容易有傾斜問題。此外，封膠體⑽需透過‘ 象填充於晶片120與晶片承載器11()之間，因此封膠體刚 容易因為不易填滿晶片m與晶片承载器11()、 孔隙且需時較久。 ϋ 而後’隨著業界於材料與製程上的不斷研發，非 膠體(N〇n-c〇nductive paste，NCP)亦可被用做為 140。當封膠體140的材質為非導電膠體時，製作覆晶封裝 200941651 iu-ζνν /u6〇04 26543twf.doc/n 結構100的方法可以是先在晶片承載器no上塗佈封膠體 140，然後再將晶片120配置於晶片承載器H0上使凸塊 130與晶片承載器連接。然而，此方法容易因封膠體 140的表面不平坦而造成晶片120傾斜，且封勝體14〇容 易溢流並產生孔洞。 【發明内容】 ❹ 本發明提出一種覆晶封裝結構，可避免習知晶片易於 傾斜、非導電膠體容易溢流及產生氣泡或液態膠材不易填 滿的問題。 本發明另提出一種覆晶封裝製程，可於晶片接合至晶 片承載器時使晶片獲得支撐而不易傾斜，且可防止非導電 膠體溢流。 為具體描述本發明之内容，在此提出一種覆晶封裝結 構包括一晶片承載器、一晶片、多個凸塊、一非導電膠體 ❹ （n〇n-conductWe paste)以及一擋牆。晶片承載器具有多 個第一接點。晶片具有一主動表面以及多個位於主動表面 上的焊墊，其中焊墊配置於主動表面的一中心區域内。凸 塊配置於焊墊上以使第一接點與焊墊電性連接。非導電膠 f配置於晶片與晶片承載ϋ之間以包覆凸塊。擋牆配置於 β曰片與晶片承載器之間，且位於被非導電膠體包覆的凸塊 周邊’而且擋牆與主動表面的部分區域接觸。 在本發明之—實施例中，晶片承载器包括一可撓性電 路板。 200941651 ΐυ-2ϋϋ/ϋ8〇04 26543twf.doc/n 在本發明之一實施例中，可撓性電路板係由聚醯亞胺 (Polyimide，PI)、聚酯類化合物(polyethylene terephthalate， PET)、聚醚醢亞胺(p〇lyetherimide，PEI)或紙所製成。 在本發明之一實施例中，可撓性電路板具有多條銅羯 引線’且這些第一接點為這些銅箔引線之端部。 在本發明之一實施例中，凸塊包括多個金凸塊、多個 銅凸塊或多個錫鉛凸塊。 ❹ 在本發明之一實施例中，凸塊包括多個結線凸塊或多 個電鍍凸塊。 在本發明之一實施例中，擋牆包括多個條狀阻擋圖 案’且各條狀阻擋圖案的邊緣與晶片的邊緣切齊。 在本發明之一實施例中，擋牆包括一環狀阻擋圖案， 且環狀阻擋圖案的外緣與晶片的邊緣切齊。 ^ 在本發明之一實施例中，擋牆的材質包括二階段熱固 性膠體或防焊材料。 … 在本發明之一實施例中，非導電膠體與擋牆連接。 在本發明之一實施例中，晶片承載器具有多個第二接 點，且第-接點與第二接點分別位於晶片承載器的二相對 表面上並對應電性連接。 在本發明之-實施例中，覆晶封裝結構更包括多個焊 球，且銲球與第二接點電性連接。 為具體描述本發明之内容，在此提出一種覆晶封裝製 〇首先，提供—晶片，晶片具有一主動表面以及多個位 於主動表面上的焊墊。接著，於晶片之焊塾上形成多個凸 200941651 ID-200708004 26543twf.doc/n 塊。然後，於主動表面上形成一擋牆，擋牆避開凸塊形成 區域圍出一區塊。之後，於區塊内的主動表面上形成一非 導電膠體，以包覆凸塊。然後，令晶片透過凸塊與一晶片 承載器電性連接。 在本發明之一實施例中，擔牆之材質包括二階段熱固 性膝體，而令晶片與晶片承载器電性連接的方法可以是先 部分固化二階段熱固性膠體，以使二階段熱固性膠體形成 〇 B階膠體。然後，翻轉晶片，以使晶片透過凸塊與晶片承 載益電性連接。之後，固化B階膠體與非導電膠體以使晶 片黏著於晶片承載器上。 在本發明之一實施例中，擋牆之材質包括防焊材料， 而令晶片與晶片承載器電性連接的方法可以是先翻轉晶 片’以使晶片透過凸塊與晶片承載器電性連接。然後，固 化非導電膠體，使晶片黏著於晶片承载器上。 在本發明之一實施例中，覆晶封裝製程更包括於晶片 承載器上形成多個銲球，其中銲球與晶片分別位於晶片承 ® 載器的二相對奉面。 為具體描述本發明之内容，在此提出—種覆晶封裝製 程。首先，提供一晶片，晶片具有一主動表面以及多個位 於主動表面上的焊墊。接著，於晶片之焊塾上形成多個凸 塊。然後，於一晶片承載器上形成一擋牆。之後，於擋牆 所圍出的一區塊内的晶片承載器上形成—非導電膠體。然 後，令晶片透過凸塊與晶片承載器電性連接，以使非導電 膠體包覆凸塊’且擋牆位於被非導電膠體包覆的凸塊周邊。 200941651 ID-200708004 26543twf.doc/n 在本發明之一實施例中’擋牆之材質包括二階段熱固 性膠體’而令晶片與晶片承载器電性連接的方法可以是先 部分固化二階段熱固性膠體’以使二階段熱固性膠體$ B階膠體。接著，翻轉晶片，以使晶片透過凸塊與晶^承 載器電性連接。然後’固化B階膠體與非導電膠體，使曰 片黏著於晶片承載器上。 y BaIt is disposed in the central region f of the active surface 124 of the wafer 120. The encapsulant 140 is disposed between the wafer 120 and the wafer carrier 11A and covers the bumps 130. In the prior art, when the material of the encapsulant 140 is a liquid glue, the method for fabricating the flip chip package 100 is The wafer 120 is bonded to the wafer carrier 11 and then applied in a dispensing manner to the periphery of the wafer 12 and is wicked to flow between the wafer 120 and the wafer carrier n〇. However, in this way, the wafer 12 is first fixed to the wafer carrier 11 to fill the encapsulant 14G, and the bump 13G is disposed in the central region F of the active surface 124 of the wafer 12Q, so the wafer 12 is folded. It is easy to have a tilting problem when it is bonded to the wafer carrier. In addition, the encapsulant (10) needs to be filled between the wafer 120 and the wafer carrier 11 (e.g.), so that the encapsulant is just too short because it is difficult to fill the wafer m and the wafer carrier 11 (pores) and takes a long time. ϋ Then, as the industry continues to develop materials and processes, N〇n-c〇nductive paste (NCP) can also be used as 140. When the material of the encapsulant 140 is a non-conductive colloid, the method of fabricating the flip-chip package 200941651 iu-ζνν /u6〇04 26543twf.doc/n structure 100 may be first coating the encapsulant 140 on the wafer carrier no, and then The wafer 120 is disposed on the wafer carrier H0 to connect the bumps 130 to the wafer carrier. However, this method is liable to cause the wafer 120 to be tilted due to the unevenness of the surface of the encapsulant 140, and the sealing body 14 is liable to overflow and create voids. SUMMARY OF THE INVENTION The present invention provides a flip chip package structure that avoids the problem that the conventional wafer is easily tilted, the non-conductive colloid is easily overflowed, and bubbles are generated or the liquid glue is not easily filled. The present invention further provides a flip chip packaging process that allows the wafer to be supported without tilting when the wafer is bonded to the wafer carrier, and prevents non-conductive colloid from overflowing. To specifically describe the present invention, a flip chip package structure is provided herein comprising a wafer carrier, a wafer, a plurality of bumps, a non-conductive colloid ❹ (n〇n-conductWe paste), and a retaining wall. The wafer carrier has a plurality of first contacts. The wafer has an active surface and a plurality of pads on the active surface, wherein the pads are disposed in a central region of the active surface. The bumps are disposed on the pads to electrically connect the first contacts to the pads. A non-conductive paste f is disposed between the wafer and the wafer carrier to cover the bumps. The retaining wall is disposed between the beta die and the wafer carrier and is located adjacent the bump of the non-conductive colloid and the retaining wall is in contact with a portion of the active surface. In an embodiment of the invention, the wafer carrier comprises a flexible circuit board. 200941651 ΐυ-2ϋϋ/ϋ8〇04 26543twf.doc/n In one embodiment of the invention, the flexible circuit board is made of polyimide (PI), polyester terephthalate (PET), Made of polyether oxime imineimide (PEI) or paper. In one embodiment of the invention, the flexible circuit board has a plurality of copper ruthenium leads' and these first contacts are the ends of the copper foil leads. In an embodiment of the invention, the bump comprises a plurality of gold bumps, a plurality of copper bumps or a plurality of tin-lead bumps. In one embodiment of the invention, the bump comprises a plurality of junction bumps or a plurality of plated bumps. In one embodiment of the invention, the retaining wall includes a plurality of strip-shaped barrier patterns' and the edges of each strip-shaped barrier pattern are aligned with the edges of the wafer. In one embodiment of the invention, the retaining wall includes an annular barrier pattern and the outer edge of the annular barrier pattern is aligned with the edge of the wafer. In one embodiment of the invention, the material of the retaining wall comprises a two-stage thermoset colloid or solder resist material. ... In an embodiment of the invention, the non-conductive colloid is connected to the retaining wall. In one embodiment of the invention, the wafer carrier has a plurality of second contacts, and the first contacts and the second contacts are respectively located on opposite surfaces of the wafer carrier and are electrically connected. In an embodiment of the invention, the flip chip package further includes a plurality of solder balls, and the solder balls are electrically connected to the second contacts. To specifically describe the present invention, a flip chip package is proposed herein. First, a wafer is provided having an active surface and a plurality of pads on the active surface. Next, a plurality of bumps 200941651 ID-200708004 26543twf.doc/n blocks are formed on the solder fillets of the wafer. Then, a retaining wall is formed on the active surface, and the retaining wall avoids a block forming area to surround a block. Thereafter, a non-conductive colloid is formed on the active surface within the block to cover the bump. Then, the wafer is electrically connected to a wafer carrier through the bumps. In an embodiment of the invention, the material of the wall comprises a two-stage thermosetting knee body, and the method of electrically connecting the wafer to the wafer carrier may be to partially cure the two-stage thermosetting colloid to form a two-stage thermosetting colloid. B-stage colloid. The wafer is then flipped so that the wafer is electrically connected to the wafer carrier through the bumps. Thereafter, the B-stage colloid and the non-conductive colloid are cured to adhere the wafer to the wafer carrier. In an embodiment of the invention, the material of the retaining wall includes a solder resist material, and the method of electrically connecting the wafer to the wafer carrier may be to first flip the wafer to electrically connect the wafer to the wafer carrier through the bump. The non-conductive colloid is then cured to adhere the wafer to the wafer carrier. In an embodiment of the invention, the flip chip packaging process further includes forming a plurality of solder balls on the wafer carrier, wherein the solder balls and the wafers are respectively located on opposite sides of the wafer carrier. To specifically describe the contents of the present invention, a flip chip packaging process is proposed herein. First, a wafer is provided having an active surface and a plurality of pads on the active surface. Next, a plurality of bumps are formed on the pad of the wafer. Then, a retaining wall is formed on a wafer carrier. Thereafter, a non-conductive colloid is formed on the wafer carrier in a block enclosed by the retaining wall. Then, the wafer is electrically connected to the wafer carrier through the bumps so that the non-conductive colloid covers the bumps' and the retaining walls are located around the bumps covered by the non-conductive colloid. 200941651 ID-200708004 26543twf.doc/n In one embodiment of the present invention, the material of the retaining wall includes a two-stage thermosetting colloid, and the method of electrically connecting the wafer to the wafer carrier may be a partial curing of the two-stage thermosetting colloid. To make a two-stage thermoset colloid $B-order colloid. Next, the wafer is flipped so that the wafer is electrically connected to the crystal carrier through the bump. The B-stage colloid and the non-conductive colloid are then cured to adhere the crucible to the wafer carrier. y Ba
φ 在本發明之一實施例中，擋牆之材質包括防焊材料， 而令晶片與晶片承載器電性連接的方法可以是先翻轉曰 片，以使晶片透過凸塊與晶片承载器電性連接。然後，= 化非導電膠體以使晶片黏著於晶片承载器上。、 在本發明之-實施例中，覆晶封裳製程更包括於晶片 承載器上形成多_球’而且銲球與晶片分別位於晶 載器的二相對表面。 综上所述，本發明之覆晶封裝結構的播牆配置於晶片 與B曰片承載器之間且位於凸塊周邊。因曰 片使晶片在晶片承載器上保持平衡，以避免 覆晶封裝結構的晶片因非導電賴表面不平㈣易於傾斜 = 擋牆還可防止非導電膠體溢流及減少非導 電膠體產生氣泡。 【實施方式】 200941651 1U-200VU8〇04 26543twf.doc/n 圖2為本發明一實施例之覆晶封裝結構的剖面示意 圖。請參照圖2 ’本實施例之覆晶封裝結構2〇〇包括一晶 片承載器210、一晶片220、多個凸塊230 (於圖2中僅繪 示一個凸塊230做為代表）、一非導電膠體240以及一擒 踏250。其中，晶片承載器21〇具有多個第一接點212a(於 圖2中僅繪示一個第一接點212a做為代表）。而於本實施 例中，第一接點212a例如是晶片承載器210所具有的多條 ❹ 銅箔引線212 (於圖2中僅繪示一條銅箔引線212做為代 表）的端部。此外，晶片承載器210例如是一可撓性電路 板，而且可撓性電路板例如是由聚酿亞胺、聚酯類化合物、 聚醚醯亞胺或紙所製成，也就是說，可撓性電路板除了銅 4引線212以外的部分例如是由聚酿亞胺所製成。 晶片220具有一主動表面222以及多個位於主動表面 222上的焊墊224 (於圖2中僅繪示一個焊墊224做為代 表）。而且，焊墊224配置於主動表面222的一中心區域 F内，亦即本實施例之焊墊224為中心焊墊。此外，焊墊 224可以排列成單排或多排，而於本實施例中，焊墊224 是以單排的方式排列，但並非用以限定本發明。此外，凸 塊230配置於晶片22〇的焊墊224上以使第一接點21% 與，墊224電性連接。也就是說，凸塊230配置於晶片220 與曰曰片承載器210之間’且電性連接第一接點212a與焊墊 224其中，就凸塊230的材質而言，凸塊23〇例如是金凸 塊、銅凸塊、或錫鉛凸塊、或是以其他適當的材質所形成 的凸塊。此外，凸塊230例如是藉由焊線機（wireb〇nder) 11 200941651 ιυ-^υυ/υκ〇〇4 26543twf.doc/n 所形成之結線凸塊（stud bumps)、藉由電鍍製程所形成 之電鍍凸塊（plating bumps)或是藉由印刷方式所形成之 焊料凸塊（solder bumps )。 非導電膠體240配置於晶片220與晶片承載器21〇之 間以包覆凸塊230。擋牆250配置於晶片220與晶片承載 器210之間，並位於被非導電膠體240包覆的凸塊230周 邊’且擋牆250與主動表面222的部分區域接觸。詳細而 ❹ 言’擋牆250圍繞凸塊230與非導電膠體240，且非導電 膠體240配置於凸塊230與檔牆250之間。於本實施例中， 非導電膠體240與擋牆250連接。 承上所述，由於擋牆250配置於晶片220與晶片承載 器210之間且位於凸塊230周邊，因此擋牆250可支撐晶 片220,以使晶片220與晶片承載器210之間的間距（gap) 維持固定。換句話說，擋牆25〇有助於使晶片22〇在晶片 承載益210上保持平衡，以避免習知的覆晶封裝結構 ❹ （請參照圖1)的晶片120因受封膠體140的表面不平坦 影響而易於傾斜的問題。而且，擋牆250還可防止非導電 膠體240溢流及減少非導電膠體240產生氣泡的問題。此 外，由於擋牆250配置於晶片220與晶片承載器21〇之間， 且擋牆250與主動表面222的部分區域接觸，因此擋牆25〇 可提升晶片220與晶片承載器210之間接合的可靠度。 此外’於本實施例中，擋牆250可以是多個條狀阻擋 圖案’且各條狀阻擋圖案的邊緣與晶片22〇的邊緣226切 齊。此外’各條狀阻擋圖案也可以是僅位於晶片220與晶 12 200941651 ij-/-zuu/v〇004 26543twf.doc/n 片承载器210之間，或者是晶片220覆蓋各條狀阻擋圖案。 另外，擋牆250也可以是一環狀阻擋圖案，且環狀阻擋圖 案的外緣與晶片220的邊緣226切齊。此外，環狀阻擋圖 案也可以是僅位於晶片220與晶片承載器210之間，或者 是晶片220覆蓋環狀阻擋圖案。 另外，擋牆250的材質例如是二階段熱固性膠體 (two-stage adhesive)或防焊材料（s〇ider resist material) 〇In one embodiment of the present invention, the material of the retaining wall includes a solder resist material, and the method of electrically connecting the wafer to the wafer carrier may be to first flip the wafer to make the wafer pass through the bump and the wafer carrier. connection. Then, the non-conductive colloid is applied to adhere the wafer to the wafer carrier. In the embodiment of the present invention, the flip chip process further includes forming a plurality of balls on the wafer carrier and the solder balls and the wafers are respectively located on opposite surfaces of the carrier. In summary, the broadcast wall of the flip chip package structure of the present invention is disposed between the wafer and the B-chip carrier and located at the periphery of the bump. Because the wafer balances the wafer on the wafer carrier, the wafer of the flip-chip package structure is prevented from being tilted due to non-conductive surface unevenness (4). The retaining wall also prevents non-conductive colloid overflow and reduces bubbles generated by the non-conductive colloid. [Embodiment] 200941651 1U-200VU8〇04 26543twf.doc/n FIG. 2 is a schematic cross-sectional view showing a flip chip package structure according to an embodiment of the present invention. Referring to FIG. 2, the flip chip package structure 2 of the present embodiment includes a wafer carrier 210, a wafer 220, and a plurality of bumps 230 (only one bump 230 is shown in FIG. 2). The non-conductive colloid 240 and a step 250. The wafer carrier 21A has a plurality of first contacts 212a (only one first contact 212a is shown in FIG. 2). In the present embodiment, the first contact 212a is, for example, the end of a plurality of bismuth copper foil leads 212 (only one copper foil lead 212 is shown in FIG. 2) of the wafer carrier 210. In addition, the wafer carrier 210 is, for example, a flexible circuit board, and the flexible circuit board is made of, for example, a polyimide, a polyester compound, a polyether phthalimide or paper, that is, The portion of the flexible circuit board other than the copper 4 lead 212 is, for example, made of polyimide. The wafer 220 has an active surface 222 and a plurality of pads 224 on the active surface 222 (only one pad 224 is shown in Figure 2). Moreover, the pad 224 is disposed in a central region F of the active surface 222, that is, the pad 224 of the embodiment is a center pad. In addition, the pads 224 may be arranged in a single row or in multiple rows. In the present embodiment, the pads 224 are arranged in a single row, but are not intended to limit the invention. In addition, the bumps 230 are disposed on the pads 224 of the wafer 22 to electrically connect the first contacts 21% to the pads 224. That is, the bumps 230 are disposed between the wafer 220 and the die carrier 210 and are electrically connected to the first contacts 212a and the pads 224. For the material of the bumps 230, for example, the bumps 23 are, for example. It is a gold bump, a copper bump, or a tin-lead bump, or a bump formed of other suitable materials. In addition, the bumps 230 are formed by, for example, electroplating processes by wire bond bumps formed by wire bond 11 ) 2009 2009 2009 2009 2009 2009 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 Plating bumps or solder bumps formed by printing. The non-conductive colloid 240 is disposed between the wafer 220 and the wafer carrier 21A to cover the bumps 230. The retaining wall 250 is disposed between the wafer 220 and the wafer carrier 210 and is located adjacent the bump 230 of the non-conductive colloid 240 and the retaining wall 250 is in contact with a portion of the active surface 222. In detail, the retaining wall 250 surrounds the bump 230 and the non-conductive colloid 240, and the non-conductive colloid 240 is disposed between the bump 230 and the barrier 250. In the embodiment, the non-conductive colloid 240 is connected to the retaining wall 250. As described above, since the retaining wall 250 is disposed between the wafer 220 and the wafer carrier 210 and at the periphery of the bump 230, the retaining wall 250 can support the wafer 220 to distance the wafer 220 from the wafer carrier 210 ( Gap) Maintain fixed. In other words, the retaining wall 25〇 helps balance the wafer 22 on the wafer carrier 210 to avoid the wafer flipping of the conventional flip chip package structure (see FIG. 1) due to the surface of the encapsulant 140. A problem that is easy to tilt due to unevenness. Moreover, the retaining wall 250 also prevents the non-conductive colloid 240 from overflowing and reduces the problem of bubbles generated by the non-conductive colloid 240. In addition, since the retaining wall 250 is disposed between the wafer 220 and the wafer carrier 21A, and the retaining wall 250 is in contact with a partial region of the active surface 222, the retaining wall 25 can lift the bonding between the wafer 220 and the wafer carrier 210. Reliability. Further, in the present embodiment, the retaining wall 250 may be a plurality of strip-shaped barrier patterns' and the edges of the strip-shaped barrier patterns are aligned with the edges 226 of the wafer 22''. Further, each of the strip-shaped barrier patterns may be located only between the wafer 220 and the wafer 12 200941651 ij-/-zuu/v〇004 26543 twf.doc/n wafer carrier 210, or the wafer 220 may cover the strip-shaped barrier patterns. Alternatively, the retaining wall 250 can be an annular barrier pattern and the outer edge of the annular barrier pattern is aligned with the edge 226 of the wafer 220. Alternatively, the annular barrier pattern may be located only between the wafer 220 and the wafer carrier 210, or the wafer 220 may cover the annular barrier pattern. In addition, the material of the retaining wall 250 is, for example, a two-stage adhesive or a s〇ider resist material.
❹ 其中，二階段熱固性膠體包括溶劑型二階段熱固性膠體 (sol vent type two-stage adhesive )及無溶劑型二階段熱固 膠體（non-solvent type two-stage adhesive)。二階段熱 固性膠體的材質包括聚醯亞胺、苯並環丁烯 (benzocyclobutene)、或是其他適合的二階段熱固性膠 材料。此外，防焊材料例如是樹脂或是其他適合的絕緣 料。 此外，於本實施例中，晶片承載器21〇可具有多個第 二接點214 ’而且第一接點2仏與第二接點214分別位於 晶片承載器210的二相對表面上並對應電性連接。另外， 覆晶封裝結構綱還包括多個銲球施，且銲球細 mi4=連接。銲球260適於電性連接第二接點別 與一電子兀件（例如電路板）。 圖jA至圖3D繪不本發明一實施例之 =面圖私首先，請參照圖3A，提供—晶片31〇，=裝片= 以及多個位於主動表面上的谭㈣4 (於本實施例中歸示—個焊墊314做為代表）。這些焊 13 200941651 ΐυ-2υυ/υ8〇04 26543twf.doc/n 墊314例如是配置於主動表面312的—中心區域，這 些焊墊314可以排列成單排或多排，而於本實施例中，焊 是以單排的方式排列，但並非用以限定本發明。接 著，於晶片310之焊墊314上形成多個凸塊32〇 (於本實 施例中僅繪示一個凸塊320做為代表），也就是說這些凸 塊320也配置於主動表面312的一中心區域F内。形成凸 塊320的方式例如是電鍍、印刷或是打線形成。 ❿ 然後，請參照圖3B，於主動表面312上形成一擋牆 330，擋牆330避開凸塊320形成區域A圍出一區塊B ^ 也就是說，擋牆330圍繞凸塊320且擋牆330與凸塊320 之間有一間距。當擋牆330的材質為二階段熱固性膠體 時，形成擋牆330的方法包括印刷 '塗佈（c〇ating)、壓 印（printing)、喷霧（spraying)、旋轉塗佈（spin_c〇ating) 或浸沾（dipping)等的方式。當撐牆33〇的材質為防焊材 料時，形成擋牆330的方法包括貼附乾膜（dry film)或塗 佈絕緣材料。 之後’請參照圖3C，於區塊B内的主動表面312上 升>成一非導電膠體（non_con(juctivepaste) 340，以包覆凸 塊320。詳細而言，非導電膠體34〇包覆凸塊32〇的側面 322並暴露出凸塊32〇之遠離晶片310的一表面324。形成 非導電膠體340的方法包括塗佈。之後’請參照圖3D，令 晶片310透過凸塊320與一晶片承載器350電性連接。此 外’於本實施例中’還可以在晶片承載器350上形成多個 銲球360，而且銲球360與晶片310分別位於晶片承載器 200941651 ID-200708004 26543twf.doc/n 350的二相對表面。 承上所述’由於本實施例在形成非導電膠體340之前 先形成擋牆330，因此擋牆330可防止非導電膠體340溢 流。此外，當晶片310透過凸塊320與晶片承载器350電 性連接時，擋牆330可支撐晶片310，使晶片310與晶片 承載基板350之間的間距維持固定。因此，擋牆330可使 晶片310在晶片承載器350上保持平衡。 φ 於本實施例中，當擋牆330的材質為二階段熱固性膠 體時，令晶片310與晶片承載器350電性連接的方法可以 是如下所述。首先，請參照圖3C，部分固化（partial cure) 二階段熱固性膠體，以使二階段熱固性膠體形成B階膠 體。也就是說，先部分固化二階段熱固性膠體，以使二階 段熱固性膠體預先形成半固化膠態，較佳地，二階段熱固 性膠體於半固化膠態時具有黏性。然後，請參照圖3D，翻 轉晶片310,以使晶片310透過凸塊320與晶片承載器350 電性連接。之後，固化（Post cure) B階膠體與非導電膠 ® 體340以使晶片310黏著於晶片承載器350上。當二階段 熱固性膠體經部分固化形成具有黏性的半固化膠態時，更 有助於使晶片310黏著於晶片承載器350上。 於本實施例中’當擋膽的材質為防焊材料時，令 晶片310與晶片承載器350電性連接的方法如下所述。首 先，請參照圖3D，可先翻轉晶片310 ’以使晶片310透過 凸塊320與晶片承載器350電性連接。然後，固化非導電 膠體340，使晶片31〇黏著於晶片承載器350上。 15 200941651 ιυ-/υυ /υδ004 26543twf.doc/n 圖4Α至圖4D繪示本發明另—實施例之覆晶封裝製 程的剖面圖。首先，請參照圖4A，提供一晶片41〇，晶片 410具有一主動表面412以及多個位於主動表面412上的 焊墊414(於本實施例中僅繪示一個诨墊414做為代表）。 這些焊塾414例如是配置於主動表面412 #一中心區域F 内，這些焊#414可以排列成單排或多排，而於本實施例 中，焊墊414是以單排的方式排列，但並非用以限定本發 Ο 明。接著，於晶片410之焊墊414上形成多個凸塊42〇(於 本實施例中僅繪示一個凸塊420做為代表），也就是說這 些凸塊420也配置於主動表面412的一中心區域F内。 然後，請參照圖4B，於一晶片承載器43〇上形成一 擋牆440。當擋牆440的材質為二階段熱固性膠體時，形 成擋牆440的方法包括印刷、塗佈、壓印（printing)、喷 霧（spraying)、旋轉塗佈或浸沾⑽pping) 等的方式。當擋牆440的材質為防焊材料時，形成擋牆440 的方法包括貼附乾膜或塗佈絕緣材料。 ® 之後，請參照圖4C ’於擋牆440所圍出的一區塊c 内的晶片承載器430上形成一非導電膠體450。形成非導 電膠體450的方法包括塗佈。然後，請參照圖4D，令晶片 410透過凸塊420而與晶片承載器430電性連接，以使非 導電膠體450包覆凸塊420。而且，擋牆440位於被非導 電膠體450包覆的凸塊420周邊。此外，於本實施例中， 還可以在晶片承載器430上形成多個銲球460，而且鮮球 460與晶片410分別位於晶片承載器430的二相對表面。 16 200941651 χι;-2υυ/υδ004 26543twf.doc/n 於本實施例中，當擋牆440的材質為二階段熱固性膠 體時，使晶片410與晶片承載器430電性連接方式可為如 下所述。首先，請參照圖4C，部分固化二階段熱固性膠體， 以使二階段熱固性膠體形成B階膠體。也就是說，先藉由 部分固化二階段熱固性膠體，以使二階段熱固性膠體預先 形成半固化膠態，較佳地，二階段熱固性膠體於半固化膠 態時具有黏性。接著，請參照圖4D，翻轉晶片410，以使 晶片410透過凸塊420而與晶片承載器430電性連接。然 後’固化B階膠體與非導電膠體450，以使晶片410黏著 於晶片承載器430上。 此外，於本實施例中，當擋牆440的材質為防焊材料 時’使晶片410與晶片承載器430電性連接的方法可為如 下所述。首先，請參照圖4D，翻轉晶片410,以使晶片41〇 透過凸塊420而與晶片承載器430電性連接。然後，固化 非導電膠體450以使晶片410黏著於晶片承載器“ο上。 矣τ'上所述，本發明之覆晶封装結構的擋牆配置於晶片 與曰曰片承載器之間且位於凸塊周邊。因此，擔牆可支撐晶 片，以使晶片與晶片承載器之間的間距維持固定並有助於 使晶片在晶片承載器上保持平衡，以避免習知技術中的覆 晶封裝結構的晶片因非導電膠體表面不平坦而易於傾斜的 問題。而且’擋祕可防止非導電膠體溢流及減少非導電 膠體產生氣泡。此外，由於擋牆配置於晶片與晶片承載器 ^間，且簡與主動表面的部分_接觸，@此擋牆還可 k升晶片與晶片承載器之間接合的可靠度。 17 200941651 ιυ-ζυυ/υδ004 26543twf.doc/n 明^實施例揭露如上，然其雌用以限定 曰^接^所領域中具有通常知識者，在不脫離本發 :之=範圍内，當可作些許之更動與潤飾， 明之保護_當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖 圖1繪示習知之具有中心焊墊的覆晶封裝結構的剖面 Φ 圖 示意 圖2為本發明—實施狀覆晶封裝結構的剖面 圖3Α至圖3D緣示本發明一實施例之覆晶 的剖面圖。 衣牲 圖4Α至目4D緣示本發明另一實施例之覆晶封 程的剖面圖。 & 【主要元件符號說明】 ❿ 100、2〇〇 :覆晶封裝結構 110、210、350、430 :晶片承载器 120、220、310、410 :晶片 122 :中心焊墊 124、222'312、412 :主動表面 130、230、320、420 :凸塊 140 =封膠體 240、340、450 :非導電膠體 18 200941651 ιυ-ζυυ/υδ004 26543twf.doc/n 212 :銅箔引線 212a :第一接點 214 :第二接點 224、314、414 :焊墊 226 .邊緣 250、330、440 :擋牆 260、360、460 :銲球 322 :側面 324 :表面 A .區域 B、C:區塊 F :中心區域 ❹ 19❹ Among them, the two-stage thermosetting colloid includes a solvent-type two-stage adhesive and a non-solvent type two-stage adhesive. The two-stage thermoset colloids include polyimine, benzocyclobutene, or other suitable two-stage thermoset materials. Further, the solder resist material is, for example, a resin or other suitable insulating material. In addition, in this embodiment, the wafer carrier 21A may have a plurality of second contacts 214' and the first contacts 2'' and the second contacts 214 are respectively located on opposite surfaces of the wafer carrier 210 and correspond to electricity. Sexual connection. In addition, the flip chip package structure also includes a plurality of solder balls, and the solder balls are fine mi4=connected. The solder balls 260 are adapted to electrically connect the second contacts to an electronic component (e.g., a circuit board). FIG. 3A to FIG. 3D illustrate an embodiment of the present invention. First, referring to FIG. 3A, a wafer 31〇, a mounting sheet, and a plurality of Tans (4) 4 on the active surface are provided. Representation - a pad 314 as a representative). These solders 13 200941651 ΐυ-2υυ/υ8〇04 26543twf.doc/n pads 314 are, for example, disposed in a central region of the active surface 312, and the pads 314 may be arranged in a single row or in multiple rows, and in this embodiment, The welding is arranged in a single row, but is not intended to limit the invention. Then, a plurality of bumps 32 〇 are formed on the pads 314 of the wafer 310 (only one bump 320 is shown in the embodiment), that is, the bumps 320 are also disposed on the active surface 312. In the center area F. The manner in which the bumps 320 are formed is, for example, electroplating, printing, or wire bonding. ❿ Then, referring to FIG. 3B, a retaining wall 330 is formed on the active surface 312. The retaining wall 330 avoids the bump 320 forming region A to enclose a block B. That is, the retaining wall 330 surrounds the bump 320 and blocks There is a gap between the wall 330 and the bump 320. When the material of the retaining wall 330 is a two-stage thermosetting colloid, the method of forming the retaining wall 330 includes printing 'c〇ating, printing, spraying, spin-c〇ating. Or dipping or the like. When the material of the support wall 33 is a solder resist material, the method of forming the retaining wall 330 includes attaching a dry film or coating an insulating material. Then, please refer to FIG. 3C, the active surface 312 in the block B rises > a non-conducting colloid (non_con (juctive paste) 340 to cover the bump 320. In detail, the non-conductive colloid 34 〇 covers the bump The 32 sided side 322 exposes a surface 32 of the bump 32 away from the wafer 310. The method of forming the non-conductive colloid 340 includes coating. Thereafter, referring to FIG. 3D, the wafer 310 is carried through the bump 320 and a wafer. The device 350 is electrically connected. Further, in the present embodiment, a plurality of solder balls 360 may be formed on the wafer carrier 350, and the solder balls 360 and the wafer 310 are respectively located on the wafer carrier 200941651 ID-200708004 26543twf.doc/n The two opposing surfaces of the 350. According to the present embodiment, the retaining wall 330 is formed before the non-conductive colloid 340 is formed, so that the retaining wall 330 can prevent the non-conductive colloid 340 from overflowing. Further, when the wafer 310 passes through the bump 320 When electrically coupled to the wafer carrier 350, the retaining wall 330 can support the wafer 310 to maintain a constant spacing between the wafer 310 and the wafer carrier substrate 350. Thus, the retaining wall 330 can maintain the wafer 310 on the wafer carrier 350. φ In this embodiment, when the material of the retaining wall 330 is a two-stage thermosetting colloid, the method of electrically connecting the wafer 310 to the wafer carrier 350 may be as follows. First, please refer to FIG. 3C, partial curing (partial Curing a two-stage thermosetting colloid to form a second-stage thermosetting colloid to form a B-stage colloid. That is, the two-stage thermosetting colloid is partially cured to pre-form a two-stage thermosetting colloid into a semi-cured colloid, preferably a two-stage thermosetting The colloid is viscous in a semi-cured colloidal state. Then, referring to FIG. 3D, the wafer 310 is flipped so that the wafer 310 is electrically connected to the wafer carrier 350 through the bump 320. Thereafter, the post-cured B-stage colloid is The non-conductive adhesive body 340 is used to adhere the wafer 310 to the wafer carrier 350. When the two-stage thermosetting colloid is partially cured to form a viscous semi-cured colloid, it helps to adhere the wafer 310 to the wafer carrier 350. In the present embodiment, when the material of the rib cage is a solder resist material, the method of electrically connecting the wafer 310 to the wafer carrier 350 is as follows. First, please refer to 3D, the wafer 310' may be flipped first to electrically connect the wafer 310 to the wafer carrier 350 through the bumps 320. Then, the non-conductive paste 340 is cured to adhere the wafer 31 to the wafer carrier 350. 15 200941651 ιυ-/ Υυ /υδ004 26543twf.doc/n FIG. 4A to FIG. 4D are cross-sectional views showing a flip chip packaging process according to another embodiment of the present invention. First, referring to FIG. 4A, a wafer 41 is provided, and the wafer 410 has an active surface 412. And a plurality of pads 414 on the active surface 412 (only one pad 414 is shown in the present embodiment). The solder bumps 414 are disposed, for example, in the active surface 412 # a central region F. The solder bumps 414 may be arranged in a single row or multiple rows. In the embodiment, the solder pads 414 are arranged in a single row, but It is not intended to limit the present invention. Then, a plurality of bumps 42 are formed on the pads 414 of the wafer 410 (only one bump 420 is shown in the embodiment), that is, the bumps 420 are also disposed on the active surface 412. In the center area F. Then, referring to Fig. 4B, a retaining wall 440 is formed on a wafer carrier 43. When the material of the retaining wall 440 is a two-stage thermosetting colloid, the method of forming the retaining wall 440 includes printing, coating, printing, spraying, spin coating or dipping (10) pping. When the material of the retaining wall 440 is a solder resist material, the method of forming the retaining wall 440 includes attaching a dry film or coating an insulating material. After that, a non-conductive colloid 450 is formed on the wafer carrier 430 in a block c surrounded by the retaining wall 440 with reference to FIG. 4C'. A method of forming the non-conductive colloid 450 includes coating. Then, referring to FIG. 4D, the wafer 410 is electrically connected to the wafer carrier 430 through the bumps 420, so that the non-conductive colloid 450 covers the bumps 420. Moreover, the retaining wall 440 is located around the periphery of the bump 420 that is covered by the non-conductive gel 450. Moreover, in the present embodiment, a plurality of solder balls 460 may also be formed on the wafer carrier 430, and the fresh balls 460 and the wafers 410 are respectively located on opposite surfaces of the wafer carrier 430. 16 200941651 χι;-2υυ/υδ004 26543twf.doc/n In this embodiment, when the material of the retaining wall 440 is a two-stage thermosetting gel, the method of electrically connecting the wafer 410 to the wafer carrier 430 can be as follows. First, referring to Figure 4C, the two-stage thermosetting colloid is partially cured to form a two-stage thermosetting colloid to form a B-stage colloid. That is, the two-stage thermosetting colloid is preliminarily formed into a semi-cured colloid by partially curing the two-stage thermosetting colloid. Preferably, the two-stage thermosetting colloid is viscous in the semi-cured colloid. Next, referring to FIG. 4D, the wafer 410 is flipped so that the wafer 410 is electrically connected to the wafer carrier 430 through the bumps 420. The B-stage colloid and the non-conductive colloid 450 are then cured to adhere the wafer 410 to the wafer carrier 430. In addition, in the embodiment, when the material of the retaining wall 440 is made of solder resist material, the method of electrically connecting the wafer 410 to the wafer carrier 430 may be as follows. First, referring to FIG. 4D, the wafer 410 is flipped so that the wafer 41 is electrically connected to the wafer carrier 430 through the bumps 420. Then, the non-conductive colloid 450 is cured to adhere the wafer 410 to the wafer carrier. The ferrule of the flip-chip package structure of the present invention is disposed between the wafer and the cymbal carrier and is located The periphery of the bump. Thus, the support wall can support the wafer to maintain a constant spacing between the wafer and the wafer carrier and to help balance the wafer on the wafer carrier to avoid flip-chip packages in the prior art. The wafer is easy to tilt due to the uneven surface of the non-conductive colloid, and the 'blocking prevents the non-conductive colloid from overflowing and reduces the bubble generated by the non-conductive colloid. Further, since the retaining wall is disposed between the wafer and the wafer carrier, The contact with the active surface is _ contact, @ this retaining wall can also be the reliability of the joint between the wafer and the wafer carrier. 17 200941651 ιυ-ζυυ/υδ004 26543twf.doc/n The embodiment is disclosed above, but The female is used to define the general knowledge in the field of 曰^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1] FIG. 1 is a cross-sectional view of a conventional flip-chip package structure having a center pad. FIG. 2 is a cross-sectional view of the flip-chip package structure of the present invention. FIG. A cross-sectional view of a flip chip according to an embodiment of the present invention. A cross-sectional view of a flip chip sealing process according to another embodiment of the present invention is shown in FIG. 4A to FIG. 4D. & [Major component symbol description] ❿ 100, 2 〇〇: flip chip package structure 110, 210, 350, 430: wafer carrier 120, 220, 310, 410: wafer 122: center pad 124, 222 '312, 412: active surface 130, 230, 320, 420: Bump 140 = encapsulant 240, 340, 450: non-conductive colloid 18 200941651 ιυ-ζυυ/υδ004 26543twf.doc/n 212: copper foil lead 212a: first contact 214: second contact 224, 314, 414: Solder pad 226. Edges 250, 330, 440: Retaining walls 260, 360, 460: Solder balls 322: Side 324: Surface A. Area B, C: Block F: Center area ❹ 19