CN111987048A - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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Publication number
CN111987048A
CN111987048A CN201910476232.7A CN201910476232A CN111987048A CN 111987048 A CN111987048 A CN 111987048A CN 201910476232 A CN201910476232 A CN 201910476232A CN 111987048 A CN111987048 A CN 111987048A
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CN
China
Prior art keywords
conductive
layer
electronic
package
electronic package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910476232.7A
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Chinese (zh)
Inventor
陈汉宏
林荣政
余国华
林长甫
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN111987048A publication Critical patent/CN111987048A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

An electronic package and its manufacturing method, including setting up electronic component and multiple conducting posts on a bearing structure, and should lead the perimeteric surface of the post to form the isolating layer, and then wrap up the electronic component, lead post and isolating layer with the packaging layer, in order to plant and set up the solder ball on the post in this and lead, make the solder material not extend to should lead the perimeteric surface of post along with the scaling powder that the operation uses of planting, avoid the solder ball of two adjacent places from taking place the problem of bridging.

Description

Electronic package and manufacturing method thereof
Technical Field
The present invention relates to a semiconductor packaging process, and more particularly, to an electronic package and a method for fabricating the same.
Background
With the rapid development of portable electronic products in recent years, the development of various related products is also developing towards high density, high performance, and light, thin, short, and small trends, and the semiconductor package structure of each embodiment is also developed to meet the requirements of light, thin, short, and high density.
In order to match the trend of thinning products, the chips are increasingly worn and thinner, so the strength and reliability of the chips are also tested. At present, after thinning the chip, a mold protection method is adopted, but for a semiconductor package with high contact (I/O) number and relatively small size, a conductive element to be electrically connected to the outside is formed by using a slender copper pillar to replace a solder ball, so as to avoid the problem of bridging caused by too small distance.
As shown in fig. 1, in a conventional semiconductor package 1, a plurality of copper pillars 13 are formed on a lower side of a substrate 10 by electroplating, semiconductor devices 11,12 are disposed on upper and lower sides of the substrate 10, then a molding compound (molding compound)15 is used to encapsulate the semiconductor devices 11,12 and the copper pillars 13, the copper pillars 13 of the substrate 10 are exposed from the molding compound 15, and a plurality of solder balls 17 are formed on exposed surfaces of the copper pillars 13, so that the semiconductor package 1 can be mounted on an electronic device such as a circuit board through the solder balls 17.
However, in the conventional semiconductor package 1, after the copper pillar 13 is formed, the solder ball 17 needs to be planted, so that the solder material of the solder ball 17 easily extends (climbs up) to the copper pillar 13 along with the flux used in the planting operation, thereby causing bridging of the solder material (two adjacent solder balls 17), and after the solder climbing condition, the pad area of the solder ball 17 is increased, so that the height of the solder ball 17 cannot be controlled.
In addition, the plurality of copper pillars 13 formed on the substrate 10 by electroplating has a very high manufacturing cost, and is not in line with economic benefits.
Therefore, how to overcome the various problems of the prior art has become an issue to be solved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic package and a method for manufacturing the same, so as to avoid the problem of bridging between two adjacent solder balls.
The electronic package of the present invention includes: a load-bearing structure; at least one electronic element arranged on the bearing structure and electrically connected with the bearing structure; a plurality of conductive columns arranged on the bearing structure and electrically connected with the bearing structure; an isolation layer formed on the peripheral surface of each conductive column; and a packaging layer, which encapsulates the electronic element, the conductive post and the isolation layer.
The invention also provides a method for manufacturing the electronic packaging piece, which comprises the following steps: arranging a conductive frame and at least one electronic element on a bearing structure, wherein the conductive frame comprises a plate body and a plurality of conductive columns connected with the plate body, the conductive columns are combined on the bearing structure, and an isolating layer is formed on the peripheral surface of each conductive column; the electronic element, the conductive post and the isolation layer are coated by the packaging layer; and removing the plate body.
In an embodiment, the carrier structure has a first side and a second side opposite to the first side, so that the conductive pillar is bonded to the first side and/or the second side of the carrier structure, the electronic element is disposed on the first side and/or the second side, and the package layer is formed on the first side and/or the second side.
In the electronic package and the method for manufacturing the same, the encapsulation layer is exposed from a portion of the surface of the electronic component.
In the electronic package and the manufacturing method thereof, the conductive pillar is electrically connected to the supporting structure through a conductive body.
In the electronic package and the manufacturing method thereof, the end surface of the conductive pillar is exposed out of the surface of the package layer.
In an embodiment, the conductive pillar has an end surface flush with or lower than an outer surface of the package layer.
In the electronic package and the method for manufacturing the same, the isolation layer is further formed on the outer surface of the board body, so that when the board body is removed, the isolation layer on the surface of the board body is removed. Or, when the plate body is removed, the isolation layer is kept, so that the isolation layer is kept on the outer surface of the packaging layer.
In the electronic package and the method for manufacturing the same, a conductive element is formed on the end surface of the conductive pillar.
The electronic package and the method for manufacturing the same further include forming an alignment portion on a surface of the package layer. For example, the process of the alignment portion includes: forming a convex part on the conductive frame, and coating the convex part with the isolation layer; after removing the plate body, the convex part is exposed out of the packaging layer; and removing the convex part to form a concave part on the surface of the packaging layer, wherein the concave part is used as the contraposition part.
In view of the above, in the electronic package and the manufacturing method thereof of the present invention, the isolation layer mainly encapsulates the peripheral surface of the conductive pillar, so that during the ball-mounting operation, the solder material does not extend onto the peripheral surface of the conductive pillar along with the soldering flux used in the mounting operation, and therefore, compared with the prior art, the present invention can avoid the problem of bridging between the solder balls at two adjacent positions during the ball-mounting operation.
On the other hand, the electronic packaging part of the invention can avoid the problem of increasing the bonding pad area of the solder ball because the tin climbing condition can not occur, so the height of the solder ball can be effectively controlled.
In addition, the conductive frame is designed to place the conductive pillar on the carrying structure 20, so that compared with the prior art, the manufacturing cost of the manufacturing method of the invention is greatly reduced, thereby meeting the economic benefit.
Drawings
Fig. 1 is a cross-sectional view of a conventional semiconductor package.
Fig. 2A to 2E are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to a first embodiment of the invention.
FIG. 2A' is a schematic view of another embodiment of FIG. 2A.
Fig. 2D' and 2D ″ are schematic views of other different embodiments of fig. 2D.
Fig. 2E' is a schematic view of another embodiment of fig. 2E.
Fig. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to a second embodiment of the invention.
Description of the symbols
1 semiconductor package
10 base plate
11,12 semiconductor element
13 copper column
15 packaging colloid
17 solder ball
2, 2', 3 electronic package
2a conductive frame
20 load bearing structure
20a first side
20b second side
200 circuit layer
201 insulating layer
21 first electronic component
21a action surface
21b non-active surface
210 electrode pad
211,220 conductive bump
22 second electronic component
23 conductive post
23a,23 a' end face
23c peripheral surface
230 electric conductor
24 plate body
25 first encapsulation layer
25a first surface
25b second surface
26 second encapsulation layer
27 conductive element
29 isolation layer
30 convex part
31 alignment part.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "first", "second", and "a" as used in the present specification are for clarity of description only, and are not intended to limit the scope of the present invention, and changes or modifications in the relative relationship may be made without substantial technical changes.
Fig. 2A to fig. 2E are schematic cross-sectional views illustrating a method for manufacturing an electronic package 2 according to a first embodiment of the invention.
As shown in fig. 2A, a conductive frame 2A is provided, which includes a board 24 and a plurality of conductive posts 23 separately disposed on the board 24. Next, an isolation layer 29 is formed on the conductive frame 2a to cover the peripheral surface 23c of the conductive pillar 23.
In the present embodiment, the plate 24 and the conductive pillar 23 are integrally formed, for example, by etching, laser or otherwise removing a portion of the material of a metal plate to form the conductive frame 2 a. In another embodiment, the conductive posts 23 may also be formed on the plate 24 by a patterning process (e.g., electroplating, deposition, pasting, or other methods), as shown in fig. 2A'.
In addition, the isolation layer 29 is an insulating material, such as a green paint, which is coated (or wetted) on the surface of the conductive frame 2a (including the plate body 24 and the conductive post 23) in the manufacturing process, and then the isolation layer 29 on the end surface 23a of the conductive post 23 is removed (e.g., by polishing) to expose the end surface 23a of the conductive post 23.
In addition, the spacer 29 (green paint) does not form an eutectic with the solder material, so that the solder material is prevented from flowing onto the green paint.
As shown in fig. 2B, the conductive frame 2a is disposed on a carrying structure 20 with the conductive pillar 23, and at least one first electronic component 21 is disposed on the carrying structure 20.
In this embodiment, the carrier structure 20 has a first side 20a and a second side 20b opposite to each other, and the carrier structure 20 is, for example, a package substrate (substrate) having a core layer and a circuit portion or a coreless (core) type package substrate having a circuit portion, the circuit portion has at least one insulating layer 201 and a circuit layer 200 disposed on the insulating layer 201, and the circuit layer 200 is, for example, a fan-out (fan out) redistribution layer (RDL). Specifically, the material forming the circuit layer 200 is, for example, copper, and the material forming the insulating layer 201 is, for example, a dielectric material such as Polyoxadiazole (PBO), Polyimide (PI), Prepreg (pre, PP), or the like. It should be understood that the supporting structure may also be other supporting units for supporting electronic devices such as chips, such as lead frame (leadframe) or silicon interposer (silicon interposer), but is not limited thereto.
In addition, the first electronic element 21 is disposed on the first side 20a of the supporting structure 20, and the first electronic element 21 is an active element, such as a semiconductor chip, a passive element, such as a resistor, a capacitor, or an inductor, or a combination thereof. For example, the first electronic component 21 has an active surface 21a and an inactive surface 21b opposite to each other, and the active surface 21a has a plurality of electrode pads 210 flip-chip mounted on the circuit layer 200 via a plurality of conductive bumps 211 such as solder material and electrically connected to the circuit layer 200; alternatively, the first electronic component 21 can be electrically connected to the circuit layer 200 by wire bonding through a plurality of bonding wires (not shown). However, the manner of electrically connecting the first electronic element to the carrying structure is not limited to the above.
The conductive frame 2a is coupled to the circuit layer 200 on the first side 20a of the carrier structure 20 through the conductive body 230 such as solder material with the end surface 23a of the conductive post 23.
As shown in fig. 2C, a first encapsulation layer 25 is formed on the first side 20a of the carrier structure 20 to encapsulate the first electronic element 21, the conductive pillars 23 and the conductive body 230.
In the present embodiment, the first encapsulation layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the first surface 25a is bonded to the first side 20a of the carrier structure 20.
The material of the first sealing layer 25 is, for example, Polyimide (PI), dry film (dry film), epoxy resin (epoxy), or sealing compound (molding compound), but is not limited thereto.
In addition, the first encapsulating layer 25 is filled between the first electronic element 21 and the first side 20a of the carrying structure 20 to cover the conductive bumps 211; alternatively, an underfill (not shown) may be filled between the first electronic component 21 and the first side 20a of the carrier structure 20 to encapsulate the conductive bumps 211, and then the first encapsulant layer 25 encapsulates the underfill.
As shown in fig. 2D, a planarization process is performed to remove the board body 24 and a portion of the isolation layer 29 (even a portion of the first encapsulation layer 25), so that the end surfaces 23a of the conductive pillars 23, the isolation layer 29 and the second surface 25b of the first encapsulation layer 25 are coplanar (flush), and the end surfaces 23a of the conductive pillars 23 and the isolation layer 29 are exposed from the second surface 25b of the first encapsulation layer 25.
In this embodiment, the plate 24 and a portion of the isolation layer 29 (or even a portion of the first encapsulation layer 25) are removed by grinding, etching, burning, cutting, or other suitable means.
In addition, as shown in fig. 2D ', a portion of the material of the conductive pillar 23 is removed, so that the end surface 23 a' of the conductive pillar 23 is lower than the second surface 25b of the first encapsulation layer 25; alternatively, only the board 24 may be removed as required to retain the isolation layer 29 and the first package layer 25 above the first electronic device 21, as shown in fig. 2D ", for printing characters thereon or establishing the identification points required for the back-end process.
In addition, as shown in fig. 2D, the inactive surface 21b of the first electronic component 21 may optionally not be exposed to the second surface 25b of the first encapsulating layer 25; alternatively, as shown in fig. 2D', the non-active surface 21b of the first electronic component 21 can be exposed to the second surface 25b of the first encapsulating layer 25.
As shown in fig. 2E (see fig. 2D by turning over), a conductive element 27 such as a solder ball is formed on the exposed surface (end surface 23a) of the conductive posts 23 to form the electronic package 2, so that the conductive element 27 is reflowed to connect the electronic package 2 to an electronic device (not shown) such as a circuit board or another package.
In the present embodiment, the second side 20b of the carrying structure 20 can be used for mounting (e.g., stacking) an electronic device (not shown) such as a package substrate or another package.
In another embodiment, as shown in fig. 2E', following the process of fig. 2D (turning over fig. 2D), at least one second electronic device 22 may be disposed on the second side 20b of the carrier structure 20, and a second encapsulating layer 26 may be formed on the second side 20b of the carrier structure 20 to encapsulate the second electronic device 22. Then, conductive elements 27 such as solder balls are formed on the end surfaces 23a of the conductive posts 23 to form the electronic package 2'.
In the present embodiment, the second electronic component 22 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, or an inductor, or a combination thereof. For example, the second electronic component 22 is flip-chip mounted on the circuit layer 200 via a plurality of conductive bumps 220, such as solder material; alternatively, the second electronic component 22 can be electrically connected to the circuit layer 200 by wire bonding via a plurality of bonding wires (not shown); alternatively, the second electronic component 22 may directly contact the circuit layer 200. However, the manner of electrically connecting the second electronic element to the carrying structure is not limited to the above.
In addition, the material of the second encapsulant layer 26 is, for example, Polyimide (PI), dry film (dry film), epoxy resin (epoxy), or molding compound (molding compound), but is not limited thereto, and the material of the first encapsulant layer 25 and the material of the second encapsulant layer 26 may be the same or different, and may be formed on the second side 20b of the carrier structure 20 by lamination or molding.
In the method for manufacturing the electronic package 2 of the present invention, the isolation layer 29 is mainly used to cover the peripheral surface 23c of the conductive post 23, so that when the ball-mounting operation (forming the conductive element 27) is performed, the solder material (the conductive element 27) does not extend to the peripheral surface 23c of the conductive post 23 along with the soldering flux used in the ball-mounting operation, and therefore, compared with the prior art, the method for manufacturing the electronic package 2 of the present invention can avoid the problem of bridging between the adjacent two conductive elements 27 during the ball-mounting operation of the conductive element 27. Therefore, the electronic package 2 of the present invention does not have a tin-climbing condition, so that the problem of increasing the pad area of the conductive element 27 can be avoided, and the height of the conductive element 27 can be effectively controlled.
In addition, through the design of the conductive frame 2a, the conductive pillar 23 is placed on the carrying structure 20, so compared with the prior art, the manufacturing cost of the manufacturing method of the present invention can be greatly reduced, and thus the economic benefit can be met.
Fig. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing an electronic package 3 according to a second embodiment of the invention. The difference between this embodiment and the first embodiment is that the alignment portion is added, and other processes are substantially the same, so only the differences will be described below.
As shown in fig. 3A, at least one protrusion 30 is additionally formed on the conductive frame 2a, and the protrusion 30 is covered by the isolation layer 29.
In the present embodiment, the protrusion 30 may be a conductive material integrally formed on the board 24 or additionally formed on the board 24. In another embodiment, the protrusion 30 may be an insulating material, which is adhered to the board 24. Therefore, the structure and process of the protrusion 30 are not particularly limited.
As shown in fig. 3B, the processes shown in fig. 2B, 2C and 2D "are performed to expose the convex portion 30 from the second surface 25B of the first encapsulation layer 25.
As shown in fig. 3C, the protrusion 30 is removed to form an alignment portion 31, such as a concave portion, on the second surface 25b of the first package layer 25.
In the present embodiment, the protruding portion 30 is removed by etching, and a portion of the material of the conductive pillar 23 is also removed by etching, so that the end surface 23 a' of the conductive pillar 23 is lower than the isolation layer 29. The end surface 23 a' of the conductive pillar 23 is lower than the isolation layer 29, so that the situation of offset during subsequent ball mounting can be avoided.
The manufacturing method of the present invention is mainly used to avoid the abnormal situation of the offset occurring during ball mounting due to the offset of the supporting structure 20 by the design of the positioning portion 31, which is used as the identification point of the ball mounting machine for the electronic package 3 during ball mounting (forming the conductive element 27).
In addition, it should be understood that the conductive pillars 23 can also be bonded to the second side 20b of the carrier structure 20 as required, and the second encapsulant layer 26 encapsulates the conductive pillars 23, such that the end surfaces 23a of the conductive pillars 23 are exposed out of the second encapsulant layer 26.
The present invention also provides an electronic package 2, 2', 3 comprising: a carrier structure 20, at least one first electronic element 21, a plurality of conductive pillars 23, an isolation layer 29, and a first package layer 25.
The carrier structure 20 has a first side 20a and a second side 20b opposite to each other, and the carrier structure 20 is configured with at least one circuit layer 200.
The first electronic component 21 is disposed on the first side 20a of the carrier 20 and electrically connected to the circuit layer 200 of the carrier structure 20.
The conductive pillars 23 are disposed on the first side 20a of the carrier structure 20 and electrically connected to the circuit layer 200 of the carrier structure 20.
The isolation layer 29 is formed on the peripheral surface 23c of the conductive post 23.
The first encapsulating layer 25 encapsulates the first electronic element 21, the conductive pillar 23 and the isolating layer 29, wherein the first encapsulating layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the first surface 25a is bonded to the first side 20a of the carrier structure 20.
In one embodiment, the second electronic component 22 is disposed on the second side 20b of the supporting structure 20.
In one embodiment, a second encapsulation layer 26 is formed on the second side 20b of the carrier structure 20.
In one embodiment, a portion of the surface (non-active surface 21b) of the first electronic component 21 is exposed to the second surface 25b of the first packaging layer 25.
In one embodiment, the conductive pillars 23 are bonded and electrically connected to the circuit layer 200 of the carrier structure 20 through conductive bodies 230.
In one embodiment, the end surface 23a of the conductive pillar 23 is exposed to the second surface 25b of the first package layer 25.
In one embodiment, the end surface 23a of the conductive pillar 23 is flush with or lower than the second surface 25b of the first packaging layer 25.
In one embodiment, the isolation layer 29 extends over the second surface 25b of the encapsulation layer 25.
In one embodiment, the electronic package 2, 2', 3 further includes a plurality of conductive elements 27 formed on the end surface 23a of the conductive pillar 23.
In one embodiment, the electronic package 3 further includes at least one alignment portion 31 formed on the second surface 25b of the first package layer 25.
In summary, the electronic package and the manufacturing method thereof of the present invention mainly coat the peripheral surface of the conductive pillar with the isolation layer, so that during the ball-mounting operation, the conductive element does not extend to the peripheral surface of the conductive pillar along with the flux used in the mounting operation, and thus the problem of bridging between two adjacent conductive elements can be avoided during the process of mounting the conductive element, and therefore the electronic package of the present invention does not have the tin-climbing condition, which is beneficial to controlling the height of the conductive element.
In addition, the conductive column is arranged on the bearing structure through the design of the conductive frame, so that the manufacturing cost can be greatly reduced, and the economic benefit can be met.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims (20)

1. An electronic package, comprising:
A load-bearing structure;
at least one electronic element arranged on the bearing structure and electrically connected with the bearing structure;
a plurality of conductive columns arranged on the bearing structure and electrically connected with the bearing structure;
an isolation layer formed on the peripheral surface of each conductive column; and
and the packaging layer is used for coating the electronic element, the conductive column and the isolating layer.
2. The electronic package according to claim 1, wherein the carrier structure has a first side and a second side opposite to each other, the conductive posts are bonded to the first side and/or the second side of the carrier structure, the electronic component is disposed on the first side and/or the second side, and the package layer is formed on the first side and/or the second side.
3. The electronic package of claim 1, wherein a portion of the surface of the electronic component is exposed to the encapsulation layer.
4. The electronic package according to claim 1, wherein the conductive pillar is electrically coupled and connected to the carrier structure via a conductive body.
5. The electronic package according to claim 1, wherein the end surface of the conductive pillar is exposed out of the encapsulation layer.
6. The electronic package according to claim 1, wherein the end surface of the conductive pillar is flush with or lower than the outer surface of the encapsulation layer.
7. The electronic package of claim 1, wherein the isolation layer extends over an outer surface of the encapsulation layer.
8. The electronic package according to claim 1, further comprising a conductive element formed on the conductive pillar end surface.
9. The electronic package of claim 1, further comprising an alignment portion formed on a surface of the package layer.
10. A method of fabricating an electronic package, comprising:
arranging a conductive frame and at least one electronic element on a bearing structure, wherein the conductive frame comprises a plate body and a plurality of conductive columns connected with the plate body, the conductive columns are combined on the bearing structure, and an isolating layer is formed on the peripheral surface of each conductive column;
the electronic element, the conductive post and the isolation layer are coated by the packaging layer; and
the plate body is removed.
11. The method of claim 10, wherein the carrier structure has a first side and a second side opposite to each other, the conductive posts are bonded to the first side and/or the second side of the carrier structure, the electronic component is disposed on the first side and/or the second side, and the package layer is formed on the first side and/or the second side.
12. The method of claim 10, wherein a portion of the surface of the electronic component is exposed to the encapsulation layer.
13. The method of claim 10, wherein the conductive posts are electrically connected to the carrier structure by conductive bonding.
14. The method of claim 10, wherein the end surfaces of the conductive posts are exposed out of the package layer.
15. The method of claim 10, wherein the end surface of the conductive pillar is flush with or lower than the outer surface of the package layer.
16. The method of claim 10, wherein the isolation layer is further formed on the surface of the board body, so that when the board body is removed, the isolation layer on the surface of the board body is removed.
17. The method of claim 10, wherein the isolation layer is further formed on the surface of the board, such that the isolation layer remains on the outer surface of the encapsulation layer when the board is removed.
18. The method as claimed in claim 10, further comprising forming a conductive element on the end surface of the conductive pillar.
19. The method of claim 10, further comprising forming an alignment feature on a surface of the encapsulation layer.
20. The method of claim 19, wherein the step of fabricating the alignment portion comprises:
forming a convex part on the conductive frame, and coating the convex part with the isolation layer;
after removing the plate body, the convex part is exposed out of the packaging layer; and
removing the convex part to form a concave part on the surface of the packaging layer, and using the concave part as the contraposition part.
CN201910476232.7A 2019-05-23 2019-06-03 Electronic package and manufacturing method thereof Pending CN111987048A (en)

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CN115472574A (en) * 2021-06-10 2022-12-13 矽品精密工业股份有限公司 Electronic package and manufacturing method thereof
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