CN116207053A

CN116207053A - Electronic package and method for manufacturing the same

Info

Publication number: CN116207053A
Application number: CN202111507890.1A
Authority: CN
Inventors: 李泳达
Original assignee: Siliconware Precision Industries Co Ltd
Current assignee: Siliconware Precision Industries Co Ltd
Priority date: 2021-11-30
Filing date: 2021-12-10
Publication date: 2023-06-02
Also published as: TW202324649A; TWI806263B

Abstract

The invention relates to an electronic package and a manufacturing method thereof, comprising an electronic structure with a plurality of conductors, a plurality of conductive posts, a protective layer for coating the conductors and the conductive posts, and a coating layer for coating the electronic structure, the protective layer and the conductive posts.

Description

Electronic package and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device, and more particularly, to an electronic package and a method for manufacturing the same.

Background

In order to ensure continuous miniaturization and versatility of electronic products and communication devices, semiconductor packages are required to be miniaturized in size to facilitate multi-pin connection and to have high functionality. For example, in advanced process packaging, conventional packaging types such as 2.5D packaging, fan-Out (Fan-Out) wiring and Embedded Bridge (FO-EB) device manufacturing processes, etc., have advantages of low cost and material suppliers compared to 2.5D packaging processes.

Fig. 1 is a schematic cross-sectional view of a conventional FO-EB semiconductor package 1. The semiconductor package 1 is provided with a first semiconductor chip 11 and a plurality of conductive pillars 13 on a substrate structure 14 having a circuit layer 140 (via an adhesive 12), and then a first package layer 15 is used to encapsulate the first semiconductor chip 11 and the conductive pillars 13, and then a circuit structure 10 electrically connecting the first semiconductor chip 11 and the conductive pillars 13 is formed on the first package layer 15, so as to provide a plurality of second semiconductor chips 16 electrically connected to the circuit structure 10 on the circuit structure 10, and a second package layer 18 is used to encapsulate the second semiconductor chips 16, wherein the circuit layer 140 and the circuit structure 10 adopt a fan-out type redistribution circuit layer (redistribution layer, abbreviated as RDL) specification, and the first semiconductor chip 11 is used as a Bridge element (Bridge die) embedded in the first package layer 15 to electrically Bridge two adjacent second semiconductor chips 16.

The semiconductor package 1 is mainly disposed on a package substrate 1a by the substrate structure 14 via a plurality of solder balls 17, and the conductive pillars 13 are electrically connected to the circuit layer 140, so that the package substrate 1a is disposed on a circuit board (not shown) via solder balls 19.

However, in the conventional semiconductor package 1, after the first package layer 15 wraps the first semiconductor chip 11 and the conductive pillars 13, the large copper pillars (i.e. the conductive pillars 13) and the small copper pillars (i.e. the conductive bodies 110) of the first semiconductor chip 11 are polished to form a contour, so that in the polishing process, a polishing wheel or polishing liquid pulls a soft material such as copper along a polishing tangential direction, i.e. a so-called copper extension (Cu burr), so that the conductive pillars 13 and the conductive bodies 110 are outwardly extended to form a wire-like (burr) structure Z, which causes a short circuit problem during subsequent electrical inspection.

Therefore, how to overcome the above problems of the prior art has been an urgent issue.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic package and a method for manufacturing the same, which can avoid the problem of short circuit during subsequent electrical inspection.

The electronic package of the present invention includes: a coating layer; an electronic structure embedded in the cladding layer and having a plurality of conductors; a plurality of conductive pillars embedded in the cladding layer; and the protective layer is embedded in the coating layer and coats the plurality of conductors and the plurality of conductive columns, and part of the surfaces of the plurality of conductors and part of the surfaces of the plurality of conductive columns are exposed out of the protective layer and the coating layer.

The invention also provides a manufacturing method of the electronic packaging piece, which comprises the following steps: disposing a plurality of conductive posts and an electronic structure having a plurality of conductors on a carrier; forming a protective layer on the electronic structure and the plurality of conductive posts, so that the protective layer covers the plurality of conductors and the plurality of conductive posts; forming a coating layer on the carrier, so that the electronic structure, the protective layer and the conductive posts are coated by the coating layer, and the end surfaces of the conductive bodies and the surfaces of the end parts of the conductive posts are exposed out of the protective layer and the coating layer; the carrier is removed.

In the foregoing electronic package and the method for manufacturing the same, a leveling process is further included to make a surface of the cladding layer flush with a surface of the protection layer, a surface of the end portion of the conductive post, and an end surface of the conductive body. For example, the planarization process removes a portion of the material of the passivation layer and a portion of the material of the cladding layer by polishing. Further, the length of the end part of the protective layer, which is coated on the conductive column, is larger than the grinding depth.

In the electronic package and the method for manufacturing the same, the adjacent spacing between the plurality of conductive pillars is less than 150 μm.

In the electronic package and the method for manufacturing the same, the protective layer is an insulating material.

In the electronic package and the method for manufacturing the same, the protective layer covers the end portions of the conductive pillars but does not cover all of the conductive pillars.

In the electronic package and the method for manufacturing the same, the length of the protective layer covering the conductive post is longer than the length of the protective layer covering the conductive body.

In the electronic package and the method for manufacturing the same, the hardness of the protective layer is greater than the hardness of the conductor.

In the electronic package and the method for manufacturing the same, the hardness of the protective layer is greater than that of the conductive post.

In the electronic package and the method for manufacturing the same, the hardness of the protective layer is greater than 400Mpa.

In the foregoing electronic package and the method for manufacturing the same, a circuit structure is formed on the cladding layer and the protection layer, so that the circuit structure is electrically connected with the plurality of conductive pillars and the plurality of conductors. Further, disposing an electronic device on the circuit structure may be included, and the electronic device is electrically connected to the circuit structure.

In the foregoing electronic package and the method for manufacturing the same, a wiring structure is formed on the cladding layer, so that the wiring structure is electrically connected to the plurality of conductive pillars and the electronic structure. Further, forming a plurality of conductive elements on the wiring structure may be included, and the plurality of conductive elements are electrically connected to the wiring structure.

Therefore, in the electronic package and the manufacturing method thereof of the present invention, the protective layer is mainly used to cover the plurality of conductors and the plurality of conductive pillars, so that copper extension is not generated around the conductive pillars and the conductors due to the limitation of the protective layer when the leveling process is performed, and the conductive pillars and the conductors do not extend outward to form a filament structure.

Drawings

Fig. 1 is a schematic cross-sectional view of a conventional semiconductor package.

Fig. 2A to 2F are schematic cross-sectional views illustrating a manufacturing method of the electronic package of the present invention.

FIG. 3 is a schematic cross-sectional view of the subsequent process of FIG. 2F.

Fig. 4A to 4B are schematic cross-sectional views of another manufacturing method corresponding to fig. 2A to 2F.

Description of the reference numerals

1 semiconductor package

1a,30 packaging substrate

10,20 line structure

11 first semiconductor chip

110,21a electric conductor

12, viscose

13,23 conductive posts

14 substrate structure

140,241 line layer

15 first encapsulation layer

16 second semiconductor chip

17,19 solder balls

18 second packaging layer

2,3,4 electronic package

2a electronic structure

200 insulating layer

201 Circuit redistribution layer

202 electrical contact pad

21 electronic main body

210 conductive perforation

22 line portion

22a external connection convex block

22b bonding layer

220 passivation layer

221 conductive trace

23a end portion

24 wiring structure

24a first side

24b second side

240 dielectric layer

25 coating layer

25a first surface

25b second surface

26 electronic component

26a conductive bump

260 solder material

262, primer

27,300 conductive elements

27a UBM layer

270 metal bump

271 solder material

28 packaging layer

29 protective layer

31:strengthening piece

49 cover layer

9 bearing part

90 release layer

91 Metal layer

depth d

H, L1, L2 length

S cutting path

t is spacing

Z is a filiform structure.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure, when the following description of the present invention is taken in conjunction with the accompanying drawings.

It should be understood that the structures, proportions, sizes, etc. shown in the drawings are for the purpose of understanding and reading the disclosure, and are not intended to limit the scope of the invention, which is defined by the appended claims, but rather by the claims, unless otherwise indicated, any structural modifications, proportional changes, or dimensional adjustments, which would otherwise be apparent to those skilled in the art, are included within the spirit and scope of the present invention. Also, the terms "upper", "first", "second", "a" and the like are used herein for descriptive purposes only and are not intended to limit the scope of the invention, as such changes or modifications in the relative relationship may be made without materially altering the technical context.

Fig. 2A to 2F are schematic cross-sectional views illustrating a manufacturing method of the electronic package 2 according to the present invention.

As shown in fig. 2A, a carrier 9 is provided, and an electronic structure 2A and a plurality of conductive pillars 23 are disposed on the carrier 9, and a protection layer 29 is formed on the electronic structure 2A and the conductive pillars 23.

The carrier 9 is, for example, a plate of semiconductor material (e.g., silicon or glass), on which a release layer 90 and a metal layer 91 such as titanium/copper are sequentially formed, for example, by coating, so that a wiring structure 24 is formed on the metal layer 91.

In the present embodiment, the wiring structure 24 has a first side 24a and a second side 24b opposite to each other, and the second side 24b of the wiring structure 24 is bonded to the metal layer 91.

Furthermore, the wiring structure 24 includes at least one dielectric layer 240 and a wiring layer 241 combined with the dielectric layer 240. For example, the dielectric layer 240 is formed of a material such as poly (p-diazole) (PBO), polyimide (PI), prepreg (PP), or the like, and the circuit layer 241 and the dielectric layer 240 may be formed by a circuit redistribution layer (redistribution layer, RDL) process.

The electronic structure 2a includes an electronic main body 21, a circuit portion 22, a plurality of conductors 21a formed on the electronic main body 21, and a plurality of external bumps 22a formed on the circuit portion 22 and electrically connecting the circuit portion 22 and the circuit layer 241, wherein a bonding layer 22b is formed on the circuit portion 22 to cover the external bumps 22a, so that the electronic structure 2a is bonded on the first side 24a of the wiring structure 24 with the bonding layer 22b thereon, and the external bumps 22a are bonded to the circuit layer 241.

In this embodiment, the electronic body 21 is a silicon substrate, such as a semiconductor chip, and has a plurality of conductive vias 210, such as Through-silicon vias (TSVs), penetrating the electronic body 21 to electrically connect the circuit portion 22 and the plurality of conductors 21a. For example, the circuit portion 22 includes at least one passivation layer 220 and a conductive trace 221 combined with the passivation layer 220, such that the conductive trace 221 electrically connects the conductive via 210 and the plurality of external bumps 22a. It should be understood that the embodiment of the device structure with the conductive via 210 is numerous and not particularly limited.

Furthermore, the Conductive body 21a and the external bump 22a are metal pillars such as copper pillars, and the bonding layer 22b is a Non-Conductive Film (NCF) or other material that is easy to adhere to the dielectric layer 240.

The conductive post 23 is disposed on the first side 24a of the wiring structure 24 and electrically connected to the circuit layer 241.

In this embodiment, the conductive pillars 23 are formed of a metal material such as copper or a solder material, and the adjacent distance t between the conductive pillars 23 is less than 150 micrometers (um). For example, the conductive pillars 23 are formed on the circuit layer 241 by electroplating through an exposure and development method.

The protective layer 29 is made of an insulating material, for example, nitride (silicon nitride (SiN)), and the protective layer 29 covers the peripheral surface of the end portion 23a of the conductive post 23 but does not cover the entire peripheral surface of the conductive post 23, and the protective layer 29 covers the entire peripheral surface of the conductive body 21a.

In this embodiment, the hardness of the protection layer 29 is greater than the hardness of the conductive body 21a (e.g., copper pillar) and the hardness of the conductive pillar 23 (e.g., copper pillar). For example, the hardness of the protective layer 29 is greater than 400Mpa.

As shown in fig. 2B, a cladding layer 25 is formed on the first side 24a of the wiring structure 24, such that the cladding layer 25 encapsulates the electronic structure 2a, the protection layer 29 and the conductive pillars 23, wherein the cladding layer 25 has a first surface 25a and a second surface 25B opposite to each other, such that the end surfaces of the protection layer 29, the conductive body 21a and the surfaces of the ends 23a of the conductive pillars 23 are exposed from the first surface 25a of the cladding layer 25, and such that the cladding layer 25 is bonded to the first side 24a of the wiring structure 24 with the second surface 25B thereof.

In this embodiment, the coating layer 25 is an insulating material, such as Polyimide (PI), dry film (dry film), and an encapsulant or a molding compound (molding compound) such as epoxy. For example, the coating layer 25 may be formed on the wiring structure 24 by liquid molding (liquid composition), spraying (injection), lamination (lamination), or embossing (compression molding).

Furthermore, the first surface 25a of the cladding layer 25 may be flush with the top surface of the protection layer 29, the surface of the end portion 23a of the conductive pillar 23 and the end surface of the conductive body 21a through a planarization process, so that the surface of the end portion 23a of the conductive pillar 23 and the end surface of the conductive body 21a are exposed out of the first surface 25a of the cladding layer 25. For example, the planarization process removes a portion of the material of the protective layer 29, a portion of the material of the conductive pillars 23, a portion of the material of the conductive body 21a, and a portion of the material of the cladding layer 25 by polishing. Further, the length H of the protective layer 29 covering the end 23a of the conductive pillar 23 is greater than the polishing depth d of the planarization process, as shown in fig. 2A.

In addition, the length L2 of the protective layer 29 covering the conductive post 23 is greater than the length L1 of the protective layer 29 covering the conductive body 21a. For example, the lengths L1, L2 differ by at least 10 microns (i.e., L2-L1 +.10).

As shown in fig. 2C, a circuit structure 20 is formed on the first surface 25a of the cladding layer 25 and the protection layer 29, so that the circuit structure 20 electrically connects the conductive pillars 23 and the conductive body 21a.

In this embodiment, the circuit structure 20 includes at least one insulating layer 200 and a circuit redistribution layer (redistribution layer, abbreviated as RDL) 201 disposed on the insulating layer 200, wherein the insulating layer 200 on the outermost layer can be used as a solder mask, and the solder mask is exposed out of the circuit redistribution layer 201 on the outermost layer, so as to serve as an electrical contact pad 202, such as a micro pad (commonly called μ -pad).

Furthermore, the material forming the circuit redistribution layer 201 is copper, and the material forming the insulating layer 200 is a dielectric material such as poly (p-diazole) (PBO), polyimide (PI), prepreg (PP), or a solder resist material such as green paint, ink, or the like.

As shown in fig. 2D, a plurality of electronic devices 26 are disposed on the circuit structure 20, and an encapsulation layer 28 is used to encapsulate the electronic devices 26.

In the present embodiment, the electronic device 26 is an active device, such as a semiconductor chip, a passive device, such as a resistor, a capacitor, and an inductor, or a combination thereof. In one embodiment, the electronic device 26 is a semiconductor chip such as a graphics processor (graphics processing unit, GPU) or a high bandwidth memory (High Bandwidth Memory, HBM), and the electronic structure 2a is used as a Bridge device (Bridge die) electrically connected to the circuit structure 20 via the conductor 21a to electrically Bridge at least two electronic devices 26.

Furthermore, the electronic component 26 has a plurality of conductive bumps 26a, such as copper pillars, to electrically connect the electrical contact pads 202 via a plurality of solder materials 260, such as solder bumps, and the encapsulation layer 28 can encapsulate the electronic component 26 and the conductive bumps 26a at the same time. In this embodiment, an under bump metal (Under Bump Metallurgy, abbreviated as UBM) (not shown) may be formed on the electrical contact pad 202 or the electronic device 26 to facilitate bonding the solder material 260 or the conductive bump 26a.

In addition, the encapsulation layer 28 is an insulating material, such as Polyimide (PI), dry film (dry film), an encapsulant such as epoxy (epoxy), or a molding compound (molding compound), which may be formed on the circuit structure 20 by lamination or molding. It should be appreciated that the material forming the encapsulation layer 28 may be the same or different from the material of the cladding layer 25.

In addition, an underfill 262 may be formed between the electronic component 26 and the circuit structure 20 to encapsulate the conductive bumps 26a and the solder material 260, and then the encapsulation layer 28 may be formed to encapsulate the underfill 262 and the electronic component 26.

As shown in fig. 2E, the carrier 9 and the release layer 90 thereon are removed, and the metal layer 91 is removed to expose the second side 24b of the wiring structure 24.

In this embodiment, when the release layer 90 is stripped, the metal layer 91 is used as a barrier to avoid damaging the dielectric layer 240 of the wiring structure 24, and after the carrier 9 and the release layer 90 thereon are removed, the metal layer 91 is removed by etching to expose the wiring layer 241.

As shown in fig. 2F, a singulation process is performed along the dicing path S shown in fig. 2E, and a plurality of conductive elements 27 are formed on the second side 24b of the wiring structure 24, such that the conductive elements 27 are electrically connected to the circuit layer 241, so as to manufacture the electronic package 2.

In this embodiment, the conductive element 27 includes a metal bump 270 made of copper material and a solder material 271 formed on the metal bump 270. For example, an under bump metal (Under Bump Metallization, UBM) 27a may be formed on the wiring layer 241 to facilitate bonding the metal bump 270. It should be appreciated that when the number of contacts (IOs) is insufficient, a build-up operation may still be performed via the RDL process to reconfigure the number of IOs and their locations of the wiring structure 24.

Furthermore, a portion of the material of the encapsulation layer 28 may be removed by a planarization process, such as polishing, so that the upper surface of the encapsulation layer 28 is flush with the upper surface of the electronic component 26, as shown in fig. 3, so that the electronic component 26 is exposed out of the encapsulation layer 28.

In addition, as shown in fig. 3, the conductive elements 27 may be disposed on a package substrate 30. Further, the lower side of the package substrate 30 is subjected to a ball-mounting process to form a plurality of conductive elements 300, such as solder balls, for subsequent processes, wherein the package substrate 30 is disposed on a circuit board (not shown) with the conductive elements 300 on the lower side thereof.

In addition, a fastener 31, such as a metal frame as shown in fig. 3, may be disposed on the package substrate 30 according to requirements, so as to eliminate the problem of stress concentration and avoid the warpage of the electronic package 3.

Therefore, in the method of the present invention, the plurality of conductive bodies 21a and the plurality of conductive pillars 23 are mainly covered by the protection layer 29, and the protection layer 29 has a hardness greater than that of copper, so that when the leveling process shown in fig. 2B is performed, the periphery of the large copper pillars (i.e. the conductive pillars 23) and the small copper pillars (i.e. the conductive bodies 21 a) are limited by the protection layer 29, and copper expansion is not generated, so that compared with the prior art, the conductive pillars 23 and the conductive bodies 21a of the present invention do not expand the filament structure outwards, and thus the problem of short circuit during subsequent electrical inspection (such as electrical defect of the circuit redistribution layer 201 of the circuit structure 20) can be avoided.

Furthermore, since the protection layer 29 can prevent the plurality of conductors 21a and the plurality of conductive pillars 23 from copper extension, the short circuit problem of the conductive pillars 23 is not caused when the pitch t of each conductive pillar 23 is shortened.

In addition, the protection layer 29 may be made of hard metal material based on the hardness of the protection layer 29 being greater than that of copper material, but the protection layers 29 between the conductive posts 23 (or the conductive bodies 21 a) need to be separated from each other.

In addition, as shown in fig. 4A, in the process of fig. 2A, the protection layer 29 is formed only on a portion of the surface of the electronic structure 2A and not covered on the entire top surface of the electronic body 21. For example, the protective layer 29 is formed along the peripheral surface and the end surface of the conductor 21a, and then the protective layer 29 is covered by a cover layer 49, wherein the cover layer 49 is an insulating Film, a Polyimide (PI) material, a Non-Conductive Film (NCF) or other insulating materials. Then, according to the process shown in fig. 2B to 2F, another electronic package 4 is obtained, as shown in fig. 4B. Thus, the electronic structure 2a can cover the entire top surface of the electronic body 21 through two cladding operations.

The invention also provides an

electronic package

2,4 comprising: a cladding layer 25, an electronic structure 2a having a plurality of conductors 21a, a plurality of conductive pillars 23, and a protective layer 29.

The electronic structure 2a is embedded in the cladding layer 25.

The conductive posts 23 are embedded in the cladding layer 25.

The protective layer 29 is embedded in the cladding layer 25 and coats the plurality of conductors 21a and the plurality of conductive pillars 23, and the protective layer 29 and the cladding layer 25 are exposed from part of the surfaces of the plurality of conductors 21a and part of the surfaces of the plurality of conductive pillars 23.

In one embodiment, the first surface 25a of the cladding layer 25 is flush with a surface of the protection layer 29, a surface of the end 23a of the conductive pillar 23, and an end surface of the conductive body 21a.

In one embodiment, the distance t between adjacent conductive pillars 23 is less than 150 μm.

In one embodiment, the protection layer 29 is an insulating material.

In one embodiment, the protective layer 29 covers the end 23a of the conductive post 23 without covering the entire conductive post 23.

In one embodiment, the length L2 of the protective layer 29 covering the conductive post 23 is greater than the length L1 of the protective layer 29 covering the conductive body 21a.

In one embodiment, the hardness of the protective layer 29 is greater than the hardness of the electrical conductor 21a.

In one embodiment, the hardness of the protective layer 29 is greater than the hardness of the conductive post 23.

In one embodiment, the hardness of the protective layer 29 is greater than 400Mpa.

In an embodiment, the electronic package 2 further includes a circuit structure 20 formed on the cladding layer 25 and the protection layer 29, so that the circuit structure 20 electrically connects the plurality of conductive pillars 23 and the plurality of conductors 21a. Further, the electronic packages 2,3 may further include at least one electronic component 26 disposed on the circuit structure 20 and electrically connected to the circuit structure 20.

In an embodiment, the electronic package 2 further includes a wiring structure 24 formed on the cladding layer 25, so that the wiring structure 24 electrically connects the plurality of conductive pillars 23 and the electronic structure 2a. Further, the electronic package 2 may further include a plurality of conductive elements 27 formed on the wiring structure 24 and electrically connected to the wiring structure 24.

In summary, the design of the protective layer is used to prevent copper from extending around the conductive pillars and the conductive body due to the limitation of the protective layer when the planarization process is performed, so that the conductive pillars and the conductive body do not extend out of the wire structure, and the electronic package of the invention can avoid the problem of short circuit during subsequent electrical inspection, and also can avoid the problem of short circuit of the conductive pillars when the pitch of the conductive pillars is shortened.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications to the above would be obvious to those of ordinary skill in the art, without departing from the spirit and scope of the present invention. The scope of the invention is therefore intended to be indicated by the appended claims.

Claims

1. An electronic package, comprising:

a coating layer;

an electronic structure embedded in the cladding layer and having a plurality of conductors;

a plurality of conductive pillars embedded in the cladding layer; and

and the protective layer is embedded in the coating layer and coats the plurality of conductors and the plurality of conductive columns, and part of the surfaces of the plurality of conductors and part of the surfaces of the plurality of conductive columns are exposed out of the protective layer and the coating layer.

2. The electronic package of claim 1, wherein a surface of the cladding layer is flush with a surface of the protective layer, a surface of the end of the conductive post, and an end face of the conductive body.

3. The electronic package of claim 1, wherein the plurality of conductive pillars are adjacent to each other at a pitch of less than 150 microns.

4. The electronic package of claim 1, wherein the material forming the protective layer is an insulating material.

5. The electronic package of claim 1, wherein the protective layer covers the ends of the conductive pillars but not all of the conductive pillars.

6. The electronic package of claim 1, wherein the length of the protective layer covering the conductive pillars is greater than the length of the protective layer covering the conductors.

7. The electronic package of claim 1, wherein the protective layer has a hardness greater than a hardness of the electrical conductor.

8. The electronic package of claim 1, wherein the protective layer has a hardness greater than the hardness of the conductive posts.

9. The electronic package of claim 1, wherein the protective layer has a hardness greater than 400Mpa.

10. The electronic package of claim 1, further comprising a circuit structure formed on the cover layer and the protective layer and electrically connecting the plurality of conductive pillars and the plurality of conductors.

11. The electronic package of claim 10, further comprising an electronic device disposed on and electrically connected to the circuit structure.

12. The electronic package of claim 1, further comprising a wiring structure formed on the cladding layer, wherein the wiring structure electrically connects the plurality of conductive pillars and the electronic structure.

13. The electronic package of claim 12, further comprising a plurality of conductive elements formed on and electrically connected to the wiring structure.

14. A method of manufacturing an electronic package, comprising:

disposing a plurality of conductive posts and an electronic structure having a plurality of conductors on a carrier;

forming a protective layer on the electronic structure and the plurality of conductive posts, so that the protective layer covers the plurality of conductors and the plurality of conductive posts;

forming a coating layer on the carrier, so that the electronic structure, the protective layer and the conductive posts are coated by the coating layer, and the end surfaces of the conductive bodies and the surfaces of the end parts of the conductive posts are exposed out of the protective layer and the coating layer; and

the carrier is removed.

15. The method of claim 14, further comprising leveling a surface of the cover layer to be flush with a surface of the protective layer, a surface of the end portion of the conductive post, and an end surface of the conductive body.

16. The method of claim 15, wherein the planarization process removes a portion of the passivation layer and a portion of the cladding layer by polishing.

17. The method of claim 16, wherein the protective layer covers the conductive post with a length greater than the polishing depth.

18. The method of claim 14, wherein the plurality of conductive pillars are adjacent to each other at a pitch of less than 150 microns.

19. The method of claim 14, wherein the material forming the passivation layer is an insulating material.

20. The method of claim 14, wherein the protective layer covers the ends of the conductive pillars but not the entire conductive pillars.

21. The method of claim 14, wherein the length of the protective layer covering the conductive pillars is greater than the length of the protective layer covering the conductors.

22. The method of claim 14, wherein the protective layer has a hardness greater than a hardness of the electrical conductor.

23. The method of claim 14, wherein the protective layer has a hardness greater than the conductive pillars.

24. The method of claim 14, wherein the hardness of the protective layer is greater than 400Mpa.

25. The method of claim 14, further comprising forming a circuit structure on the cladding layer and the passivation layer to electrically connect the plurality of conductive pillars and the plurality of conductors.

26. The method of claim 25 further comprising disposing an electronic device on the circuit structure and electrically connecting the electronic device to the circuit structure.

27. The method of claim 14, further comprising forming a wiring structure on the cladding layer to electrically connect the plurality of conductive pillars and the electronic structure.

28. The method of claim 27, further comprising forming a plurality of conductive elements on the wiring structure, and electrically connecting the plurality of conductive elements to the wiring structure.