CN101226915B - 封装基板及其制造方法 - Google Patents
封装基板及其制造方法 Download PDFInfo
- Publication number
- CN101226915B CN101226915B CN 200810080707 CN200810080707A CN101226915B CN 101226915 B CN101226915 B CN 101226915B CN 200810080707 CN200810080707 CN 200810080707 CN 200810080707 A CN200810080707 A CN 200810080707A CN 101226915 B CN101226915 B CN 101226915B
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- CN
- China
- Prior art keywords
- packaging
- board unit
- base board
- base plate
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Packaging Frangible Articles (AREA)
Abstract
Description
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200810080707 CN101226915B (zh) | 2008-02-05 | 2008-02-05 | 封装基板及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200810080707 CN101226915B (zh) | 2008-02-05 | 2008-02-05 | 封装基板及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101226915A CN101226915A (zh) | 2008-07-23 |
CN101226915B true CN101226915B (zh) | 2010-09-29 |
Family
ID=39858801
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 200810080707 Active CN101226915B (zh) | 2008-02-05 | 2008-02-05 | 封装基板及其制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101226915B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102194715A (zh) * | 2010-03-16 | 2011-09-21 | 南亚电路板股份有限公司 | 封装基板模块及其条状封装基板 |
CN109256361B (zh) * | 2018-08-02 | 2020-06-09 | 江苏长电科技股份有限公司 | 一种选择性背金芯片封装结构及其工艺方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6481098B1 (en) * | 2001-07-05 | 2002-11-19 | Shou-Chih Lin Chen | Method of manufacturing circuit boards |
US6551855B1 (en) * | 2001-11-14 | 2003-04-22 | Advanced Semiconductor Engineering, Inc. | Substrate strip and manufacturing method thereof |
TWI237353B (en) * | 2003-12-23 | 2005-08-01 | Siliconware Precision Industries Co Ltd | Substrate strip for increasing yield and method for fabricating the same |
CN1816904A (zh) * | 2003-06-30 | 2006-08-09 | 英特尔公司 | 在倒装多矩阵阵列封装中的模制化合物盖及其制作工艺 |
-
2008
- 2008-02-05 CN CN 200810080707 patent/CN101226915B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6481098B1 (en) * | 2001-07-05 | 2002-11-19 | Shou-Chih Lin Chen | Method of manufacturing circuit boards |
US6551855B1 (en) * | 2001-11-14 | 2003-04-22 | Advanced Semiconductor Engineering, Inc. | Substrate strip and manufacturing method thereof |
CN1816904A (zh) * | 2003-06-30 | 2006-08-09 | 英特尔公司 | 在倒装多矩阵阵列封装中的模制化合物盖及其制作工艺 |
TWI237353B (en) * | 2003-12-23 | 2005-08-01 | Siliconware Precision Industries Co Ltd | Substrate strip for increasing yield and method for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
CN101226915A (zh) | 2008-07-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: RI YUE GUANG SEMICONDUCTOR (SHANGHAI)CO., LTD. Free format text: FORMER OWNER: RIYEGUANG SEMICONDUCTOR MANUFACTURING CO., LTD. Effective date: 20081107 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20081107 Address after: A6-2 block, Zhangjiang hi tech park, Shanghai, China: 201203 Applicant after: Advanced Semiconductor (Shanghai) Co., Ltd. Address before: Taiwan City, Kaohsiung Chinese Nantze export processing zone by three road No. 26 Applicant before: Riyueguang Semiconductor Manufacturing Co., Ltd. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee |
Owner name: ADVANCED SEMICONDUCTOR (SHANGHAI) CO., LTD. Free format text: FORMER NAME: ADVANCED SEMICONDUCTOR ENGINEERING (SHANGHAI) INC. |
|
CP01 | Change in the name or title of a patent holder |
Address after: 201203 Shanghai Zhangjiang hi tech park A6-2 block Patentee after: Advanced Semiconductor (Shanghai) Co., Ltd. Address before: 201203 Shanghai Zhangjiang hi tech park A6-2 block Patentee before: Advanced Semiconductor (Shanghai), Inc. |
|
C56 | Change in the name or address of the patentee | ||
CP02 | Change in the address of a patent holder |
Address after: 201203 Shanghai Jinke Road, Pudong New Area Zhangjiang hi tech Park No. 2300 Patentee after: Advanced Semiconductor (Shanghai) Co., Ltd. Address before: 201203 Shanghai Zhangjiang hi tech park A6-2 block Patentee before: Advanced Semiconductor (Shanghai) Co., Ltd. |