TWI237353B - Substrate strip for increasing yield and method for fabricating the same - Google Patents
Substrate strip for increasing yield and method for fabricating the same Download PDFInfo
- Publication number
- TWI237353B TWI237353B TW092136487A TW92136487A TWI237353B TW I237353 B TWI237353 B TW I237353B TW 092136487 A TW092136487 A TW 092136487A TW 92136487 A TW92136487 A TW 92136487A TW I237353 B TWI237353 B TW I237353B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- hollowed
- out area
- strip
- adjacent
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
12373531237353
五、發明說明(1) 【發明所屬之技術領域】 及其製 擠壓而 、本^月,有關於一種半導體封裝件之基板條片 法更"羊而口之’係關於一種可提高產量且不致因 變形之基板條片及其製法。 【先前技術】 術, 座, 晶片 表面 包覆 產需 一整 元, 封裝 裝單 10〇 球栅陣列半導體封裝技術是一種先進的 丄圖所示,以基板21作為半導體晶片心;支 在於,、上表面與下表面皆敷設導電跡線層4,而 2以詳線3包性連接該上表面之導電跡線層,以藉复 所植入之鋅埭6而將電訊訊號傳送至外界,進而一 該晶片2與銲線3的封裝膠體5保護該封裝件。曰 此一球柵陣列封裝们〇為顧及製法上之成本考量盥旦 二其…系以批次方式(Batch Type)製作,亦即: 一、土反 乂夕條封裝分界線預先定義出複數個封裝單 、工 ί^上片(Die Bond)、銲接(wire Bond)及膠 I# 等步驟後,再施予切單(Singulati〇n)去除相鄰封 元門的連、σ ’以製成第1圖所示之單一半導體封装件 如第2圖所示,該球栅陣列基板單元22係以成批方式 (Ba^ch Type)建構於一基板條片 μ (substrate Strip) •母* =板彳木片2 1均包含複數個由封裳線24 ( Package Une)劃分出來的四方形基板單元22與連結各相鄰基板單 兀22之基板,接部21〇,而各基板單元22係彼此鄰接,並 於相鄰基板單元2 2間的基板連接部2 1 0上開設一用以釋放V. Description of the invention (1) [Technical field to which the invention belongs] and its extrusion, this month, there is more about the substrate strip method of a semiconductor package " going by the sheep 'is about improving production The substrate strip and its manufacturing method without causing deformation. [Previous technology] The entire surface area of the wafer, the wafer, and the wafer are covered with a whole package. The packaging technology of the 100-ball grid array semiconductor package is an advanced diagram shown in the figure. The substrate 21 is used as the core of the semiconductor wafer. The upper and lower surfaces are laid with a conductive trace layer 4, and 2 is connected to the conductive trace layer on the upper surface with a detailed wire 3 to transmit the telecommunication signal to the outside by recovering the implanted zinc alloy 6. An encapsulant 5 of the chip 2 and the bonding wire 3 protects the package. This is a ball grid array package. In order to take into account the cost of the manufacturing method, it is produced in a batch method (that is, batch type), that is: 1. A number of packaging boundaries are defined in advance. After packaging, sheet bonding, die bonding, wire bonding, and glue I #, etc., Singulation is applied to remove the connection and σ 'of the neighboring seal gates to make The single semiconductor package shown in FIG. 1 is shown in FIG. 2. The ball grid array substrate unit 22 is constructed in a batch manner on a substrate strip μ (substrate Strip). • Female * = The linden wood chips 21 each include a plurality of rectangular substrate units 22 divided by a package line 24 (Package Une) and the substrates connecting the adjacent substrate units 22 and the connecting portions 21, and the substrate units 22 are connected to each other. Adjacent to each other, a substrate release portion 2 10 between adjacent substrate units 22 is provided for releasing.
175]3石夕品.口土(1 第10頁 1237353 五、發明說明(2) 應力之孔槽2 3 Γ ς 1 i^ 翹曲變形。 1〇t),以防止基板條片21在封裝製程中 酌述基板條片2 1之最大缺點在於空間盘 = = 處,卻於該型基板條片21上二 7 使基板條片21上之基板單元22數量難以再往上 基板材料成:………,亦將浪費過多的 所干=’ :Κ ί利第5’ 65 2’ 185號案所揭示,如第3圖 2板條片…其係縮減前述基板條片2! 才郤土板早兀22間的基板連接部2丨〇空間,並令相 = ί力釋放孔槽2“可大幅提升基板條 片11上之二間利用率’解決前述基板條片21問題,並提高 早位空間中的基板單元22密度’提升整體產能。 然而,對前述兩種基板條片2卜u而言,均難以避 於製造過程中產生不良之基板單元,一般而言,每一基板 條片常出現有一至兩個不良基板單元(—般稱為^ 〇ut 2-X out基板),而當每個基板條片上之不良基板單元超, 過,個時,封裝業者將不予購買,而造成基板製造成本上 之貝失’且在封I之自動化整體製程了,亦難以在隨後的 模壓(Moidmg)製程中停止對該不良基板單元之灌膠,從 而將使生產效率降低並增加封裝膠體的材料成本。 目前習知上係以一嵌入更替方法解決此一不良基板 元問題,以提高封裝件產出及降低生產成本,該方法係如175] 3 Shi Xipin. Mouth soil (1 Page 10 1237353 V. Description of the invention (2) Stress hole 2 3 Γ ς 1 i ^ Warpage deformation. 10t) to prevent the substrate strip 21 from being packaged In the manufacturing process, the biggest disadvantage of the substrate strip 21 is that the space disk = =, but on this type of substrate strip 21, the number of substrate units 22 on the substrate strip 21 is difficult to go up. …, Too much waste will be wasted = ': Κ ί 利 5' 65 2 '185 Case, as shown in Figure 3 slabs ... It is to reduce the aforementioned substrate strips 2! The space of the substrate connection portion 2 between the early stages 22 and the phase = force release the slot 2 "can greatly improve the utilization rate of the two spaces on the substrate strip 11 'to solve the aforementioned problem of the substrate strip 21 and improve the early position. The density of the substrate units 22 in the space improves the overall production capacity. However, for the two types of substrate strips described above, it is difficult to avoid defective substrate units during the manufacturing process. Generally, each substrate strip is often There are one to two bad substrate units (commonly referred to as ^ 〇ut 2-X out substrate), and when the A good substrate unit is too expensive. However, at this time, the packaging industry will not buy it, which will result in a loss of substrate manufacturing cost and it will be in the automated overall process of sealing. It is also difficult to stop the process in the subsequent molding (Moidmg) process. The filling of the defective substrate unit will reduce the production efficiency and increase the material cost of the packaging colloid. It is conventionally known to solve this problem of the defective substrate element by an embedded replacement method to increase the output of the package and reduce the production cost. , The method is
17513石夕品.口士(] f 11頁 1237353 五、發明說明(3) 第4A至4C圖所示(以第3圖所示之基板條片1 1為例),首先 如第4 A圖所示分別檢測該基板條片1 1上之複數個基板單元 1 2,以藉檢測結果選取該基板條片1 1上的不良基板單元 1 2 b ;並如第4 B圖般自該基板條片1 1上裁切下該不良基板 單元1 2 b,以於該基板條片1 1上留下一鏤空區域1 5,同時 保留其餘之良好基板單元1 2 a ;接著,如第4 C圖所示另外 選取一良好基板單元14,且 係與該鏤空區域1 5相同,以 鏤空區域1 3中,例如美國專 出類似之嵌入方法,以於封 條片上的不良基板單元,避 惟,此一方法雖可藉由 而提升整體產能,卻將產生 該良好基板單元1 4在尺寸與 同,故而當該良好基板單元 條片1 1時’將造成該基板條 力而致使該基板條片1 1變形 送料過程發生卡料等問題, 加一修邊整型過程,導致製 因此,如何提供一種可 法,以解決該基板條片之嵌 序以增進製程效率,確為此 題。 【發明内容】 該良好基板單元1 4之形狀尺寸 將該良好基板單元1 4嵌合入該 利第5, 8 9 7, 3 34號案,即係提 裝製程之前即預先更換該基板 免產能之浪費。 預先選取出不良基板單元12b 其他良率問題,其原因係由於 形狀上均與該鏤空區域1 5相 1 4如第4C圖所示嵌合入該基板 片1 1的擠壓,進而因其擠壓應 且平面度降低,並於自動化之 故而常需於嵌合步驟之後再增 程步驟之增加與產能之降低。 提高產量之基板條片及其製 合變形問題,同時省去修邊程 一研究領域所需迫切面對之問17513 Shi Xipin. Mouth (] f 11 pages 1237353 5. Explanation of the invention (3) Figures 4A to 4C (take the substrate strip 1 1 shown in Figure 3 as an example), first as shown in Figure 4 A As shown in the figure, the plurality of substrate units 12 on the substrate strip 11 are respectively detected, and the defective substrate units 1 2 b on the substrate strip 11 are selected based on the detection results; The bad substrate unit 1 2 b is cut out on the sheet 11 to leave a hollowed-out area 15 on the substrate strip 11 while retaining the remaining good substrate units 1 2 a; then, as shown in FIG. 4C As shown, another good substrate unit 14 is selected, and is the same as the hollow area 15, and in the hollow area 13, for example, a similar embedding method is specially developed in the United States for the bad substrate unit on the seal sheet to avoid this. Although the method can improve the overall productivity by this method, the good substrate unit 14 will have the same size, so when the good substrate unit strip 11 is used, the substrate strip force will be caused and the substrate strip 1 1 will be caused. Problems such as jamming during the deformation feeding process, plus a trimming and shaping process, leading to the system. It is a problem to provide a method to solve the embedded sequence of the substrate strip to improve the process efficiency. [Summary] The shape and size of the good substrate unit 14 fit the good substrate unit 14 into the lidi. Case No. 5, 8 9 7, 3 34 is to replace the substrate in advance before the lifting process to avoid waste of production capacity. The bad yield of the defective substrate unit 12b is selected in advance. The reason is that the shape is related to the hollowed out area. 1 5 phase 1 4 is inserted into the extrusion of the substrate sheet 1 as shown in FIG. 4C, and because of the extrusion and flatness of the extrusion, it is often necessary to increase the step after the fitting step for automation reasons. Increase and decrease in production capacity. Increasing the production of substrate strips and their deformation problems, while eliminating the need for urgent repair in the research area
17513石夕品.口士(117513 Shi Xipin. Oral (1
第12頁 1237353 五、發明說明(4) 鑒於上述習知技術的問題,本發明之主要目的在於提 供一種可提高產量且於嵌合時不易變形之基板條片及其製 法。 本發明之另一目的在於提供一種可減少成本且於嵌合 時不易變形之基板條片及其製法。 本發明之又一目的在於提供一種無需進行修邊程序的 基板條片及其製法。 本發明之再一目的在於提供一種可增進製程效率的基 板條片及其製法。 為達上述之目的,本發明提供一種可提高產量之基板 條片製法,該基板條片上係包括複數個彼此鄰接的基板單 元,該製法包括:分別檢測該基板條片上之複數個基板單 元,以藉檢測結果選取該基板條片上的不良基板單元;自 該基板條片上裁切下該不良基板單元,以於該基板條片上 留下一第一鏤空區域,同時,一併自該基板條片上裁切下 與該不良基板單元之至少一邊緣相鄰的區域,以於該基板 條片上留下至少一與該第一鏤空區域相連通的第二鏤空區 域,另外選取已經檢測的良好基板單元,且該良好基板單 兀之形狀尺寸與該第一鏤空區域相同;以及將該良好基板 單兀嵌合入該第一鏤空區域中,以藉該至少第二鏤空區域 避免該基板條片發生變形。 另外’本發明復提供一種可提高產量之基板條片,包 括邊框與複數個彼此相鄰的良好基板單元,且該複數個 良好基板單元係分別形成於該邊框所圍置出的複數個區域Page 12 1237353 V. Description of the invention (4) In view of the problems of the above-mentioned conventional technology, the main object of the present invention is to provide a substrate strip which can increase the yield and is not easily deformed during fitting, and a manufacturing method thereof. Another object of the present invention is to provide a substrate strip which can reduce cost and is not easily deformed during fitting, and a manufacturing method thereof. Still another object of the present invention is to provide a substrate strip without a trimming process and a method for manufacturing the same. Still another object of the present invention is to provide a base strip and a method for manufacturing the same, which can improve the process efficiency. To achieve the above object, the present invention provides a substrate strip manufacturing method capable of improving yield. The substrate strip includes a plurality of substrate units adjacent to each other. The manufacturing method includes: detecting a plurality of substrate units on the substrate strip, and Based on the test results, the defective substrate unit on the substrate strip is selected; the defective substrate unit is cut from the substrate strip to leave a first hollow area on the substrate strip, and at the same time, the substrate strip is cut from the substrate strip. An area adjacent to at least one edge of the defective substrate unit is cut to leave at least one second hollowed area on the substrate strip that communicates with the first hollowed out area, and a good substrate unit that has been tested is selected, and The shape and size of the good substrate unit are the same as the first hollowed-out area; and the good substrate unit is fitted into the first hollowed-out area to prevent the substrate strip from being deformed by the at least second hollowed-out area. In addition, the present invention further provides a substrate strip capable of improving yield, including a frame and a plurality of good substrate units adjacent to each other, and the plurality of good substrate units are respectively formed in a plurality of regions surrounded by the frame.
175] 3石夕品.ptd 第13頁 1237353 五、發明說明(5) ~~------ 少—欲ί於該邊框所圍置出的其中-區域的良 緣“的區域i:ί J: ”良好基板單元之至少-邊 :Lί! L t 鏤空區$,同時,該欲合良好的 ==尺寸係與該複數個良好基板單元相同。 則述基板條片上之相鄰基板單 且該孔槽係可分別盥該兩美柘@ — 你開e又有孔牙曰175] 3 Shi Xipin. Ptd Page 13 1237353 V. Description of the invention (5) ~~ ------ Less—I want to focus on the middle of the border surrounded by the border. J: ”At least-edge of a good substrate unit: Lί! L t Hollow out area $, meanwhile, the desired good == size is the same as the plurality of good substrate units. Then, the adjacent substrates on the substrate strip are described, and the holes and grooves can be used separately. @ — 你 开 e 又有 牙
Lin^n ps 4別/、亥兩基板早兀之封裝線(Package ’Λ可^別與該兩基板單元之封裝線重 :域係與該第…區域上未與該孔槽“之ί::Γ 因此,本方法即係藉由該鏤空區域之設叶,以嗲铉 空區域釋放嵌合過程中之應力 =1錯4鏤 面度降低缺陷,並可省去修邊步; 基板產量與節省基板成本等功效。’亦兼〃有提南 【實施方式】 以下即以圖式配合各實施例蛘 片及其製"各圖式的元心;:、:明之基板條 實施例内容簡單繪示,並非依昭實物數里及結構僅按 條片的實物結構以及實際態樣應較圖式更::::該基板 本發明之基板條片係供至少一半導峡:^ =件載接之用,㈣上片、銲線及膠一】 = = 裝件成型於基板條片上#,此基板條 使封 皁作業而製成複數個球柵陣列半導體封事 機口執仃切 I二·實施例: 、件。Lin ^ n ps 4 // Hai two substrates early packaging line (Package 'Λ 可 ^ and the two substrate unit packaging line weight: the domain system and the first area is not connected with the hole slot of the "": : Γ Therefore, this method is to use the leaves in the hollowed area to release the stress in the hollowing out process in the hollowed area = 1 to reduce the defect and reduce the trimming step; the substrate yield and Saves the cost of the substrate and other effects. [Embodiment] [Embodiment] The following is to match the cymbals and the system of each embodiment with a pattern " The core of each pattern; It is shown that the physical structure and actual appearance of the strip according to the actual number of miles and the structure should not be more than the figure: ::: The substrate The strip of the substrate of the present invention is provided for at least half of the gorge: ^ = pieces For subsequent use, the film, bonding wire, and glue are used.] = = The component is molded on the substrate strip #. This substrate strip is used for soap sealing to make a plurality of ball grid array semiconductor sealers. · Examples:, pieces.
1237353 五、發明說明(6) 下面結合第5 A圖至第5 E圖說明本發明之基板條片製法 的第一實施例,此一實施例係針對第3圖所示之習知基板 條片,以解決該習知技術之問題。 首先,如第5 A圖所示,製備一基板條片3 1,其係為一 從整片基材上切割而成的長條狀基板條片,該基板條片3 1 係為一單層、雙層或多層之印刷電路板,其係於由?1?_4樹 脂、BT( Bismaleimide Triazine)樹脂、聚亞醯胺樹脂 等塑膠材料製成之芯層的至少一表面上佈設多條導電跡線 (Conductive Traces),且具有一對長邊31 2及一對與兩 長邊3 1 2垂直之短邊3 1 3,該基板條片3 1表面係以縱向封裝 線3 2 2、3 2 3 ( P a c k a g e L i n e)預先劃分出複數個彼此鄰接 的方形基板單元3 2,且相鄰基板單元3 2之間係另開設有一 與該短邊3 1 3平行之孔槽3 3,同時,該孔槽3 3邊緣係與相 鄰兩基板單元3 2縱側之封裝線3 2 2、3 2 3重合,以作為該兩 相鄰基板單元3 2共用之應力釋放孔槽3 3。 接著,參閱第5 B圖,係對該基板條片3 1上之複數個基 板單元3 2分別進行檢測,例如對該基板單元3 2上之導電跡 線進行短路測試,以藉檢測結果區分出該基板條片3丨上的 不良基板單元32b與良好基板單元32a;隨後,如第5C圖所 示’沿該剪裁線而自該基板條片3 1上裁切下該不良基板單 元3 2b ’且亦一併自該基板條片31上裁切下與該不良基板 單元3 2 b之上下邊緣相鄰的兩相對矩形長條區域3 3,以使 該基板條片3 1上形成一鏤空區域,其中,該鏤空區域係包 括一相對於該不良基板單元32b位置的第一鏤空區域34,1237353 V. Description of the invention (6) The first embodiment of the substrate strip manufacturing method of the present invention will be described below with reference to FIGS. 5A to 5E. This embodiment is directed to the conventional substrate strip shown in FIG. To solve the problems of the conventional technology. First, as shown in FIG. 5A, a substrate strip 31 is prepared, which is a long substrate strip cut from a whole substrate, and the substrate strip 3 1 is a single layer. , Double-layer or multi-layer printed circuit board 1? _4 Resin, BT (Bismaleimide Triazine) resin, polyurethane resin and other plastic materials, at least one surface of the core layer is provided with a plurality of conductive traces (Conductive Traces), and has a pair of long sides 31 2 and A pair of short sides 3 1 3 perpendicular to the two long sides 3 1 2. The surface of the substrate strip 3 1 is divided in advance by a plurality of vertical packaging lines 3 2 2, 3 2 3 (Package Line). A square substrate unit 3 2 is provided with a hole slot 3 3 parallel to the short side 3 1 3 between adjacent substrate units 3 2. At the same time, the edge of the hole slot 3 3 is adjacent to two adjacent substrate units 3 2 The packaging lines 3 2 2 and 3 2 3 on the vertical side are overlapped to serve as stress relief holes 33 shared by the two adjacent substrate units 32. Next, referring to FIG. 5B, the plurality of substrate units 32 on the substrate strip 31 are tested separately, for example, a short-circuit test is performed on the conductive traces on the substrate unit 32 to distinguish them by the test results. The defective substrate unit 32b and the good substrate unit 32a on the substrate strip 3; then, as shown in FIG. 5C, 'the defective substrate unit 3 2b is cut from the substrate strip 31 along the cutting line' Also, two relatively rectangular long regions 3 3 adjacent to the upper and lower edges of the defective substrate unit 3 2 b are cut from the substrate strip 31 to form a hollow area on the substrate strip 31. Wherein, the hollowed-out area includes a first hollowed-out area 34 relative to the position of the defective substrate unit 32b,
]7513石夕品.ptd 第15頁 1237353 五、發明說明(7) 以及與該第一鏤空區域34相連通的兩第二鏤 第一鏤空區域3 6亦即該兩矩形長條區域3 3之 該第一鏤空區域36之長邊係與其所相鄰之第 之邊緣相互平行,且該第二鏤空區域36之長 所相鄰之第一鏤空區域34之邊緣長度;此外 區域3 4上未連接第二鏤空區域3 6之平行兩邊 兩側之應力釋放孔槽3 3連通。 接著,如第5D圖所示,於其他之基板條 裁切下:良好基板單元37,該良好基板單元 係與該第一鏤空區域3 4相同,以將該良好基 入該第Γ鏤空區域34中,而成為該原先基板 分,該嵌合完成後之結構係如第5£圖所示, 入之良好基板單兀3 7係藉該基板條片3丨的左 與該基板條片31緊密接合且共平面,而在此 由於該基板條片3 1係預先於該第一鏤空區域 兩第二鏤空區域36,故而將可藉該與良好基 之弟一鐘空區域3 6 ’釋放嵌合過程中施加於 上之應力,從而避免該基板條片3丨受播壓而 基板條片3 1之品質良率並發揮本發明之功效 因此,通過本發明之第一實施例所製成 即如第5 E圖所示’包括一邊框與複數個彼此 板單元3 2 a ’且該複數個良好基板單元3 2 a係 邊框所圍置出的複數個區域中;以及一嵌合 元3 7,係嵌合於該邊框所圍置出的其中一區 空區域3 6,該 位置;同時, —鏤空區域34 邊係略短於其 ’該第一鏤空 則係分別與其 片(未圖示)上 3 7之形狀尺寸 板單元3 7嵌合 條片3 1之一部 此時,該嵌合 右兩邊側3 8而 嵌合過程中, 3 4之周圍預留 板單元3 7相鄰 該基板條片3 1 變形,提升該 〇 之基板條片3 1 鄰接的良好基 分別形成於該 之良好基板單 域中,且該邊] 7513 石 夕 品 .ptd Page 151237353 V. Description of the invention (7) and the two second hollow first hollowed areas 3 6 communicating with the first hollowed area 34, that is, the two rectangular long areas 3 3 The long sides of the first hollowed-out area 36 are parallel to each other, and the length of the edges of the first hollowed-out area 34 adjacent to the length of the second hollowed-out area 36; The stress relief holes 3 3 on the two sides of the two hollowed-out areas 36 are in communication. Next, as shown in FIG. 5D, cut out other substrate strips: a good substrate unit 37, which is the same as the first hollowed area 34, so as to base the good into the first hollowed area 34 In the original substrate, the structure after the mating is as shown in Fig. 5; a good substrate unit 37 is connected to the substrate strip 31 by the left of the substrate strip 3 丨. They are joined and coplanar, and since the substrate strip 3 1 is in advance the two hollowed areas 36 in the first hollowed area 36, it is possible to release the fitting with the one-hollowed area 3 6 ′ of the good base brother. The stress applied to the substrate during the process, so as to avoid the substrate strip 3 丨 from being subjected to broadcast pressure and the quality yield of the substrate strip 31 and exert the effect of the present invention. Therefore, the first embodiment of the present invention can be made as As shown in FIG. 5E, 'including a frame and a plurality of mutual plate units 3 2 a', and the plurality of good substrate units 3 2 a are surrounded by a plurality of areas surrounded by a frame; and a mosaic element 37, It is fitted in one of the empty areas 36, surrounded by the frame, at this position; , —The side of the hollowed out area 34 is slightly shorter than its side. The first hollowed out area is a part of the shape and size plate unit 3 7 fitted on the strip 3 (not shown). The right and left sides 3 and 8 are fitted, and during the fitting process, the plate units 3 7 around 3 4 are deformed adjacent to the substrate strip 3 1, and the good substrates adjacent to the substrate strip 3 1 that promotes 0 are formed in the Good substrate in a single domain, and the edge
17513 矽品.ptd 第16頁 1237353 五、發明說明(8) 一~ 框上與該嵌合良好基板單元37之上下邊緣相鄰的區域上係 開設有矩形長條鏤空區域36,同時,該嵌合良好基板單元 37之形狀尺寸係與該複數個良好基板單元32a相同。 第土實施例:_ 本發明之第二實施例即如第6A、6B圖所示,其係針對 第2圖所不之習知基板條片,解決習知技術之問題,且為 便於說明,結構相同或相似的元件仍選用前述實施例之標 號,並且該相同或相似之結構將不再予以重復說明。 首先’該第二實施例係如第6A圖所示,檢測該基板條 片31上之複數個基板單元並選取其中之不良基板單元32b 後,而自該基板條片3 1上沿預定之裁切線裁切下該不良基 板單元3 2 b,以一併於該基板條片3 1上形成一第一鏤空區 域34以及與該不良基板單元32b之四邊相鄰接的矩形長條 區域3 3 ’其中’該四個矩形長條區域3 3將於該基板條片3 1 上之對應位置分別留下四個與該第一鏤空區域^相連通的 第二鏤空區域3 6,此即本第二實施例與第一實施例不同之 處,而可藉由多出的兩第二鏤空區域36釋放兩側之嵌合應 力,同時,該第二鏤空區域3 6之長邊係與其所相鄰之第一 鏤空區域34的邊緣相互平行,且該第二鏤空區域^之長邊 係略短方;其所相鄰之弟一鐘空區域3 4之邊緣長产·其次, 再如第6B圖所示,另外選取一良好基板單元3 7,且該良好 基板單元3 7之形狀尺寸係與該第一鏤空區域3 4相同,以將 該良好基板單元3 7嵌合入該第一鏤空區域中34,並藉該四 個第二鐘空區域3 6避免散合過程中該基板條片3 1因各方向17513 硅 品 .ptd Page 16 1237353 V. Description of the invention (8) A ~ A rectangular long hollow area 36 is provided on the frame adjacent to the upper and lower edges of the well-fitted substrate unit 37. At the same time, the embedded The shape and size of the good substrate unit 37 are the same as those of the plurality of good substrate units 32a. The first embodiment: _ The second embodiment of the present invention is shown in Figs. 6A and 6B, which is directed to the conventional substrate strips not shown in Fig. 2 to solve the problems of the conventional technology, and for the convenience of explanation, Elements having the same or similar structure still use the reference numerals of the foregoing embodiments, and the same or similar structures will not be described repeatedly. First, as shown in FIG. 6A, the second embodiment detects a plurality of substrate units on the substrate strip 31 and selects a defective substrate unit 32b, and then cuts a predetermined cut from the substrate strip 31. Cut the defective substrate unit 3 2 b with a tangent line to form a first hollow area 34 and a rectangular strip area 3 3 ′ adjacent to the four sides of the defective substrate unit 32 b together on the substrate strip 31. Among them, the four rectangular long strip areas 3 3 will leave four second hollow areas 3 6 corresponding to the first hollow area ^ at the corresponding positions on the substrate strip 3 1, and this is the second The embodiment is different from the first embodiment in that the two sides of the second hollowed-out area 36 can release the fitting stress on both sides. At the same time, the long side of the second hollowed-out area 36 is adjacent to it. The edges of the first hollowed-out area 34 are parallel to each other, and the long sides of the second hollowed-out area ^ are slightly shorter; the edge of the neighboring brother Yizhongkong area 34 is long. Second, as shown in FIG. 6B In addition, a good substrate unit 37 is selected, and the shape and dimensions of the good substrate unit 37 are selected. Same as the first hollowed-out area 34, to fit the good substrate unit 37 into the first hollowed-out area 34, and to use the four second clock-empty areas 36 to avoid the substrate strip during the disengagement process 3 1 due to various directions
]7513石夕品.ptd 第17頁 1237353 五、發明說明(9) 應力所致的擠壓變形。 第三實施例: 此外,本發明之第二鏤空區域3 6的形狀、數量與分佈 亦可根據實際需要而作不同的改變和調整,並非僅以前述 兩實施例所揭示者為限,例如第7圖所示之本發明第三實 施例,亦係針對第2圖所示之習知基板條片,而於裁切下 其不良基板單元時,一併於其每一邊均分別裁切下兩矩形 區域,以令該第一鏤空區域的各邊均分別鄰接有兩第二鏤 空區域3 6,而可藉該八個第二鏤空區域3 6分別釋放各個方 向的嵌合應力;此外,除了數量之變化外,該第二鏤空區 域3 6之形狀尺寸亦非僅限於矩形,而可為其他諸如三角 形、正方形、半圓形等實施態樣,亦同樣可發揮本發明之 功效。 因此,藉由本發明之裁切與第二鏤空區域設計,將可 避免該基板條片於嵌合過程中的變形與平面度降低之缺 陷,以省去修邊步驟,同時,亦兼具有提高基板產量與節 省基板成本等功效。 上述實施例僅例示性說明本發明之原理及其功效,而 非用於限制本發明。任何熟習此項技藝之人士均可在不違 背本發明之精神及範疇下,對上述實施例進行修飾與改 變。因此,本發明之權利保護範圍,應如後述之申請專利 範圍所列。] 7513 石 夕 品 .ptd Page 17 1237353 V. Description of the invention (9) Extrusion deformation caused by stress. Third embodiment: In addition, the shape, number, and distribution of the second hollowed-out areas 36 of the present invention can also be changed and adjusted differently according to actual needs, not limited to those disclosed in the foregoing two embodiments. The third embodiment of the present invention shown in FIG. 7 is also directed to the conventional substrate strip shown in FIG. 2. When the defective substrate unit is cut, two pieces are cut on each side together. The rectangular area, so that each side of the first hollowed-out area is adjacent to two second hollowed-out areas 36, respectively, and the eight second hollowed-out areas 36 can be used to release the fitting stress in each direction; In addition to the changes, the shape and size of the second hollowed area 36 is not limited to a rectangle, but may be other embodiments such as a triangle, a square, a semicircle, and the like, and can also exert the effect of the present invention. Therefore, by the cutting and the second hollowed-out area design of the present invention, the defects of deformation and flatness of the substrate strip during the fitting process can be avoided, so as to eliminate the trimming step, and also improve the Substrate yield and save substrate cost. The above-mentioned embodiments merely illustrate the principle of the present invention and its effects, but are not intended to limit the present invention. Any person skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.
]75]3石夕品.ptd 第18頁 1237353 圖式簡單說明 【圖式簡單說明】 第1圖係為習知球栅陣列半導體封裝件之剖視圖; 第2圖係一習知基板條片之上視圖; 第3圖係另一習知基板條片之上視圖; 第4A至4C圖係習知上用以替換不良基板單元之基板條 片(第3圖)製法流程示意圖; 第5 A至5 E圖係本發明第一實施例之基板條片製法的流 程示意圖; 第6 A及6 B圖係本發明第二實施例之基板條片製法的流 程不意圖,以及 第7圖係本發明第三實施例之基板條片上視圖。 10 半 導 體 封 裝 件 11 基 板 條 片 112 長 邊 113 短 邊 12 基 板 單 元 12a 良 好 基 板 單 元 12b 不 良 基 板 單 元 122 封 裝 線 123 封 裝 線 13 孔 槽 14 良 好 基 板 單 元 15 鏤 空 區 域 2 晶 片 21 基 板 條 片 210 基 板 連 接 部 22 基 板 單 元 23 孔 槽 24 封 裝 線 3 銲 線 31 基 板 條 片 312 長 邊 313 短 邊 32 基 板 單 元 32a 良 好 基 板 單 元] 75] 3 石 夕 品 .ptd Page 18 1237353 Brief Description of Drawings [Simplified Description of Drawings] Figure 1 is a cross-sectional view of a conventional ball grid array semiconductor package; Figure 2 is a top view of a conventional substrate strip Figure 3 is a top view of another conventional substrate strip; Figures 4A to 4C are schematic diagrams of a conventional method for manufacturing a substrate strip (Figure 3) to replace a defective substrate unit; Figures 5 A to 5 E FIG. 6 is a schematic flow chart of a substrate strip manufacturing method according to the first embodiment of the present invention; FIGS. 6A and 6B are not intended to illustrate the flow of the substrate strip manufacturing method according to the second embodiment of the present invention, and FIG. 7 is the third embodiment of the present invention. Top view of the substrate strip of the embodiment. 10 Semiconductor package 11 Substrate strip 112 Long side 113 Short side 12 Substrate unit 12a Good substrate unit 12b Bad substrate unit 122 Packaging line 123 Packaging line 13 Hole slot 14 Good substrate unit 15 Hollow area 2 Wafer 21 Substrate strip 210 Substrate connection Section 22 Substrate unit 23 Slot 24 Encapsulation line 3 Welding wire 31 Substrate strip 312 Long side 313 Short side 32 Substrate unit 32a Good substrate unit
17513石夕品.ptd 第19頁 123735317513 Shi Xipin.ptd Page 19 1237353
175]3石夕品.ptd 第20頁175] 3 Shi Xipin.ptd Page 20
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW092136487A TWI237353B (en) | 2003-12-23 | 2003-12-23 | Substrate strip for increasing yield and method for fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW092136487A TWI237353B (en) | 2003-12-23 | 2003-12-23 | Substrate strip for increasing yield and method for fabricating the same |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200522283A TW200522283A (en) | 2005-07-01 |
TWI237353B true TWI237353B (en) | 2005-08-01 |
Family
ID=36821420
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092136487A TWI237353B (en) | 2003-12-23 | 2003-12-23 | Substrate strip for increasing yield and method for fabricating the same |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI237353B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101226915B (en) * | 2008-02-05 | 2010-09-29 | 日月光半导体(上海)股份有限公司 | Package substrate and manufacturing method thereof |
CN103167745A (en) * | 2011-12-09 | 2013-06-19 | 富葵精密组件(深圳)有限公司 | Continuous circuit board and manufacture method thereof |
-
2003
- 2003-12-23 TW TW092136487A patent/TWI237353B/en not_active IP Right Cessation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101226915B (en) * | 2008-02-05 | 2010-09-29 | 日月光半导体(上海)股份有限公司 | Package substrate and manufacturing method thereof |
CN103167745A (en) * | 2011-12-09 | 2013-06-19 | 富葵精密组件(深圳)有限公司 | Continuous circuit board and manufacture method thereof |
CN103167745B (en) * | 2011-12-09 | 2015-09-30 | 富葵精密组件(深圳)有限公司 | The manufacture method of connecting sheet circuit board and connecting sheet circuit board |
Also Published As
Publication number | Publication date |
---|---|
TW200522283A (en) | 2005-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI394238B (en) | Small form factor molded memory card and method thereof | |
US7378300B2 (en) | Integrated circuit package system | |
US20070114654A1 (en) | Stackable semiconductor package and method for its fabrication | |
US20080067634A1 (en) | Reduced footprint packaged microelectronic components and methods for manufacturing such microelectronic components | |
TW201230212A (en) | Manufacturing method of semiconductor device | |
CN101009271A (en) | Stack of semiconductor chips | |
US20040166605A1 (en) | Fabrication method of semiconductor integrated circuit device | |
JP4454608B2 (en) | Manufacturing method of semiconductor integrated circuit device | |
CN102054714B (en) | Method for manufacturing packaging structure | |
TWI237353B (en) | Substrate strip for increasing yield and method for fabricating the same | |
TWI421993B (en) | Quad flat no-lead package, method for forming the same, and metal plate for forming the package | |
JP2001237258A (en) | Method of manufacturing semiconductor device | |
CN103000599A (en) | Flip chip package structure and method for forming the same | |
TWI618160B (en) | Semiconductor device having a multi-wafer stack, a gold bond wire, and a fan-out type RDL layer Low cost manufacturing method | |
CN101442012B (en) | Model sealing and cutting method for small window and formed encapsulation conformation | |
KR100618541B1 (en) | Method for fabricating multi-chip semiconductor package | |
CN108364917A (en) | Semiconductor package and its packaging method | |
CN207676902U (en) | A kind of high reliability array locking-type lead frame | |
TWI244167B (en) | Semiconductor package and method thereof | |
TWI620279B (en) | Separated pre-formed package lead frame and manufacturing method thereof | |
CN206584920U (en) | Separate type preform packaging conductor frame | |
US7632720B2 (en) | Method of manufacturing a semiconductor device | |
CN100592506C (en) | Non-planar base grate and method for semiconductor package using same | |
CN101609803A (en) | The validation test method of semiconductor packaging process with and the shared substrate that uses | |
CN101853833B (en) | Embedded basic island and multi-convex point basic island lead framework and first-etching last-plating method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |