CN103137618A - 局部载流子寿命减少 - Google Patents

局部载流子寿命减少 Download PDF

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CN103137618A
CN103137618A CN2012104483609A CN201210448360A CN103137618A CN 103137618 A CN103137618 A CN 103137618A CN 2012104483609 A CN2012104483609 A CN 2012104483609A CN 201210448360 A CN201210448360 A CN 201210448360A CN 103137618 A CN103137618 A CN 103137618A
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power device
substrate
capture feature
isolated part
semiconductor structure
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CN103137618B (zh
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亚历克斯·卡尔尼茨基
姚智文
蔡军
柳瑞兴
段孝勤
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体结构，包括：衬底；位于衬底中的第一功率器件和第二功率器件；位于第一和第二功率器件之间的至少一个隔离部件；以及位于衬底中的邻接至少一个隔离部件的俘获部件。本发明提供了局部载流子寿命减少的结构及其形成方法。

Description

局部载流子寿命减少
技术领域
本发明大体上涉及半导体结构，更具体而言，涉及高电压器件和形成高电压器件的方法。
背景技术
高电压器件或功率器件常常被用作电力电子电路或集成电路中的开关或整流器。一些常见的功率器件是功率二极管、晶闸管、功率金属氧化物半导体场效应晶体管(MOSFET)、双极结型晶体管(BJT)和绝缘栅双极型晶体管(IGBT)。功率二极管或MOSFET采用与其对应的低功率器件相似的原则进行运行，但其能够携带更大量的电流，并通常能够在关闭状态中支持更大的反向偏置电压。通过减小各种部件的尺寸，高电压器件逐渐制造得越来越小。随着尺寸的减小，高电压器件变得越来越容易受到由邻近的器件之间的不需要的串扰引起的邻近的功率器件之间的干扰。在许多情况下，串扰是由横向寄生衬底电流引起的。
邻近的功率器件之间的干扰也表现为在功率器件之间形成闭锁电路的寄生结构的形成。闭锁电路是短路的一种，其在寄生结构之间具有低阻抗路径。通常，寄生结构等同于晶闸管、充当彼此相邻堆叠的PNP和NPN晶体管的PNPN结构。在闭锁期间，当其中一个晶体管导电时，另一个晶体管也开始导电。只要结构是正向偏置的并且有电流通过，他们双方就能彼此保持饱和。因此，闭锁电路能够导致产品出现故障。
电子设计包括闭锁尺度(latchup rule)，其描述了用于减少或消除器件之间形成闭锁的可能性的两个器件之间(有时是两个隔离结构之间)的最小距离。高电压器件使用较大的闭锁尺度。如果保持不变，该最小距离阻止包含高电压器件的电路尺寸的显著缩小。因此，需要不断探索更小的抗闭锁或防闭锁半导体结构设计及其制造方法。
发明内容
一方面，本发明提供了一种半导体结构，所述半导体结构包括：衬底；第一功率器件和第二功率器件，都位于所述衬底中；至少一个隔离部件，位于所述第一功率器件和所述第二功率器件之间；以及俘获部件，位于所述衬底中，所述俘获部件邻接所述至少一个隔离部件。
在所述的半导体结构中，所述俘获部件包含锗、碳、或惰性气体中的至少一种。
在所述的半导体结构中，所述至少一个隔离部件是两个深沟槽隔离(DTI)部件。
在所述的半导体结构中，所述俘获部件邻接所述至少一个隔离部件的底部。
在所述的半导体结构中，所述俘获部件的一部分位于所述第一功率器件或所述第二功率器件的下面。
在所述的半导体结构中，所述俘获部件设置在所述衬底的一部分和所述至少一个隔离部件之间。
在所述的半导体结构中，所述俘获部件的一部分设置在所述第一功率器件和所述至少一个隔离部件之间。
在所述的半导体结构中，所述俘获部件的一部分设置在所述第二功率器件和所述至少一个隔离部件之间。
在所述的半导体结构中，所述第一功率器件和所述第二功率器件是不同的功率器件。
在所述的半导体结构中，所述俘获部件是硅锗。
另一方面，本发明提供了一种形成半导体结构的方法，所述方法包括：提供硅衬底；在所述衬底内蚀刻沟槽；在所述衬底中邻接所述沟槽形成俘获部件；用隔离材料填充所述沟槽；以及在邻近所述沟槽的所述硅衬底中形成功率器件；其中，在两个邻近沟槽的相对侧上形成至少两个功率器件。
在所述的方法中，在所述衬底中邻接所述沟槽形成俘获部件包括：采用大于约1E14/cm2的注入剂量，将锗、碳、或惰性气体中的至少一种注入所述沟槽的底部。
在所述的方法中，所述注入剂量是约5E14/cm2或更高。
在所述的方法中，在所述衬底中邻接所述沟槽形成俘获部件包括：在所述沟槽中沉积衬垫；蚀刻所述衬垫的底部，以暴露出位于所述沟槽的所述底部的所述衬底；在所述沟槽的所述底部外延生长俘获部件，其中，所述俘获部件包含锗、锗硅、碳、或这些的组合。
在所述的方法中，所述衬垫是热氧化硅。
在所述的方法中，所述碳是石墨烯。
在所述的方法中，在所述衬底中邻接所述沟槽形成俘获部件包括：采用原子层沉积(ALD)或等离子体辅助化学汽相沉积(PA-CVD)在所述沟槽中沉积锗、硅锗、或碳的共形层。
所述的方法进一步包括对所述共形层进行退火。
在所述的方法中，所述共形层的厚度小于约5nm。
又一方面，本发明还提供了一种半导体结构，包括：衬底；第一功率器件和第二功率器件，位于所述衬底的上面，所述第一功率器件和所述第二功率器件具有高电压阱(HVW)区域，所述HVW区域具有n-型导电性；拾取区域，位于所述第一功率器件和所述第二功率器件之间；第一隔离部件，位于所述第一功率器件和所述拾取区域之间；第一俘获部件，邻接所述第一隔离部件；第二隔离部件，位于所述第二功率器件和所述拾取区域之间；以及第二俘获部件，邻接所述第二隔离部件；其中，与所述第一功率器件和所述第二功率器件相比，所述第一俘获部件和所述第二俘获部件更深得延伸到衬底中。
附图说明
根据以下详细的描述和附图更好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1是根据本发明的一个或多个实施例的形成具有抗闭锁结构的半导体结构的方法的流程图。
图2至图9C是根据图1的方法的一些实施例的在各个制造阶段的半导体结构的截面图。
图10至图11是根据本发明的一个实施例的模拟双极结型晶体管(BJT)的半导体结构的电气性能的标绘图。
具体实施方式
下面详细讨论本发明示例性实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所论述的具体实施例仅仅是示例性的，而不用于限制本发明的范围。
图1是根据本发明的一个或多个实施例的形成具有抗闭锁结构的半导体结构的方法101的流程图。在操作103中，提供了衬底。衬底通常是硅衬底，但也可以是其他半导体衬底，诸如碳化硅(SiC)、二氧化硅、氧化铝、蓝宝石、锗、砷化镓(GaAs)、或磷化铟(InP)。这些衬底作为在其上设置功率器件(诸如，晶体管和二极管)的基础。
在操作105中，在衬底内蚀刻沟槽。沟槽可以是浅沟槽或深沟槽，并被用于在后续操作中形成隔离部件。沟槽将衬底划分为用于功率器件的不同区域，这些区域紧挨着沟槽形成。在一些实施例中，在功率器件之间采用一个沟槽。在其他实施例中，在功率器件之间采用两个或更多个沟槽。根据沟槽的形状，可以采用各种技术来蚀刻沟槽。在衬底表面上形成图案，以保护将要在其上形成功率器件的部分。图案可以作为介电层形成，随后，对该介电层进行蚀刻以形成图案。图案也可以由光刻胶形成。对于浅沟槽，光刻胶图案通常以栅格/网状图案覆盖部分衬底。然后，对衬底进行干式蚀刻或湿式蚀刻。对于深沟槽，采用等离子体辅助干式蚀刻。可以采用干式蚀刻或湿式蚀刻方法蚀刻浅沟槽。不同的蚀刻方法和工艺参数允许形成不同的沟槽形状。例如，工艺参数可以允许过蚀刻的发生，其中除了未受保护的衬底之外，还可以蚀刻受保护的衬底的边缘部分。与偏置衬底一起采用等离子体蚀刻技术引导蚀刻剂以法线角(normal angle)进入衬底中，从而形成无太多过蚀刻的基本上垂直的沟槽。由于工艺的局限性，通常会形成具有小的倾斜角的深沟槽，从而使沟槽的底部小于开口。对于浅沟槽，沟槽的形状可以大致呈长方形。沟槽的尺寸和形状取决于功率器件之间所需的隔离件的数量。当在功率器件之间形成两个沟槽时，闭锁尺度决定了两个沟槽的最近边缘之间的最小距离。换句话说，较小的闭锁尺度允许功率器件更紧密地设置在一起，并且可以在管芯中封装更多的器件。
在操作107中，在衬底中邻接沟槽形成俘获部件(trapping feature)。俘获部件在器件运行期间减少载流子寿命。在俘获部件处复合或吸收用于形成寄生衬底电流的空穴和电子。俘获部件的加入提高了隔离部件的有效性，并且降低了在功率器件之间的干扰和形成闭锁电路的可能性。因此，闭锁尺度可以更小些，而不增加闭锁的可能性。
在沟槽的底部周围、在侧壁上和底部作为沟槽衬里的衬底中、或在侧壁上的部分衬底形成俘获部件。对衬底的一部分进行处理，使其具有用于形成俘获部件的其他材料。该其他材料包括锗、碳或惰性气体种类。在各个实施例中，结合其他材料在提供额外的载流子复合部位的衬底中引入晶格缺陷和应力。
一方面，通过用一种或多种掺杂物注入沟槽的底部形成俘获部件。可以使用锗、碳和惰性气体种类，诸如氮气、氖气、氩气、氪气、或氙气。在一个实例中，掺杂物种类是锗，注入剂量大于约1E14/cm2或约5E14/cm2或更大，以使掺杂浓度介于约1E16/cm3至约1E21/cm3之间。注入系统在电场中使离子加速并且将离子注入到衬底中。每个单个的离子通过碰撞在衬底晶体结构中产生许多点缺陷，诸如空位和间隙。空位是未被原子占据的晶格点：在这种情况下，离子与靶原子碰撞，导致大量能量转移到靶原子，从而使其离开它的晶位。然后，这种靶原子自身成为衬底中的射弹，并且可以引发连续的碰撞事件。当这种原子(或原始离子本身)静止时，形成间隙，但是发现在晶格中无驻留的未用空间。这些点缺陷可以迁移并彼此聚集，从而导致位错环和其他缺陷。最后，离子可以置换晶体结构中的原子，但由于所使用的离子与衬底的材料不同，其产生的晶格常数与原始晶格常数不一样。这种差异引发了应力。
注入使衬底中形成了浓度分布轮廓，从而形成俘获部件。在注入之后，可以在直到1000摄氏度的温度下对衬底进行退火。俘获部件具有大于沟槽的底部的印记(footprint)，并且俘获部件深至少10nm，并且可以最多深至几微米。例如，峰值密度可以是约10nm，并且长尾为至少1微米。
另一方面，可以采用选择性外延在沟槽底部生长俘获部件。首先，通过共形衬垫层保护沟槽的侧壁。衬垫层是介电材料，诸如热沉积的氧化硅或原子层氧化硅或氮化硅。然后，蚀刻衬垫层的底部区域，以暴露出衬底。然后，从底部区域外延生长俘获部件。俘获部件可以是锗、硅锗或石墨烯(碳的同素异形体)。在这方面，形成的俘获部件可以是数纳米厚。在选择性外延工艺之后，可以对衬底进行退火。
又一方面，可以采用化学汽相沉积工艺在沟槽中的所有表面上形成俘获部件。在一些实施例中，原子层沉积(ALD)工艺可以形成非常薄且共形的材料层，其可以是几个原子厚(几埃)。重复ALD工艺可以形成直到数纳米的共形层。ALD可以沉积锗、硅锗或碳。也可以采用等离子体辅助(PA)或等离子体增强(PE)CVD来沉积共形层，但是比ALD沉积的共形层厚。可以采用PACVD沉积非晶碳。形成共形层之后，在直到约1000摄氏度的高温中对衬底进行退火。
返回参考图1，在操作109中，用隔离材料填充沟槽。隔离材料通常是采用高密度等离子体(HDP)CVD沉积的氧化硅。采用HDPCVD通过同时沉积和蚀刻在具有高纵横比的沟槽中沉积。在将材料沉积到沟槽的底部中时，等离子体刻蚀保持悬垂在沟槽的开口，以防止开口闭合。一旦沟槽填充完毕，在操作111中，在邻近沟槽的硅衬底中形成功率器件。根据功率器件的类型，器件通常涉及多步注入，以将不同的材料注入到衬底中，从而在衬底上方形成各种电极和栅极，并且可以包括形成额外的隔离部件。功率器件通常是晶体管或二极管。功率晶体管包括高电子迁移率晶体管(HEMT)、功率MOSFET和双极结型晶体管(BJT)。功率二极管包括肖特基二极管(Schottky diodes)和其他高电压二极管。
图2至图9C示出了根据图1的方法的一些实施例的在各个制造阶段的半导体结构的截面图。在图2中，硅衬底201具有p-型导电性。p-型衬底可以通过将p-型掺杂物注入在裸硅晶圆中形成，或通过在绝缘体上硅加工过程中结合p-型掺杂物形成。在p-型衬底上，限定、蚀刻并填充浅沟槽隔离部件203。然后，使晶圆平坦化。然后采用CVD工艺在衬底和STI结构203上方沉积焊盘氧化物层205和氮化硅层207，以便在随后的加工过程中保护衬底201的表面。
图3示出了位于衬底201上方的经图案化的光刻胶层303。在衬底201内蚀刻沟槽301。如所示，沟槽301具有高纵横比，并且被用于形成深沟槽隔离(DTI)部件。注意，虽然示出的是穿过STI部件203形成的DTI，但是可以不使用STI部件。在一些实施例中，STI部件203可以仅位于沟槽的一侧上或被省略掉。在又一些实施例中，邻接STI部件203而不是DTI形成俘获部件。
图4A、图4B、和图4C示出了采用不同的工艺形成不同类型的俘获部件。图4A示出了其中采用注入工艺形成俘获部件的各个实施例。在图4A中，如能量箭头403所示，将锗、碳或惰性气体种类注入到沟槽301的底部内，且光刻胶层303位于适当的位置。注入在衬底部分中邻接沟槽301的底部形成俘获部件401。根据注入的纵横比和角度，可以在接近底部的侧壁中以及沿着沟槽301的侧壁注入一些材料。根据某些实施例，注入角度保持为法线角或保持笔直地进入沟槽301的底部内，从而使大多数的注入种类最初设置在衬底201中的沟槽底部的正下方。在注入工艺之后，可以对衬底进行退火，并且由于注入种类的扩散/迁移可以形成略大一些的俘获区域411。虽然图4A示出了俘获部件401和411的特定椭圆形，但是根据注入的能量、注入的角度、以及随后是否对衬底进行退火和在什么温度下进行退火，实际的俘获部件可以具有不同的形状。例如，较高的注入能量可以使注入种类更深地穿透到衬底中，从而产生不同的椭圆形。更长时间或更高温度的退火工艺会增加迁移。
在其中功率器件之间只使用一个隔离部件的某些实施例中，可以形成更大的但并不干扰功率器件的运行的俘获部件。在其中功率器件之间使用两个隔离部件的其他实施例中，俘获部件不能大到可以覆盖功率器件之间的拾取区域(pick-up region，始动区域)。
图4B示出了其中沿着沟槽的侧壁和底部通过CVD形成俘获部件405的各个实施例。首先，通过以共形方式将锗、锗硅、或碳的薄层沉积到沟槽301的侧壁和底部上来形成俘获部件405。然后，在高于500摄氏度、约700摄氏度、介于约700摄氏度至约1000度摄氏度之间、或约1000摄氏度或更高的较高的温度下对该薄层进行退火。退火通过将膜种类结合到硅衬底中增加俘获部件405的厚度。沉积的厚度可以处于几纳米至十几纳米且直至100纳米的量级。退火后，俘获部件405可以处于几十纳米直至200多纳米的量级。
图4C示出了其中在沟槽301的底部中选择性地外延生长俘获部件407的各个实施例。首先，沿着侧壁和底部在沟槽301中沉积共形衬垫409。该衬垫是不生长外延膜的介电材料。衬垫通常是氧化硅，并且可以是其他电介质，诸如氮化硅。然后，通过蚀刻去除底部中的部分衬垫，从而暴露出下面的衬底。根据蚀刻方法，可以去除更多或更少的衬垫材料。
然后，在暴露出来的衬底上实施外延工艺以生长锗外延膜、硅锗外延膜或石墨烯膜。该工艺可以是金属有机CVD(MOCVD)、金属有机汽相外延(MOVPE)、等离子体增强CVD(PECVD)、远程等离子体增强CVD(RP-CVD)、分子束外延(MBE)、氢化物汽相外延(HVPE)、氯化物汽相外延(C1-VPE)、和/或液相外延(LPE)。可以对膜进行退火，以促进锗或碳的扩散/迁移。注意，结合图4A至4C描述的各种退火步骤不需要在紧接形成俘获部件之后的制造工艺中实施。因为在制造过程中可以对衬底进行多次退火，所以，可以稍后实施退火步骤。
如图5中所示，在形成初始俘获部件之后，去除(剥离)光刻胶层，然后，填充沟槽301以形成隔离部件501。通常用氧化硅填充沟槽，氧化硅采用高密度等离子体(HDP)CVD进行沉积。图5示出了隔离部件501以及位于隔离部件501上方的场中的氧化硅层503。为了确保适当填充且无空隙，沉积更多的材料。在填充沟槽之前去除光刻胶层，以减小沟槽的纵横比，并且使其更易于填充，但是在填充沟槽之前的去除并不是必须的。也可以稍后去除光刻胶。
图6示出了在使衬底平坦化以去除多余的氧化硅层503之后的结构。平坦化采用化学机械抛光工艺来实施，并且可以包括其他湿蚀刻操作。然后，如图7中所示，通过蚀刻或剥离去除氮化硅和焊盘氧化物层，从而暴露出STI部件203之间的衬底。在之前或随后的步骤中，可以故意或非故意掺杂STI部件203，导致各种STI部件203形成相同或不同的掺杂分布。由于这个原因，在以下附图中用不同的底纹描绘每个STI部件203。
图8示出的是被分成器件区域801、803和805的衬底201。在一些实施例中，功率器件被两个隔离部件501分开。在这些实施例中，在区域801和805中形成功率器件，而在区域803中不形成功率器件。例如，在区域801和805中形成高电压n-阱(HVNW)，以及在区域803中可以形成高电压p-阱(HVPW)。在区域801和805中的HVNW上方形成功率器件，而在区域803的HVPW上方不形成功率器件。区域803可以被用于衬底电流拾取(pickup，始动)。各个区域801和805中的器件不需要是同一类型的功率器件。区域803的大小与隔离部件501之间的闭锁尺度的最小距离相对应。俘获部件401的使用启用较小的闭锁尺度，从而可以减小不包括任何器件的区域803的尺寸。区域803的减小允许在相同大小的区域中设置更多的功率器件。
在其他实施例中，在区域801、803和805中的每一个中形成功率器件。各个区域801、803和805中的器件不需要是同一类型的功率器件。将具有俘获部件401的隔离部件501设置在邻近的功率器件之间。在这些实施例中，俘获部件401充分减少了载流子寿命，并因而减少了衬底电流，从而在一些邻近区域之间不使用拾取区域。然而，一些始动区域仍然可以用于功率器件的集群中。例如，拾取区域可以被4个或更多个功率器件包围。
在一个实施例中，具有隔离部件和俘获部件的拾取区域可以被4个或更多个功率器件包围。虽然每个功率器件通过至少一个隔离部件和俘获部件与邻近的功率器件分开，但是只有一个分离的隔离部件邻接拾取区域。换句话说，每个功率器件区域只与一个拾取区域相邻，以及它的其余的邻近区域是其他功率器件。
图9A、图9B、和图9C示出了根据本发明的各个实施例的示例结构。图9A示出了经注入的俘获部件的实施例，其中俘获部件401形成在隔离部件501的底部的下方。区域801和803是功率器件，具有栅极901和905以及掺杂区域907和909。拾取电极903通过介电层911与区域803中的衬底相连接。注意，在该实例中，功率器件区域比俘获部件401浅。较深的俘获部件401减少了俘获部件401干扰功率器件运行的可能性。
图9B示出了共形俘获部件的实施例，其中俘获部件405形成在隔离部件501的侧壁和底部上。区域801和803是功率器件，具有栅极901和905以及掺杂区域907和909。拾取电极903通过介电层911与区域803中的衬底相连接。
图9C示出了外延俘获部件实施例，其中俘获部件407在隔离部件501的底部上生长。区域801和803是功率器件，具有栅极901和905以及掺杂区域907和909。拾取电极903通过介电层911与区域803中的衬底相连接。
模拟根据图9A的半导体结构，以测定使用不同的锗注入剂量时电流寿命的变化。在该模拟中，区域801和805是高电压n-阱(HVNW)，以及区域803是高电压p-阱(HVPW)。区域801上方的区域907是p型掺杂的；以及区域805上方的区域909也是p型掺杂的。形成位于区域801和805上方的多晶硅栅极结构。在区域803的上方形成拾取结构。用区域801作为发射极、区域803作为基极、以及区域805作为集电极来模拟BJT。模拟提供了4种不同的锗注入方案：1E14/cm2、5E14/cm2、1E15/cm2，以及不注入锗。
图10示出了在不同的基极到发射极电压(Vbe)下的每个方案的空穴电流。在基极和发射极之间(即，在区域803和801之间)的空穴电流模拟漏衬底电流。线1001对应于不注入锗的方案。线1003对应于注入浓度为1E14/cm2的方案。线1005对应于注入浓度为5E14/cm2的方案。线1007对应于注入浓度为1E15/cm2的方案。图10表明空穴电流在线1001和线1003之间显著减少，在线1003和线1005之间少量减少，以及在线1005和1007之间略微减少。在每个Vbe下，基极和发射极之间的空穴电流随注入剂量的增加而减少。
图11示出了不同注入剂量之间的关系。图11示出了对寿命退化率的复合率(复合/cm3s)。图11中的每个数据点对应于图10中的线所示的一个方案。换句话说，因为载流子寿命没有变化，所以线1001对应于图11中的0％寿命退化数据点。因为载流子寿命减少了约50％，所以线1003对应于图11中的约50％寿命退化数据点。图11表明在任何注入剂量下，复合率随着具有俘获部件而显著降低。然而，随着注入剂量的增加，复合率没有进一步显著降低。模拟数据表明1E14/cm2的标称剂量有效地减少了衬底电流并且降低了复合率，但是5E14/cm2更有效。由另一剂量1E15/cm2获得了小且或许不明显的额外的收益。总的来说，该模拟证明了俘获部件在减少衬底电流方面是有效的。衬底电流的减少降低了形成闭锁电路的可能性。
虽然已详细地介绍了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变、替换和更改。虽然通过高电压功率器件描述了各个实施例，但是俘获部件也可以用于不是功率器件的隔离器件。器件在较低的电压下运行时具有较低的衬底电流，因而形成闭锁电路的可能性较小。然而，随着临界尺寸继续缩小，较好的隔离部件减少器件之间的干扰，并且在足够小的临界尺寸下，具有俘获部件的隔离部件能够提高电路的性能。
虽然模拟示出了用于一个实施例的注入剂量，本领域的技术人员将能够发现本发明不同实施例的最佳浓度和工艺参数。例如，可以对具有不同的厚度和不同的硅到锗浓度的外延俘获部件进行模拟或测试。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明的公开内容将很容易理解，根据本发明可以应用现有的或今后开发的用于执行与本文所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种半导体结构，包括：
衬底；
第一功率器件和第二功率器件，都位于所述衬底中；
至少一个隔离部件，位于所述第一功率器件和所述第二功率器件之间；以及
俘获部件，位于所述衬底中，所述俘获部件邻接所述至少一个隔离部件。
2.根据权利要求1所述的半导体结构，其中，所述俘获部件包含锗、碳、或惰性气体中的至少一种。
3.根据权利要求1所述的半导体结构，其中，所述至少一个隔离部件是两个深沟槽隔离(DTI)部件。
4.根据权利要求1所述的半导体结构，其中，所述俘获部件邻接所述至少一个隔离部件的底部。
5.根据权利要求1所述的半导体结构，其中，所述俘获部件设置在所述衬底的一部分和所述至少一个隔离部件之间；
在所述第一功率器件和所述至少一个隔离部件之间；或
设置在所述第二功率器件和所述至少一个隔离部件之间。
6.根据权利要求1所述的半导体结构，其中，所述第一功率器件和所述第二功率器件是不同的功率器件。
7.根据权利要求1所述的半导体结构，其中，所述俘获部件是硅锗。
8.一种形成半导体结构的方法，该方法包括：
提供硅衬底；
在所述衬底内蚀刻沟槽；
在所述衬底中邻接所述沟槽形成俘获部件；
用隔离材料填充所述沟槽；以及
在邻近所述沟槽的所述硅衬底中形成功率器件；其中，在两个邻近沟槽的相对侧上形成至少两个功率器件。
9.根据权利要求8所述的方法，其中，在所述衬底中邻接所述沟槽形成俘获部件包括：
采用大于约1E14/cm2的注入剂量，将锗、碳、或惰性气体中的至少一种注入所述沟槽的底部。
10.一种半导体结构，包括：
衬底；
第一功率器件和第二功率器件，位于所述衬底的上面，所述第一功率器件和所述第二功率器件具有高电压阱(HVW)区域，所述HVW区域具有n-型导电性；
拾取区域，位于所述第一功率器件和所述第二功率器件之间；
第一隔离部件，位于所述第一功率器件和所述拾取区域之间；
第一俘获部件，邻接所述第一隔离部件；
第二隔离部件，位于所述第二功率器件和所述拾取区域之间；以及
第二俘获部件，邻接所述第二隔离部件；
其中，与所述第一功率器件和所述第二功率器件相比，所述第一俘获部件和所述第二俘获部件更深得延伸到衬底中。
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