CN103128650A - Chemical mechanical polishing method - Google Patents
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- CN103128650A CN103128650A CN2011103977700A CN201110397770A CN103128650A CN 103128650 A CN103128650 A CN 103128650A CN 2011103977700 A CN2011103977700 A CN 2011103977700A CN 201110397770 A CN201110397770 A CN 201110397770A CN 103128650 A CN103128650 A CN 103128650A
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Abstract
The invention relates to a chemical mechanical polishing method. The chemical mechanical polishing method is characterized by comprising the steps that a dielectric layer is subjected to first-stage chemical mechanical polishing so that the dielectric layer is preliminarily smoothed; a repair layer is deposited on the surface of the dielectric layer which is preliminarily smoothed; and the repair layer is subjected to second-stage chemical mechanical polishing so that the part, higher than the surface of the dielectric layer, of the repair layer is removed. The chemical mechanical polishing method is little in consumption, short in flow and high in efficiency, and has quite high operability. Through the chemical mechanical polishing method, the sinking phenomenon caused by a general chemical mechanical polishing method can be greatly reduced, the circuit malfunction of a semiconductor device is effectively avoided, and therefore the scrapping situation of wafers is reduced, and the yield of products is greatly improved.
Description
Technical field
The present invention relates to semiconductor device fabrication process, relate more specifically to a kind of cmp (CMP) method.
Background technology
The integrated level of current electronic devices and components is more and more higher, for example Pentium IV is with regard to integrated more than 4,000 ten thousand transistors, these transistors can be worked, will apply certain voltage or electric current to each transistor, and this just need to couple together so many transistor by lead-in wire.Yet, multiple transistor so be coupled together, plane routing is impossible, is merely able to adopt three-dimensional wiring or multilayer wiring.In the process of making these lines, can become between layers uneven so that can not the multilayer superposition.Therefore, planarization is a step very important in semiconductor devices manufacturing process.
At present in semiconductor device fabrication process, be widely used cmp (CMP, Chemical Mechanical Polishing) carry out planarization, grinding agent and grinding pad cooperative mechanical abrasive action that its utilization has corrosiveness polish the unnecessary any material (for example oxide dielectric layer, barrier layer etc.) in each layer surface in the multi-layer framework semiconductor devices, thereby realize global planarization, reduce the layout restriction, promote distribution density.Generally speaking, lapping device comprises grinding table (being covered with grinding pad on it) and grinding head, and semiconductor wafer is fixed on grinding head, and grinding pad is in the face of wanting the semiconductor wafer of polishing.When grinding semiconductor chip, grinding pad with certain pressure contact and grinding semiconductor chip, thereby makes its surface be tending towards smooth under the existence of the lapping liquid with polishing particles.
With regard to the whole manufacturing process of semiconductor devices, generally first carried out thin film deposition processes before the flatening process of for example cmp.Yet present technique is easier to be mingled with the particulate material that may be the protrusion state in the film that deposits, and if such particle is removed by integral body in follow-up chemical mechanical planarization process, will be inevitably produce depression on this layer surface.Schematically show this depression in Fig. 1, by label 10 indications.In follow-up technique, these depressions will be filled by other materials, and then affect the circuit normal operation, and this is present problem very fatal in semiconductor device fabrication process.
At present, produce depression in the situation that run into, mainly contain two kinds of processing methods: a kind of is direct clearance, and this will be take the loss yield as cost; Another kind is that wafer is directly scrapped, and this is very uneconomic way.Thus, desirable is the generation of as far as possible avoiding this depression.
Summary of the invention
In view of this, the object of the invention is to effectively reduce the generation of described depression by the technical process of improving cmp, thereby greatly improve the yield of product.
For achieving the above object, the invention provides a kind of chemical and mechanical grinding method, described method comprises: dielectric layer is carried out the phase I cmp so that its preliminary planarization; Dielectric layer surface deposition repair layer in preliminary planarization; And described repair layer is carried out the second stage cmp with the part removal higher than described dielectric layer surface with described repair layer.
Preferably, the part higher than described dielectric layer surface of described repair layer is removed with the grinding rate that sets in advance by controlling milling time during described second stage cmp.
Preferably, described repair layer higher than the thickness of the part on described dielectric layer surface between 3000 ~ 5000.
Preferably, all comprise main grinding steps and edge grinding step at described the first and second stage cmps, and identical grinding plate rotating speed, grinding head rotating speed, snap ring pressure, diaphragm pressure and inner sicula pressure are set during the cmp in described the first and second stages.
Preferably, in described main grinding steps, described grinding plate rotating speed is set to about 93 rev/mins, described grinding head rotating speed is set to about 87 rev/mins, described snap ring pressure is arranged in 5.22 ~ 6.38 pounds/square inchs of scopes, described diaphragm pressure is arranged in 5.4 ~ 6.6 pounds/square inchs of scopes, and described inner sicula pressure is arranged in 4.05 ~ 4.95 pounds/square inchs of scopes; And in described edge grinding step, described grinding plate rotating speed is set to about 93 rev/mins, described grinding head rotating speed is set to about 87 rev/mins, described snap ring pressure is arranged in 2.7 ~ 3.3 pounds/square inchs of scopes, described diaphragm pressure is arranged in 5.4 ~ 6.6 pounds/square inchs of scopes, and described inner sicula pressure is arranged in 0.9 ~ 1.1 pounds/square inch of scope.
Preferably, repair layer is made of the material identical with described dielectric layer.
In some embodiments of the invention, described dielectric layer is before-metal medium layer (pmd layer).
In some embodiments of the invention, described dielectric layer is silicon dioxide layer.
Preferably, the silica that generates by deposition ethyl orthosilicate TEOS and oxygen reaction generates described repair layer.
In some embodiments of the invention, adopt ion enhanced chemical vapor deposition pecvd process to deposit described repair layer.
In other embodiment of the present invention, adopt high density plasma chemical vapor deposition HDPCVD technique to deposit described repair layer.
Method provided by the present invention consumes little, and flow process is short, and efficient is high and have a very strong operability.By adopting method of the present invention can greatly reduce the depression that is caused by general cmp, effectively avoided the circuit malfunction of semiconductor devices, thus the situation that the minimizing wafer is scrapped and the yield that greatly improves product.
Description of drawings
Below with reference to drawings and Examples, technical scheme of the present invention is described in further detail.
Wherein: Fig. 1 schematically shows the depression that is caused by the CMP process.
Fig. 2 a and 2b schematically show the basic structure of CMP device commonly used.
Fig. 3 shows the flow chart according to CMP method of the present invention.
Fig. 4 schematically shows the dielectric layer surface of using CMP method provided by the present invention to obtain.
The specific embodiment
For above-mentioned purpose of the present invention, feature and advantage are become apparent more, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.Need to prove, each structure in accompanying drawing is schematic rather than determinate, so that those of ordinary skills can understand principle of the present invention best, it is not necessarily drawn in proportion.
The basic structure of CMP device commonly used has been shown in Fig. 2 a.This CMP device mainly comprises grinding plate (platen) 10, is placed in above grinding plate and can synchronizes with it grinding pad (polishing pad) 20, grinding head (polishing head) 30, slurry conveyer (Slurry delivery) 90 that rotates.Slurry conveyer 90 is in order to supply ground slurry 91 to grinding pad 20, and wafer 40 is scheduled to be fixed on grinding head 30, and it is placed between grinding head 30 and grinding pad 20; Grinding head 30 applies certain downforce (downforce) to wafer 40, and rotates and swing (sweep) relative to grinding pad, thereby realizes the CMP process.
Fig. 2 b is depicted as the basic structure schematic diagram of grinding head.Normally, grinding head comprises snap ring (Retaining Ring is hereinafter to be referred as " RR "), diaphragm (Membrane is hereinafter to be referred as " MM ") and inner sicula (Inner Tube is hereinafter to be referred as " IT ").In the grinding head structure of Fig. 2 b illustrated embodiment, RR 31 is used for locating fixed wafer 40 at process of lapping, and it is exerted pressure to RR 31 by pressurized air chamber 311, and the control of this pressure realizes by the gas pressure control device that the 3rd wireway 343 connects; MM 32 is used for direct bearing wafer 40 and provides downforce to control grinding rate to wafer 40, it exerts pressure, passes to wafer 40 by pressurized air chamber 321 to MM 32, and the control of this pressure realizes by the gas pressure control device that the second wireway 342 connects; Whether IT 33 locates for detection of wafer 40 and controls uniformity to the downforce of wafer 40 in conjunction with MM institute applied pressure.In the process of CMP, wafer 40 is placed between MM 32 and grinding pad 20, realizes the process of lapping of each step by the pressure parameter of controlling RR 31, MM 32, IT 33.
As mentioning in background technology, utilize so typical CMP device will inevitably produce depression on its handled layer of surface after carrying out the CMP processing procedure, and method provided by the present invention will take full advantage of the described depression in characteristics efficient quick ground of CMP technique on the basis that does not change the existing apparatus structure.Specifically describe CMP method provided by the present invention below in conjunction with Fig. 3.
As shown in Figure 3, at first carry out phase I CMP in step S110.This phase I CMP is similar to CMP processing procedure of the prior art substantially, and it generally can comprise preparation process, main grinding steps and edge grinding step before grinding.
In preparation process before grinding, generally at first need wafer to be ground is packed in grinding head, make and treat that flour milling operationally contacts with grinding pad.Then, the action that grinding head begins to prepare and grinds, the simultaneous grinding platform can begin to rotate by set rate, and the slurry conveyer also can begin to begin to carry slurry by predetermined amount of flow.
In main grinding steps, mainly the middle body of wafer ground.When applying downforce, it mainly puts on the middle body of grinding head, thereby the pressure between the middle body of wafer and grinding pad is relatively large.In the process of grinding, the middle body grinding rate is relatively very fast, and the marginal portion is relatively very slow.Grinding head can the oscillating motion on grinding pad of sine curve track, and simultaneous grinding head High Rotation Speed on grinding pad rotatablely moves and two actions of sine curve track swing motion are carried out simultaneously.Generally can stop this main process of lapping by time cessation method, terminating point detection method etc.
Edge grinding step and main grinding steps are similar.The difference mainly be, in the edge grinding step, mainly the marginal portion of wafer is ground, when applying downforce, it mainly puts on the edge of grinding head, thus the pressure between the marginal portion of wafer and grinding pad is relatively large.When edge grinding stopped, the lapped face of wafer can reach predetermined flatness requirement substantially.
It will be appreciated that, those skilled in the art understand each details step of basic CMP processing procedure, here will not do one by one and describe in detail.
Then, in step S120, deposit repair layer on the dielectric layer surface through phase I CMP.
In practice, this repair layer preferably can be made of the material identical with dielectric layer, and the depression that is produced by phase I CMP like this will be filled with the material identical with this dielectric layer itself, but this is not necessarily necessary.The below illustrates the preferred embodiment of this repair layer of deposition take the before-metal medium layer (pmd layer) that is made of silica as example.
In the situation that dielectric layer is silicon dioxide layer, can generate described repair layer by the silica that deposition ethyl orthosilicate TEOS and oxygen reaction generate.Ethyl orthosilicate claims again the tetraethoxy-silicane product, and english abbreviation is TEOS, and molecular formula can be write Si (OC
2H
5)
4, generally can be by low pressure pyrolysis tetraethoxysilance and under middle temperature deposit silica interlayer dielectric layer, the method have preferably film thickness uniformity and repeatability and cost lower.The method coordinates ion enhanced chemical vapor deposition pecvd process to carry out usually, PECVD makes by microwave or radio frequency etc. the gas ionization that contains the film composed atom, form plasma in the part, and the plasma chemical activity is very strong, be easy to react, thereby deposit desired film on substrate.The various process conditions of PECVD are very suitable for coming with TEOS the processing procedure of deposition of silica.In addition, also can deposit silica as repair layer with TEOS by high density plasma chemical vapor deposition HDPCVD technique.
For the silica dioxide medium layer, adopt the scheme of TEOS+PECVD/HDPCVD to be very beneficial for filling up of caving in, its reason is that this silica deposit process has good mobility and Step Coverage ability (step coverage).
Be only here that the purpose that is in example has been described for the selecting materials and manufacturing process of the repair layer of silica dioxide medium layer, but this not determinate.For the silica dioxide medium layer, also can adopt in this area other techniques of deposition medium layer material to make this repair layer.In addition, for the dielectric layer of the other materials except silica, also can utilize this area under similar concept in existing various technology deposit corresponding repair layer.
The thickness higher than the part on dielectric layer surface of the repair layer that deposits in step S12 can be controlled between 3000 ~ 5000, helping fully to fill depression, but can not cause the subsequent step of wasting time and energy.
Further, in step S130, the repair layer that deposits is carried out second stage CMP.The purpose of this second stage CMP is to remove into filling the dielectric layer material of depression additional deposition, to expose the surface of dielectric layer itself.Because CMP can make the surface that stays keep smooth when removing the redundancy deposition, the part that therefore only exceeds desired dielectric layer surface will be removed, and its lip-deep depression will fully be filled and led up.
As mentioning in step S120, the material that preferably deposition is identical with dielectric layer is as repair layer.In this case, preferably can adopt the time cessation method to finish this second stage CMP in step S130.That is to say, in the situation that preset the CMP grinding rate, the thickness higher than the part of dielectric layer according to repair layer namely needs the thickness of removed part to determine milling time.Then, control its termination by this milling time of technology controlling and process module count in the CMP device.It should be understood that and also can adopt additive method known in the art to realize the termination of this second stage CMP.
This second stage CMP can adopt the identical device that uses when carrying out phase I CMP, and preferably it can comprise and before the identical step of CMP process and parameter setting, comprises grinding plate rotating speed, grinding head rotating speed, snap ring pressure, diaphragm pressure and inner sicula pressure etc.According to one embodiment of present invention, can the grinding plate rotating speed all be remained about 93 rev/mins in main grinding steps and edge grinding step, and the grinding head rotating speed is remained about 87 rev/mins, slurry flow can be set to about 120 ml/min.Relatively, during snap ring pressure, diaphragm pressure and inner sicula pressure are arranged on respectively different scopes in main grinding and edge grinding step.For example in main grinding steps, snap ring pressure is arranged in 5.22 ~ 6.38 pounds/square inchs of scopes, and diaphragm pressure is arranged in 5.4 ~ 6.6 pounds/square inchs of scopes, and inner sicula pressure is arranged in 4.05 ~ 4.95 pounds/square inchs of scopes.In the edge grinding step, snap ring pressure is arranged in 2.7 ~ 3.3 pounds/square inchs of scopes, and diaphragm pressure is arranged in 5.4 ~ 6.6 pounds/square inchs of scopes, and inner sicula pressure is arranged in 0.9 ~ 1.1 pounds/square inch of scope.
Thus, can adopt identical equipment and process condition for the CMP process in former and later two stages included in the inventive method, therefore not need to increase too much extra manpower and materials and drop into, have very high business efficiency.
Fig. 4 schematically shows the dielectric layer surface of using CMP method provided by the present invention to obtain.In contrast to situation shown in Figure 1, can see that the dielectric surface that obtains through the CMP method that comprises two stages provided by the present invention can't see obvious depression.
More than enumerate some specific embodiments and illustrated in detail the present invention, these a few examples are only for explanation principle of the present invention and embodiment thereof, but not limitation of the present invention, without departing from the spirit and scope of the present invention, those of ordinary skill in the art can also make various distortion and improvement.Therefore all technical schemes that are equal to all should belong to category of the present invention and be limited by every claim of the present invention.
Claims (11)
1. a chemical and mechanical grinding method, is characterized in that, described method comprises:
Dielectric layer is carried out the phase I cmp so that its preliminary planarization;
Dielectric layer surface deposition repair layer in preliminary planarization; And
Described repair layer is carried out the second stage cmp with the part removal higher than described dielectric layer surface with described repair layer.
2. the method for claim 1, is characterized in that, wherein the part higher than described dielectric layer surface of described repair layer removed with the grinding rate that sets in advance by controlling milling time during described second stage cmp.
3. the method for claim 1, is characterized in that, wherein said repair layer higher than the thickness of the part on described dielectric layer surface between 3000 ~ 5000.
4. the method for claim 1, it is characterized in that, wherein all comprise main grinding steps and edge grinding step at described the first and second stage cmps, and identical grinding plate rotating speed, grinding head rotating speed, snap ring pressure, diaphragm pressure and inner sicula pressure are set during the cmp in described the first and second stages.
5. method as claimed in claim 4, it is characterized in that, wherein in described main grinding steps, described grinding plate rotating speed is set to about 93 rev/mins, described grinding head rotating speed is set to about 87 rev/mins, described snap ring pressure is arranged in 5.22 ~ 6.38 pounds/square inchs of scopes, and described diaphragm pressure is arranged in 5.4 ~ 6.6 pounds/square inchs of scopes, and described inner sicula pressure is arranged in 4.05 ~ 4.95 pounds/square inchs of scopes; And
In described edge grinding step, described grinding plate rotating speed is set to about 93 rev/mins, described grinding head rotating speed is set to about 87 rev/mins, described snap ring pressure is arranged in 2.7 ~ 3.3 pounds/square inchs of scopes, described diaphragm pressure is arranged in 5.4 ~ 6.6 pounds/square inchs of scopes, and described inner sicula pressure is arranged in 0.9 ~ 1.1 pounds/square inch of scope.
6. the method for claim 1, is characterized in that, described repair layer is made of the material identical with described dielectric layer.
7. the method for claim 1, is characterized in that, described dielectric layer is before-metal medium layer (pmd layer).
8. the method for claim 1, is characterized in that, wherein said dielectric layer is silicon dioxide layer.
9. method as claimed in claim 8, is characterized in that, the silica that wherein generates by deposition ethyl orthosilicate TEOS and oxygen reaction generates described repair layer.
10. method as claimed in claim 9, is characterized in that, wherein adopts ion enhanced chemical vapor deposition pecvd process to deposit described repair layer.
11. method as claimed in claim 9 is characterized in that, wherein adopts high density plasma chemical vapor deposition HDPCVD technique to deposit described repair layer.
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| CN105789131A (en) * | 2014-12-25 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof and electronic device |
| CN107398825A (en) * | 2017-08-28 | 2017-11-28 | 睿力集成电路有限公司 | The surface flat method and the semiconductor structure based on it of interlayer dielectric layer |
| CN110534423A (en) * | 2019-09-19 | 2019-12-03 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and preparation method thereof |
| CN116810619A (en) * | 2023-08-09 | 2023-09-29 | 哈尔滨工业大学 | Chemical mechanical polishing device based on microwave assistance and polishing CaF by using same 2 Method for wafer |
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Application publication date: 20130605 |