CN110534423A - Semiconductor devices and preparation method thereof - Google Patents

Semiconductor devices and preparation method thereof Download PDF

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Publication number
CN110534423A
CN110534423A CN201910884939.1A CN201910884939A CN110534423A CN 110534423 A CN110534423 A CN 110534423A CN 201910884939 A CN201910884939 A CN 201910884939A CN 110534423 A CN110534423 A CN 110534423A
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Prior art keywords
device substrate
edge
semiconductor devices
inactive area
substrate
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CN201910884939.1A
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CN110534423B (en
Inventor
杨一凡
高志强
张志军
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Wuhan Xinxin Integrated Circuit Co.,Ltd.
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02013Grinding, lapping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02021Edge treatment, chamfering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The present invention provides a kind of semiconductor devices and preparation method thereof, the described method includes: providing the device architecture after a bonding, device architecture after the bonding includes support substrate of the position in upper device substrate and position under, the device substrate includes effective coverage and the inactive area for surrounding the effective coverage, effective coverage and the inactive area of the device substrate is thinned, first time planarization is carried out to the device substrate effective coverage and inactive area;Trim the part of the inactive area of the device substrate, inactive area after forming trimming, inactive area behind effective coverage and trimming to the device substrate carries out second and planarizes, due to the device substrate thickness via twice planarization carry out it is thinned, and trimming technique is located between flatening process twice, so that influence of the planarization process for the device substrate becomes smaller, the caliper uniformity of the device substrate is improved, to improve the performance of semiconductor devices.

Description

Semiconductor devices and preparation method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors, and in particular to a kind of semiconductor devices and preparation method thereof.
Background technique
As the demand of the miniaturization of electronic component, lightweight and multifunction increasingly increases, integrated circuit is to chip Ultrathin requires higher and higher.MEMS (MEMS), imaging sensor (CIS:CMOS Image Sensor), laminated core Piece (stacked die), multi-chip package (Multi chip package) etc. all can ultra-thin core of the applied thickness less than 50 μm Piece.
In the prior art, ultra-thin chip is obtained by carrying out bonding and wafer thinning technique to semiconductor wafer mostly.For For non-EPI (epitaxial layer) substrate, reduction process generally comprises following steps: step S1, by device substrate and support substrate It is bonded;Step S2, the surface of the device substrate is thinned;Step S3, the marginal portion of the device substrate is trimmed;Step S4, the device substrate is planarized.Planarization process inevitably generates device substrate edge in step S4 Scuffing forms inclined surface, and when device substrate edge, lateral dimension is smaller, and planarization thickness thinning is thicker, and planarization process is to device The abraded area that part edges of substrate generates is bigger.However, after due to carrying out trimming technique to the device substrate edge, the device Part edges of substrate is largely removed, and the edge of the device substrate carries out flatening process relatively close to effective coverage later, Device substrate edge can be generated to scratch and form inclined surface, the caliper uniformity of device substrate is impacted, but also having The bad control of caliper uniformity for imitating region, finally impacts the performance of semiconductor devices.
Summary of the invention
Based on problem described above, the purpose of the present invention is to provide a kind of semiconductor devices and preparation method thereof, mention The caliper uniformity of high device substrate improves the performance of semiconductor devices.
To achieve the above object, the present invention provides a kind of production method of semiconductor devices, comprising:
Device architecture after providing a bonding, the device architecture after the bonding includes position in upper device substrate and position The support substrate under is set, the device substrate includes effective coverage and the inactive area for surrounding the effective coverage;
Effective coverage and the inactive area of the device substrate is thinned;
First time planarization is carried out to the device substrate effective coverage and inactive area;
The part of the inactive area of the device substrate is trimmed, the inactive area after forming trimming;
Inactive area behind effective coverage and trimming to the device substrate carries out second and planarizes.
Optionally, in the production method of the semiconductor devices, the inactive area includes first edge and the second side Edge, the first edge surround the effective coverage and form bonding face with support substrate, and the second edge surrounds described the One edge and with the not formed bonding face of support substrate, and the relatively described support substrate is hanging.
Optionally, in the production method of the semiconductor devices, the part of the inactive area of the device substrate is trimmed, Refer to the part for trimming the first edge of inactive area of the device substrate.
Optionally, in the production method of the semiconductor devices, the part of the inactive area of the device substrate is trimmed, The part support substrate is removed simultaneously.
Optionally, in the production method of the semiconductor devices, the method that forms the first edge and second edge It include: to trim the marginal portion of the device substrate to residue from bonding face side before bonding together to form the device architecture Segment thickness.
Optionally, in the production method of the semiconductor devices, before bonding together to form the device architecture, institute is formed After stating first edge and second edge, further includes: formed on the bonding face of the device substrate and the support substrate exhausted Edge layer.
Optionally, in the production method of the semiconductor devices, the material of the insulating layer after silica comprising nitrogenizing Silicon.
Optionally, in the production method of the semiconductor devices, the effective coverage of the device substrate and invalid is thinned Region is to the first edge for completely removing the device substrate.
Correspondingly, the present invention also provides a kind of semiconductor devices, using the production method of semiconductor devices as described above It is made, comprising:
Support substrate;And
Thinned device substrate in the support substrate.
Optionally, in the semiconductor devices, further includes: insulating layer is located at the support substrate and the device serves as a contrast Between bottom.
Compared with prior art, the device in semiconductor devices provided by the invention and preparation method thereof, after a bonding is provided Part structure is thinned after effective coverage and the inactive area of the device substrate, first to the device substrate effective coverage and Inactive area carries out first time planarization, then trims the part of the inactive area of the device substrate again, trims due to the Uneven part caused by primary planarization, then carries out second of planarization again, due to the device substrate thickness via Planarization carries out thinned twice, and trims technique and be located between flatening process twice, so that planarization process is for the device The influence of part substrate becomes smaller, and improves the caliper uniformity of the device substrate, to improve the performance of semiconductor devices.
Detailed description of the invention
Fig. 1~4 are each step structural schematic diagram of the production method of semiconductor device.
Fig. 5 is the flow chart of the production method of semiconductor devices provided by one embodiment of the invention.
Fig. 6~10 are each step structural representation of the production method of semiconductor devices provided by one embodiment of the invention Figure.
Figure 11 is trimming technique provided by one embodiment of the invention to the schematic diagram of device substrate edge effect.
Specific embodiment
Fig. 1~4 are each step structural schematic diagram of the production method of semiconductor device.Shown in please refer to figs. 1 to 4, The production method of semiconductor devices is specific as follows.
Firstly, please refer to shown in Fig. 1, provide a bonded wafer, bonded wafer include position upper device wafers 10 with Carrier wafer 20 of the position under.The first insulating layer 13 and the are also formed at device wafers 10 and 20 bonded interface of carrier wafer Two insulating layers 21.
The device wafers 10 include effective coverage 11 and the inactive area 12 for surrounding the effective coverage 11.The nothing Imitate region 12 include first edge 101 and second edge 102, the first edge 101 surround the effective coverage 11 and with load Body wafer 20 forms bonding face, the second edge 102 surround the first edge 101 and with carrier wafer 20 is not formed is bonded Face, and the relatively described carrier wafer 20 is hanging.
Then, it please refers to shown in Fig. 2, the effective coverage 11 that the device substrate 10 is thinned and inactive area 12 to going completely Except the second edge portion 102 of the device substrate 10.Then, it please refers to shown in Fig. 3, shears the invalid of the device substrate 10 Region 12, and remove the marginal portion of the part carrier wafer 20.Finally, please referring to shown in Fig. 4, to the device substrate 10 Effective coverage 11 and trimming after inactive area 12 planarized, but during being planarized, unavoidably Meeting overmastication is caused to the edge of the effective coverage 11 in the device wafers 10, while can be also exposed the load Overmastication is caused in the marginal portion of body wafer 20, thus causes influence to the caliper uniformity of device substrate, but also having The bad control of caliper uniformity for imitating region 11, finally impacts the performance of semiconductor devices.
In view of the above-mentioned problems, inventor provides a kind of manufacturing method of semiconductor device, comprising: the device after providing a bonding Structure, the device architecture after the bonding include support substrate of the position in upper device substrate and position under, the device Substrate includes effective coverage and the inactive area for surrounding the effective coverage;Effective coverage and the nothing of the device substrate is thinned Imitate region;First time planarization is carried out to the device substrate effective coverage and inactive area;Trim the nothing of the device substrate The part in region is imitated, the inactive area after forming trimming;The inactive area behind effective coverage and trimming to the device substrate Second is carried out to planarize.
Correspondingly, the present invention also provides a kind of semiconductor devices, using manufacturing method of semiconductor device system as described above It forms, comprising: support substrate, the thinned device substrate in the support substrate.
In semiconductor devices provided by the invention and preparation method thereof, device architecture after providing a bonding is thinned described After the effective coverage of device substrate and inactive area, first is carried out to the device substrate effective coverage and inactive area first The part of the inactive area of the device substrate is then trimmed in secondary planarization again, is trimmed caused by being planarized as first time Uneven part then carries out second of planarization again, since the thickness of the device substrate is subtracted via planarization twice It is thin, and trim technique and be located between flatening process twice, so that influence of the planarization process for the device substrate becomes smaller, The caliper uniformity of the device substrate is improved, to improve the performance of semiconductor devices.
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are done into one Walk explanation.Certainly the invention is not limited to the specific embodiment, and general replacement well known to those skilled in the art is also contained Lid is within the scope of the present invention.
Obviously, the described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on this hair Embodiment in bright, all other implementation obtained by those of ordinary skill in the art without making creative efforts Example, shall fall within the protection scope of the present invention.Secondly, the present invention has carried out detailed statement using schematic diagram, the present invention is being described in detail When example, for ease of description, schematic diagram is not partially enlarged in proportion to the general scale, should not be to this as restriction of the invention.
Fig. 5 is the flow chart of the production method of semiconductor devices provided by one embodiment of the invention.Fig. 6~10 are this hair Each step structural schematic diagram of the production method of semiconductor devices provided by a bright embodiment.Below in conjunction with attached drawing 5 and attached drawing 6 Each step of the production method of semiconductor devices is described in detail in~10 pairs of the present embodiment.
In the step s 100, it please refers to shown in Fig. 5 and Fig. 6, the device architecture after a bonding is provided, the device after the bonding Part structure includes support substrate 200 of the position in upper device substrate 100 and position under, and the device substrate 100 includes It imitates region 110 and surrounds the inactive area 120 of the effective coverage 110.The effective coverage 110 is used to form various devices Structure, and the region that the inactive area 120 is invalid as the device substrate can't be used to form device architecture, rear It can be partially removed in continuous technique.The inactive area 120 includes first edge 121 and second edge 122, the first edge 121 surround the effective coverage 110 and form bonding face with support substrate 200, and the second edge 122 surrounds first side Edge 121 and with the not formed bonding face of support substrate 200, and the support substrate 200 is hanging relatively.
The device substrate 100 is used to form the device layer of final products, therefore its material should be common semiconductor material Material, such as monocrystalline silicon, are also possible to other such as compound semiconductors.And support substrate 200 is due to only playing a supporting role, therefore Selection range is wider, and other than monocrystalline silicon and the compound semiconductor materials of routine, being also possible to sapphire even can be with It is metal substrate.In the embodiment of the present invention, the material of the device substrate 100 and the support substrate 200 is monocrystalline silicon.
The method for forming the first edge 121 and second edge 122 includes: before bonding, to repair from bonding face side The marginal portion of the device substrate 100 is cut to remainder thickness, to form the first edge 121 of the device substrate 100 With second edge 122.In embodiments of the present invention, pruning method includes that the marginal portion of a part is cut away using cutter Mechanical process.Cutter in vertical direction, horizontal direction or at an angle can trim the marginal portion.Another In embodiment, ability beam is can be used in pruning method, such as laser beam or focused ion book trim the marginal portion.Another In one embodiment, pruning method trims the marginal portion using selecting etch.The present invention for trimming specific method simultaneously It is not construed as limiting.
Trimming the marginal portion and forming first edge 121 and a reason of second edge 122 is to avoid edges broken Defect.Edges broken is likely to occur in bonding process when the device substrate 100 is bonded to the support substrate 200 When.In bonding process, the device substrate 100 is processed by skiving and is thinned, although most device substrate 100 is in skiving It is supported in the process by the support substrate 200, but the marginal portion of taper is not supported.Therefore, when the device substrate 100 by skiving, when pressure is applied to marginal portion, marginal portion fragmentation due to shortage intensity and supporting surface.In this hair In bright embodiment, marginal portion is trimmed to about to form the second edge 122 hanging with the support substrate 200, accordingly even when edge Fragmentation occurs in bonding, and the region of fragmentation will be also removed in reduction processing.When the marginal portion of the device substrate 100 A part in pruning method be removed after, the device substrate 100 present remaining new marginal portion, i.e. second edge 122, the second edge 122 is cut up during subsequent another trimming.
The first insulating layer 130 and second insulating layer are also formed between the device substrate 100 and the support substrate 200 210.The insulating layer 130 is used to form the insulating buried layer of final products with the insulating layer 210, and material can be silica Perhaps the growing method such as silicon nitride can be chemical meteorology deposition or thermal oxide.
It is (molten that the method that the device substrate 100 and the support substrate 200 are bonded can be anode linkage, Direct Bonding Melt bonding), low-temperature bonding, Intermediate Layer Bonding or binder bonding.Before bonding, need to the device substrate 100 with it is described Support substrate 200 is cleaned, to remove surface particle that may be present.It certainly, after bonding, can be with para-linkage face reality It applies annealing to reinforce, so that the firmness of bonding face can satisfy subsequent thinned and flatening process requirement.
In step s 200, it please refers to shown in Fig. 5 and Fig. 7, effective coverage 110 and the nothing of the device substrate 100 is thinned Imitate region 120.
In the present embodiment, mechanical grinding method and chemical thinning processes can be used.In mechanical grinding method, largely Substrate material is removed from the device substrate 100.Chemical thinning processes may include lithographic method well known in the art, to institute The application etching agent of device substrate 100 is stated so that the thickness of the device substrate 100 is thinned.
In the embodiment of the present invention, the device substrate 100 is thinned to the second edge for completely removing the device substrate 100 122, the effective coverage of the remaining device substrate 100 and first edge 121, the remaining thickness of the device substrate 100 can be with It is determined according to application type and design requirement.
In step S300, please refer to shown in Fig. 5 and Fig. 8, to 100 effective coverage 110 of device substrate and dead space Domain 120 carries out first time planarization.The device is thinned in step S200 using mechanical grinding method or chemical thinning processes Substrate 100 to certain thickness, the mechanical lapping and chemical etching etc. can all cause the surface of the device substrate 100 (to subtract Sake) it is uneven, influence the thinned effect of substrate bonding, it is therefore desirable to the rough surface of the device substrate 100 Carry out planarization process.Due to being carried out for the first time before inactive area 120 (the first edge part 121 after being thinned) is trimmed to about Planarization process, remains the inactive area 120 of device substrate 100, and planarization process generates device substrate edge and scratches shape At inclined surface occur mainly in inactive area 120, effective coverage 110 will not be damaged.
As shown in figure 8, in first time planarization process, can to the first edge 121 for being located at the device substrate 100 with And overmastication is caused in the marginal portion of the support substrate 200, leads to the first edge 121 and the support substrate 200 Marginal portion there is inclined surface, and effective coverage 110 is not by the damage of planarization process.
In step S400, please refers to shown in Fig. 5 and Fig. 9, trim the portion of the inactive area 120 of the device substrate 100 Point, the inactive area after forming trimming.
Specifically, trimming the part of the inactive area 120 of the device substrate 100, refer to the trimming device substrate 100 Inactive area first edge 121 part.
Preferably, the part of the inactive area of the device substrate 100 is trimmed, while removing the part support substrate 200。
Technique is trimmed to device substrate edge there are certain influence, Figure 11 is trimming provided by one embodiment of the invention Schematic diagram of the technique (Trim) to device substrate edge effect.As shown in figure 11, abscissa is wafer radius, and ordinate is grinding Amount, when the boundary Trim is 1.4mm, to the coverage at device substrate edge in 4mm or so, when the boundary Trim is 2.4mm, Coverage is in 5mm or so, and when the boundary Trim is 3mm, coverage is in 9mm or so, so trimming the device substrate portion When dividing inactive area, meeting retaining means substrate portions inactive area, the transitional region as subsequent technique.
In embodiments of the present invention, pruning method includes that the part first edge 121 and part are cut away using cutter The mechanical process of the support substrate 200.Cutter can be in vertical direction, horizontal direction or at an angle described in trimming First edge 121.In another embodiment, ability beam can be used in pruning method, such as laser beam or focused ion book are repaired Cut the first edge 121.In another embodiment, pruning method trims the first edge 121 using selecting etch.This Invention for trimming specific method and be not construed as limiting.
Inclined surface caused by being planarized in the previous step as first time is largely removed in this step, please be joined It examines shown in Fig. 8 and Fig. 9, the inclined surface in the support substrate 200 is removed, positioned at the nothing of the first edge 121 The inclined surface in effect region 120 is largely removed.After shearing procedure is placed in first time planarization surface, no It only can achieve the purpose of trimming, defect caused by the first time planarization can also be removed.
In step S500, effective coverage 110 shown in Fig. 5 and Figure 10, to the device substrate 100 and invalid is please referred to Region 120 carries out second and planarizes.When 120 lateral dimension of inactive area is smaller, planarization thickness thinning is thicker, at planarization It is bigger to manage the abraded area generated to effective coverage 110.The present invention trims technique and is located between flatening process twice, makes every time The thinned thickness of planarization reduces, and when planarizing for the first time, 120 lateral dimension of inactive area is larger, planarization thickness thinning compared with Small, planarization process generates the inclined surface for scratching and being formed to device substrate edge and occurs mainly in inactive area 120, effective district Domain 110 will not be damaged;After trimming technique, 120 lateral dimension of inactive area reduces but there are also parts to retain;Second flat When change, due to still remaining with partial invalidity region 120, planarization process generates the inclination for scratching and being formed to device substrate edge Surface still occurs mainly in inactive area 120, and effective coverage 110 will not be damaged, and is this time left after planarization process Inactive area 120 be also accordingly removed.
It is planarized by first time planarization with described second, so that the support substrate 100 reaches scheduled Thickness.It is planarized twice due to having, the thinned thickness of planarization reduces every time, also, tilts caused by planarizing for the first time Surface is removed by subsequent trimming technique, and therefore, the inclination angle of inclined surface caused by second of planarization can decline to a great extent, from And the flatness and homogeneity of the device substrate 100 are improved, while also improving the caliper uniformity of effective coverage 110.
In the production method of semiconductor devices provided by the invention, device substrate 100 and support substrate 200 are subjected to key It closes, is thinned after the back side of the device substrate 100, first time planarization is carried out to the back side of the device substrate 100 first, Then the first edge part for trimming the device substrate 100 again trims uneven portion caused by planarizing as first time Point, then carry out second of planarization again, due to the device substrate 100 thickness via twice planarization carry out it is thinned, and It trims technique to be located between flatening process twice, so that influence of the planarization process for the device substrate becomes smaller, improve The caliper uniformity of the device substrate, to improve the performance of semiconductor devices.
Correspondingly, the present invention also provides a kind of semiconductor devices, using the production method of semiconductor devices as described above It is made.It please refers to shown in Figure 10, the semiconductor devices includes:
Support substrate 200;And
Thinned device substrate 100 in the support substrate 200.
The device substrate 100 includes effective coverage 110 and the inactive area 120 for surrounding the effective coverage 110.
Preferably, further includes: insulating layer, between the support substrate 200 and the device substrate 100.The present invention In embodiment, the first insulating layer 130 and second insulating layer are formed between the support substrate 200 and the device substrate 100 210, first insulating layer 130 is close to the device substrate 100, and the second insulating layer 210 is close to the support substrate 200.The material of first insulating layer 130 and the second insulating layer 210 is including but not limited to silicon oxide or silicon nitride.
The thickness of the semiconductor devices being made using the production method of above-mentioned semiconductor devices, device substrate is equal One property is increased substantially, to improve the performance of semiconductor devices.
In conclusion in semiconductor devices provided by the invention and preparation method thereof, device architecture after a bonding is provided, It is thinned after effective coverage and the inactive area of the device substrate, first to the device substrate effective coverage and inactive area First time planarization is carried out, then trims the part of the inactive area of the device substrate again, is trimmed due to flat for the first time Uneven part caused by change, then carries out second of planarization again, since the thickness of the device substrate is via flat twice Change carries out thinned, and trims technique and is located at twice between flatening process, so that planarization process is for the device substrate Influence becomes smaller, and improves the caliper uniformity of the device substrate, to improve the performance of semiconductor devices.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims Range.

Claims (10)

1. a kind of production method of semiconductor devices characterized by comprising
Device architecture after providing a bonding, the device architecture after the bonding includes that position exists in upper device substrate and position Under support substrate, the device substrate includes effective coverage and the inactive area for surrounding the effective coverage;
Effective coverage and the inactive area of the device substrate is thinned;
First time planarization is carried out to the device substrate effective coverage and inactive area;
The part of the inactive area of the device substrate is trimmed, the inactive area after forming trimming;
Inactive area behind effective coverage and trimming to the device substrate carries out second and planarizes.
2. the production method of semiconductor devices as described in claim 1, which is characterized in that the inactive area includes the first side Edge and second edge, the first edge surround the effective coverage and form bonding face, the second edge with support substrate Surround the first edge and with the not formed bonding face of support substrate, and the relatively described support substrate is hanging.
3. the production method of semiconductor devices as claimed in claim 2, which is characterized in that trim the invalid of the device substrate The part in region refers to the part for trimming the first edge of inactive area of the device substrate.
4. the production method of semiconductor devices as claimed in claim 3, which is characterized in that trim the invalid of the device substrate The part in region, while removing the part support substrate.
5. the production method of semiconductor devices as claimed in claim 2, which is characterized in that form the first edge and second The method at edge includes: that the edge of the device substrate is trimmed from bonding face side before bonding together to form the device architecture Partially to remainder thickness.
6. the production method of semiconductor devices as claimed in claim 5, which is characterized in that bonding together to form the device architecture Before, it is formed after the first edge and second edge, further includes: in being bonded for the device substrate and the support substrate Insulating layer is formed on face.
7. the production method of semiconductor devices as claimed in claim 6, which is characterized in that the material of the insulating layer includes oxygen Silicon nitride after SiClx.
8. the production method of semiconductor devices as claimed in claim 2, which is characterized in that the effective of the device substrate is thinned Region and inactive area are to the second edge for completely removing the device substrate.
9. a kind of semiconductor devices is made of the production method of semiconductor devices such as according to any one of claims 1 to 8 It forms characterized by comprising
Support substrate;And
Thinned device substrate in the support substrate.
10. semiconductor devices as claimed in claim 9, which is characterized in that further include: insulating layer is located at the support substrate Between the device substrate.
CN201910884939.1A 2019-09-19 2019-09-19 Semiconductor device and method for manufacturing the same Active CN110534423B (en)

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Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101752296A (en) * 2008-12-10 2010-06-23 和舰科技(苏州)有限公司 Method for improving flatness of dielectric layer between metal layers
CN101853864A (en) * 2009-03-31 2010-10-06 台湾积体电路制造股份有限公司 Method of wafer bonding
US20100255682A1 (en) * 2009-04-01 2010-10-07 Tokyo Electron Limited Method for thinning a bonding wafer
CN102814725A (en) * 2011-06-08 2012-12-12 无锡华润上华半导体有限公司 Chemical mechanical polishing method
CN103094090A (en) * 2013-01-14 2013-05-08 陆伟 Method making back of wafer flat
CN103128650A (en) * 2011-12-05 2013-06-05 无锡华润上华科技有限公司 Chemical mechanical polishing method
CN103560105A (en) * 2013-11-22 2014-02-05 上海新傲科技股份有限公司 Method for manufacturing semiconductor substrate with smooth edge
KR20150092675A (en) * 2014-02-05 2015-08-13 삼성전자주식회사 Method for manufacturing of semiconductor devices
CN105070668A (en) * 2015-08-06 2015-11-18 武汉新芯集成电路制造有限公司 Wafer-level chip packaging method
CN105271108A (en) * 2015-09-10 2016-01-27 武汉新芯集成电路制造有限公司 Wafer bonding method
CN105390408A (en) * 2014-09-03 2016-03-09 中芯国际集成电路制造(上海)有限公司 Wafer structure and thinning method therefor
US20160276310A1 (en) * 2015-03-18 2016-09-22 Globalfoundries Singapore Pte. Ltd. Edge structure for backgrinding asymmetrical bonded wafer
CN106328546A (en) * 2015-07-09 2017-01-11 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic apparatus
KR20170015441A (en) * 2013-12-31 2017-02-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Interconnect structure for semiconductor devices
CN106571376A (en) * 2015-10-13 2017-04-19 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic device
CN108346657A (en) * 2017-01-25 2018-07-31 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and its manufacturing method
CN109545672A (en) * 2018-11-21 2019-03-29 德淮半导体有限公司 Wafer bonding method and bonded wafer
US20190221435A1 (en) * 2018-01-18 2019-07-18 Sumco Corporation Method of manufacturing bonded wafer

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101752296A (en) * 2008-12-10 2010-06-23 和舰科技(苏州)有限公司 Method for improving flatness of dielectric layer between metal layers
CN101853864A (en) * 2009-03-31 2010-10-06 台湾积体电路制造股份有限公司 Method of wafer bonding
US20100255682A1 (en) * 2009-04-01 2010-10-07 Tokyo Electron Limited Method for thinning a bonding wafer
CN102814725A (en) * 2011-06-08 2012-12-12 无锡华润上华半导体有限公司 Chemical mechanical polishing method
CN103128650A (en) * 2011-12-05 2013-06-05 无锡华润上华科技有限公司 Chemical mechanical polishing method
CN103094090A (en) * 2013-01-14 2013-05-08 陆伟 Method making back of wafer flat
CN103560105A (en) * 2013-11-22 2014-02-05 上海新傲科技股份有限公司 Method for manufacturing semiconductor substrate with smooth edge
KR20170015441A (en) * 2013-12-31 2017-02-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Interconnect structure for semiconductor devices
KR20150092675A (en) * 2014-02-05 2015-08-13 삼성전자주식회사 Method for manufacturing of semiconductor devices
CN105390408A (en) * 2014-09-03 2016-03-09 中芯国际集成电路制造(上海)有限公司 Wafer structure and thinning method therefor
US20160276310A1 (en) * 2015-03-18 2016-09-22 Globalfoundries Singapore Pte. Ltd. Edge structure for backgrinding asymmetrical bonded wafer
CN106328546A (en) * 2015-07-09 2017-01-11 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic apparatus
CN105070668A (en) * 2015-08-06 2015-11-18 武汉新芯集成电路制造有限公司 Wafer-level chip packaging method
CN105271108A (en) * 2015-09-10 2016-01-27 武汉新芯集成电路制造有限公司 Wafer bonding method
CN106571376A (en) * 2015-10-13 2017-04-19 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic device
CN108346657A (en) * 2017-01-25 2018-07-31 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and its manufacturing method
US20190221435A1 (en) * 2018-01-18 2019-07-18 Sumco Corporation Method of manufacturing bonded wafer
CN109545672A (en) * 2018-11-21 2019-03-29 德淮半导体有限公司 Wafer bonding method and bonded wafer

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