CN101329917A

CN101329917A - Method for repairing defect of DRAM

Info

Publication number: CN101329917A
Application number: CNA2007100424140A
Authority: CN
Inventors: 孙强; 陈宏璘; 仇圣棻; 阎海滨; 李友
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2007-06-22
Filing date: 2007-06-22
Publication date: 2008-12-24

Abstract

The invention relates to a defect remedying method for a dynamic random access memory (DRAM). The existing dynamic random-access memory has a problem that defects influence the performance of the dynamic random access memory. The defect remedying method for the dynamic random access memory of the invention comprises the steps that: an inner-layer dielectric layer is formed to be deposited on a DRAM unit; deep chemical mechanical polishing is carried out to the inner-layer dielectric layer; after the polishing process is carried out, a protective layer is deposited on the surface of the DRAM unit. By adopting the defect remedying method for the dynamic random access memory of the invention, the isolation of the defects from the outside world can be realized, and processes of exposal, development and etching etc., are not carried out to the defects, thereby increasing the yield of dynamic random access memory products.

Description

The defect mending method of dynamic RAM

Technical field

The present invention relates to the defect mending method of dynamic RAM, particularly utilize the defect mending method of chemical gaseous phase depositing process deposition protective seam.

Background technology

Dynamic RAM (Dynamic Random Access Memory, the back is called " DRAM ") be a kind of assembly that in computing machine, is used for temporarily preserving data, extremely important in computing machine, especially aspect raising Computer Storage ability and read-write.It at any time can be read and write, and speed is very fast, usually as operating system or other just at the ephemeral data storage medium of active program.

Usually, the DRAM storer is made up of thousands of DRAM unit, and there are a transistor and a capacitor of being controlled by transistor in each DRAM unit.And up to the present, the DRAM manufacturing process technology has reached 60 nanometer left and right horizontal, so very high to the requirements such as precision of making DRAM.If in making the DRAM process, external environment or other factors cause the DRAM unit to produce and damage or defective, will influence the performance of whole DRAM storer.

Figure 1A-1D shows the art methods that forms stacking-type (stack) DRAM that has capacitor.With reference to Figure 1A, it shows the DRAM unit 10 that is in the rough handling step when forming DRAM.DRAM unit 10 comprises substrate 12 as monocrystalline silicon and word line (wordline) 14,16, and nitride spacer 18 is formed at the side of word line 14,16.Diffusion region 20 in the substrate 12 is electrically connected between

word line

14,16 and by the transistor gate of

word line

14,16 compositions.Insulation course 22 has been formed on substrate 12 and the

word line

14,16 as boron-phosphorosilicate glass (BPSG).The polycrystalline connector (plug) 24 that mixes passes insulation course 22 with power supply contact between the diffusion region 20 between capacitor and word line 14 and 16.Contact openings 26 passes insulation course 22 and arrives connector 24.A large amount of mix and unbodied in fact or pseudo-crystal silicon layer 28 is deposited on insulation course 22 and the connector 24.

With reference to Figure 1B, according to art methods, unadulterated and unbodied or pseudo-crystal silicon layer 30 be deposited over doping and amorphous or pseudo-crystal silicon layer 28 on, DRAM unit 10 then by as 32 exposures of light such as ultraviolet ray with the crystal grain layer of formation silicon crystal, shown in Fig. 1 C.DRAM unit 10 then by thermal annealing so that unadulterated and unbodied or pseudo-crystal silicon layer 30 are converted to crystal structure, thermal treatment make polysilicon condense upon the crystal grain crystal on every side and form dome-type crystal grain (HSG) polysilicon 34, shown in Fig. 1 D.

Then, shown in Fig. 1 E, in temperature approximately with Low Pressure Chemical Vapor Deposition (LPCVD) Under ℃, deposition one polysilicon layer 36 on dome-type grained polysilicon 34, utilize high density plasma chemical vapor deposition method (HDPCVD) that part inner layer dielectric layer (ILD) 38 is deposited on the zone that contact openings 26 neutralizes between two capacitors then, utilize general chemical vapour deposition technique (CVD) part inner layer dielectric layer 38 to be deposited on the surface of DRAM unit again, but the defective 40 as Fig. 1 F sometimes can appear in the above-mentioned deposition process, by analysis, this defective 40 is a micro dust particle defective (particle defect).Utilize normal chemical Mechanical Polishing Technique (CMP) that leveling is carried out on the surface of DRAM unit 10.After the leveling, this micro dust particle defective 40 also has part residual, becomes marks on surface 41 after chemically mechanical polishing, shown in Fig. 1 G.DRAM proceeds the unit little shadow, shown in Fig. 1 H, at first apply one deck photoresistance 42 at the DRAM cell surface, wherein this marks on surface 41 can cause the photoresistance 42 in little shadow (Photo) processing procedure process to cover insufficient (poorcoating), as having a no photoresistance district 43 directly over the marks on surface 41, thereby in subsequent etch (Etch) processing procedure, produce pothole 44.According to the requirement of interconnection circuit, some interconnect level are set again at last.But, influenced the performance of interconnection circuit, whole DRAM storer cisco unity malfunction because the existence of this pothole 44 is disturbed or short circuit interconnection circuit generation up and down.

Can eliminate the influence of this defective or pothole so be necessary a kind of technology or method to the interconnection circuit of dynamic RAM.

Summary of the invention

The object of the present invention is to provide a kind of defect mending method of dynamic RAM, can eliminate the influence of defective or pothole the interconnection circuit of dynamic RAM by this method.

In order to reach described purpose; the invention provides a kind of defect mending method of dynamic RAM; may further comprise the steps: form inner layer dielectric layer and be deposited on the DRAM cell; above-mentioned inner layer dielectric layer is carried out degree of depth chemically mechanical polishing, at DRAM cell surface deposition protective seam.

In the defect mending method of above-mentioned dynamic RAM, described protective seam is an inner layer dielectric layer.

In the defect mending method of above-mentioned dynamic RAM, described inner layer dielectric layer is a kind of of silicon dioxide, silicon nitride, NO (silicon nitride/silicon dioxide), ONO (silicon dioxide/silicon nitride/silicon dioxide).

In the defect mending method of above-mentioned dynamic RAM, described protective seam deposits by chemical gaseous phase depositing process.

In the defect mending method of above-mentioned dynamic RAM, described defective is the micro dust particle defective, becomes vestige through after the chemically mechanical polishing.

In the defect mending method of above-mentioned dynamic RAM, described dynamic RAM is the stacking-type dynamic RAM.

By the defect mending method of above-mentioned dynamic RAM, can defective not contacted the defective and the external isolation of dynamic RAM with outside processing procedure, thereby improve the yield of dynamic RAM product.

Description of drawings

The defect mending method of dynamic RAM of the present invention is provided by following embodiment and accompanying drawing.

Figure 1A to 1I is the dynamic RAM manufacturing flow chart of prior art;

Fig. 2 repairs the defect sturcture synoptic diagram of dynamic RAM for the present invention;

Fig. 3 is the defect mending method process flow diagram of dynamic RAM of the present invention;

Embodiment

Be described in further detail below with reference to the defect mending method of accompanying drawing dynamic RAM of the present invention.

The leading portion manufacturing process of stacking-type dynamic RAM of the present invention just is not described in detail here as described in Figure 1A to 1F.

As shown in Figures 2 and 3, be the structural representation and the method flow diagram of the defect mending of dynamic RAM of the present invention.In the stacking-type dynamic RAM; at first forming inner layer dielectric layer 38 as Fig. 1 F is deposited on the DRAM cell; then not to utilize normal chemical Mechanical Polishing Technique that leveling is carried out on the surface of stacking-type DRAM unit as Fig. 1 G; but carry out degree of depth chemically mechanical polishing (step S20) earlier; that is to say a bit more than 38 polishings of the inner layer dielectric layer on the DRAM unit; fall 3 nanometer thickness inner layer dielectric layers such as normal polishing; 3.1 nanometer thickness are fallen in polishing so now; here inner layer dielectric layer is a silicon dioxide; silicon nitride; NO (silicon nitride/silicon dioxide); ONO's (silicon dioxide/silicon nitride/silicon dioxide) is a kind of; then by utilizing chemical vapour deposition technique to deposit the protective seam 46 (step S30) that a layer thickness is 0.1 nanometer; this protective seam is an inner layer dielectric layer, exposes at last; develop; successive process such as etching.By this inner layer dielectric layer 46 micro dust particle defective 40 and outside are isolated; after testing with analysis; this micro dust particle defective becomes marks on surface 41 after chemically mechanical polishing; make marks on surface 41 not be carried out processing procedures such as little shadow, etching; thereby can not produce pothole 44; reach the purpose of protection interconnection circuit, improved the yield of product.

That more than introduces only is based on preferred embodiment of the present invention, can not limit scope of the present invention with this.Any method of the present invention is done replacement, the combination, discrete of step well know in the art, and the invention process step is done well know in the art being equal to change or replace and all do not exceed exposure of the present invention and protection domain.

Claims

1, a kind of defect mending method of dynamic RAM may further comprise the steps at least:

Forming inner layer dielectric layer is deposited on the DRAM cell;

Inner layer dielectric layer is carried out degree of depth chemically mechanical polishing;

At DRAM cell surface deposition protective seam.

2, the defect mending method of dynamic RAM as claimed in claim 1 is characterized in that: described protective seam is an inner layer dielectric layer.

3, the defect mending method of dynamic RAM as claimed in claim 2 is characterized in that: described inner layer dielectric layer is a kind of of silicon dioxide, silicon nitride, NO (silicon nitride/silicon dioxide), ONO (silicon dioxide/silicon nitride/silicon dioxide).

4, as the defect mending method of claim 1 or 5 described dynamic RAMs, it is characterized in that: described protective seam deposits by chemical gaseous phase depositing process.

5, the defect mending method of dynamic RAM as claimed in claim 1 is characterized in that: described defective is the micro dust particle defective, becomes vestige through after the chemically mechanical polishing.

6, the defect mending method of dynamic RAM as claimed in claim 1 is characterized in that: described dynamic RAM is the stacking-type dynamic RAM.