CN103064012A - Chip detector for digital electronic watches - Google Patents
Chip detector for digital electronic watches Download PDFInfo
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- CN103064012A CN103064012A CN2012105936926A CN201210593692A CN103064012A CN 103064012 A CN103064012 A CN 103064012A CN 2012105936926 A CN2012105936926 A CN 2012105936926A CN 201210593692 A CN201210593692 A CN 201210593692A CN 103064012 A CN103064012 A CN 103064012A
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Abstract
The invention relates to the chip detecting field and in particular to a chip detector for digital electronic watches. The chip detector for the digital electronic watches comprises a probe station, a probe card, a main control chip, a parameter testing circuit, an international direct dial (IDD) parameter testing circuit, a frequency parameter testing circuit and a logical function testing circuit. The parameter testing circuit can be used for testing whether a protection diode on a base pin of a wafer chip is sound. The IDD parameter testing circuit is used for testing the power consumption of the wafer chip which works under the conditions of being provided with a power-on and a clock. The frequency parameter testing circuit is used for testing the work frequency of the wafer chip. The logical function testing circuit is used for testing the logical function of the wafer chip. The control signal of the main control chip can be transmitted to a transistor-transistor logic (TTL) interface circuit of the probe station. The chip detector for digital electronic watches is simple in circuit structure and provided with testing functions which are essential for digital electronic watch chips of an operating system (OS) parameter test, an IDD parameter test, a frequency parameter test, logical function test and the like. At the same time of guaranteeing testing requests, the testing cost and the production cost of the digital electronic watch chips can be reduced.
Description
Technical field
The present invention relates to the chip testing field, be specifically related to numeric class electronic watch chip tester.
Background technology
Along with the application of digital integrated circuit (chip) increasingly extensively supports that to the semiconductor industry development domestic cmos digital integrated circuit (IC) design ability has obtained significant progress with country, industry size has also reached unprecedented prosperity.Yet the domestic enterprise that is engaged in the processing of integrated circuit postorder still says all relatively backward in quantity from scale; used test instrument also major part is from outer introduction; these testers are expensive, and complicated operation has increased the production cost of integrated circuit to a certain extent.
Nowadays, along with improving constantly of wafer flow blade technolgy and technology, the area of single chips is more and more less, the integrated complex degree is more and more higher, also more and more higher to the requirement of tester in the test process of postorder, satisfy need of production thereby force enterprise constantly to introduce more high-grade tester.Simultaneously, larger a part of market that digital consumer products are large because of its output, function has simply also occupied integrated circuit (IC) products of relative low side, if the import tester that adopts is produced, certainly will increase production cost, reduced to a certain extent the competitive power of enterprise.Therefore, developing for this type of low side digit chip tester, is one of method that reduces production costs.
At present, in the digital consumer products of low side, the chip that the numeric class electronic watch adopts is the low side chip, and prior art not yet provides the tester for the numeric class electronic watch chip.
Summary of the invention
The object of the present invention is to provide a kind of numeric class electronic watch chip tester, being intended to solve prior art not yet provides problem for the tester of numeric class electronic watch chip.
The present invention is by the following technical solutions:
A kind of numeric class electronic watch chip tester comprises:
Probe station;
Probe;
Main control chip;
Whether the protection diode on the pin of test wafer chip intact OS parameter detecting circuit, the OS parameter testing end of the OS parameter testing control end of the described probe of test termination of described OS parameter detecting circuit, the described main control chip of controlled termination, the described main control chip of output termination;
The test wafer chip is powering on and the IDD parameter detecting circuit of the power consumption when working in the situation of clock, the IDD parameter testing end of the described probe of test termination of described IDD parameter detecting circuit, the described main control chip of output termination is being arranged;
The frequency parameter test circuit of the frequency of operation of test wafer chip, the frequency parameter test lead of the frequency parameter test control end of the described probe of test termination of described frequency parameter test circuit, the described main control chip of controlled termination, the described main control chip of output termination;
The logic function test circuit of the logic function of test wafer chip, the logic function test lead of the described probe of test termination of described logic function test circuit, the described main control chip of output termination;
Show the display circuit of the parameter information of the chip wafer of testing, described display circuit connects the demonstration output terminal of described main control chip;
The button inputting circuits of input control signal, described button inputting circuits connect the key-press input end of described main control chip;
The control signal of described main control chip is transferred to the TTL interface circuit of described probe station, and described TTL interface circuit connects the probe station control end of described main control chip.
Numeric class electronic watch chip tester provided by the invention, its circuit structure is simple, and possess the required test functions of numeric class electronic watch chip such as OS parameter testing, IDD parameter testing, frequency parameter test, logic function test, therefore when guaranteeing test request, reduced testing cost and the production cost of numeric class electronic watch chip.
Description of drawings
The schematic block circuit diagram of the numeric class electronic watch chip tester that Fig. 1 provides for the embodiment of the invention;
The circuit theory diagrams of the OS parameter detecting circuit of the numeric class electronic watch chip tester that Fig. 2 provides for the embodiment of the invention;
The circuit theory diagrams of the IDD parameter detecting circuit of the numeric class electronic watch chip tester that Fig. 3 provides for the embodiment of the invention;
The circuit theory diagrams of the frequency parameter test circuit of the numeric class electronic watch chip tester that Fig. 4 provides for the embodiment of the invention;
The circuit theory diagrams of the logic function test circuit of the numeric class electronic watch chip tester that Fig. 5 provides for the embodiment of the invention;
The circuit theory diagrams of the display circuit of the numeric class electronic watch chip tester that Fig. 6 provides for the embodiment of the invention;
The circuit theory diagrams of the button inputting circuits of the numeric class electronic watch chip tester that Fig. 7 provides for the embodiment of the invention;
The circuit theory diagrams of the TTL interface circuit of the numeric class electronic watch chip tester that Fig. 8 provides for the embodiment of the invention;
The circuit theory diagrams of the RS-232 interface circuit of the numeric class electronic watch chip tester that Fig. 9 provides for the embodiment of the invention;
Figure 10 is the ATmega128 single-chip microcomputer synoptic diagram that adopts of the numeric class electronic watch tester that provides of the embodiment of the invention not.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and the specific embodiments the present invention is described in further detail.Should be appreciated that specific embodiment described herein only is used for explaining the present invention, be not limited to the present invention.
With reference to Fig. 1, the schematic block circuit diagram of the numeric class electronic watch chip tester that the embodiment of the invention provides.
A kind of numeric class electronic watch chip tester comprises:
Whether the protection diode on the pin of test wafer chip intact OS parameter detecting circuit 41, the OS parameter testing end of the OS parameter testing control end of the test termination probe 2 of OS parameter detecting circuit 41, controlled termination main control chip 3, output termination main control chip 3;
The test wafer chip is powering on and the IDD parameter detecting circuit 42 of the power consumption when working in the situation of clock, the IDD parameter testing end of the test termination probe 2 of IDD parameter detecting circuit 42, output termination main control chip 3 is being arranged;
The frequency parameter test circuit 43 of the frequency of operation of test wafer chip, the frequency parameter test lead of the frequency parameter test control end of the test termination probe 2 of frequency parameter test circuit 43, controlled termination main control chip 3, output termination main control chip 3;
The logic function test circuit 44 of the logic function of test wafer chip, the logic function test lead of the test termination probe 2 of logic function test circuit 44, output termination main control chip 3;
Show the display circuit 6 of the parameter information of the chip wafer of testing, display circuit 6 connects the demonstration output terminal of main control chip 3;
The button inputting circuits 7 of input control signal, button inputting circuits 7 connect the key-press input end of main control chip 3;
The control signal of main control chip 3 is transferred to the TTL interface circuit 8 of probe station 1, and TTL interface circuit 8 connects the probe station control end of main control chip 3.
With reference to Fig. 2, the circuit theory diagrams of the OS parameter detecting circuit of the numeric class electronic watch chip tester that the embodiment of the invention provides.
OS parameter detecting circuit 41 comprises:
The first operational amplifier U14A, the second operational amplifier U14D, CD4051 analog switch U13, resistance R 21, resistance R 22, resistance R 23, swept resistance R24;
The in-phase input end of the first operational amplifier U14A connects the 5V power supply by resistance R 22, inverting input is by resistance R 21 ground connection, positive supply termination 5V power supply, negative supply termination-5V power supply, output terminal connects its inverting input by resistance R 23, output terminal is by the first fixed end of swept resistance R24, its first fixed end of the slip termination of swept resistance R24, the in-phase input end of the second operational amplifier U14D connects the second fixed end of swept resistance R24, the in-phase input end of output its inverting input of termination and the first operational amplifier U14A, the supply pin VDD of CD4051 analog switch U13 connects the 5V power supply, negative electricity presser feet VEE connects-the 5V power supply, forbid pin INH and digital signal grounding leg VSS ground connection, input and output pin 1-5 as in the test termination probe 2 of OS parameter detecting circuit 41 corresponding to the port of the functional pin of chip wafer, address pin A-C is as the DC parameter testing control end of the controlled termination main control chip 3 of OS parameter detecting circuit 41, and public input and output pin OUT/IN is as the OS parameter testing end of the output termination main control chip 3 of OS parameter detecting circuit 41.
The OS parameter testing namely is whether the protection diode on the pin of test wafer chip is intact.Protection diode Main Function on the pin of chip wafer is that the protection pin is not damaged by forward or repercussion high-voltage breakdown.
The principle of OS parameter testing is: by the input of the protection diode on the pin of chip wafer forward current; pressure drop on the pin of this chip wafer of testing is 0.7V ~ 0.9V, and then the protection diode on the pin of this chip wafer of explanation existence is intact.
In the OS parameter detecting circuit 41 that present embodiment provides, because the passage of test is fewer here, therefore the resource-constrained of selected control chip selects CD4051 analog switch U13 as passage expansion switching.Be specially the address end A of the OS parameter testing control termination CD4051 analog switch U13 of main control chip 3, B, C, address end A by control CD4051 analog switch U13, B, one of them pin among the input and output pin 1-5 of C gating CD4051 analog switch U13, the public input and output pin OUT/IN of the electric current input CD4051 analog switch U13 that the 5V power supply forms after process through the first operational amplifier U14A and the second operational amplifier U14D, this electric current again one of them pin from the input and output pin 1-5 of CD4051 analog switch U13 exports on the pin of chip wafer, is that feedback voltage signal is to the OS parameter testing end of main control chip 3 in the time of the public input and output pin OUT/IN input current of CD4051 analog switch U13.Thereby whether the protection diode that tests out on the pin of chip wafer is intact.
Because forward diode is only designed in the inside of numeric class electronic watch chip, so this OS parameter detecting circuit only provides the forward diode is tested.
With reference to Fig. 3, the circuit theory diagrams of the IDD parameter detecting circuit of the numeric class electronic watch chip tester that the embodiment of the invention provides.
IDD parameter detecting circuit 42 comprises the 3rd operational amplifier U15A, swept resistance R25, resistance R 26, capacitor C 17;
The fixed end of swept resistance R25 is connected between 5V power supply and the ground, the in-phase input end of slip termination the 3rd operational amplifier U15A, resistance R 26 is connected between the inverting input and output terminal of the 3rd operational amplifier U15A, capacitor C 17 is connected between the inverting input and output terminal of the 3rd operational amplifier U15A, the in-phase input end of the 3rd operational amplifier U15A as in the test termination probe 2 of IDD parameter detecting circuit 42 corresponding to the port of the power pins of chip wafer, output terminal is as the IDD parameter testing end of IDD parameter detecting circuit 42 output termination main control chips 3.
IDD test namely is the test wafer chip to power on and sometimes is being deeply in love power consumption when working under the condition, because the test wafer chip is powering on and sometimes being deeply in love voltage constant under the condition, so just can calculate power consumption number as long as can measure electric current I DD size.
The principle of IDD test is: behind the power pins making alive of chip wafer, test the electric current that passes through in its circuit.
In the IDD parameter detecting circuit 42 that present embodiment provides, resistance R 26 is sampling resistor, and it is the voltage 1.5V of chip wafer VCC end that the sliding end of adjusting slip variable resistance R25 makes its voltage, by the voltage V at sampling resistor R26 two ends
R26, by formula I=V
R26/ R26 can calculate the electric current that passes through in the chip wafer circuit.Thereby the electric current that calculates according to operating voltage and this of this chip wafer again calculates the power consumption of chip wafer.
With reference to Fig. 4, the circuit theory diagrams of the frequency parameter test circuit of the numeric class electronic watch chip tester that the embodiment of the invention provides.
Frequency parameter test circuit 43 comprises the first comparer U18B, the second comparer U17D, the 3rd comparer U16C, the first relay R L3, the second relay R L5, the 3rd relay R L4, swept resistance R27, resistance R 28, resistance R 29, resistance R 30, resistance R 31, positive-negative-positive triode Q3;
The fixed end of swept resistance R27 is connected between 5V power supply and the ground, the emitter of positive-negative-positive triode Q3 connects the 5V power supply by resistance R 31, grounded collector, base stage is as the AC parameter testing control end of the controlled termination main control chip 3 of frequency parameter test circuit 43, the first comparer U18B, the second comparer U17D, the inverting input of the 3rd comparer U16C all connects the sliding end of swept resistance R27, output terminal all connects the 5V power supply, the first comparer U18B, the second comparer U17D, the output terminal of the 3rd comparer U16C is jointly as the frequency parameter test lead of the output termination main control chip 3 of frequency parameter test circuit 43, the first relay R L3, the second relay R L5, the two ends of the control coil of the 3rd relay R L4 all are connected between the emitter and 5V power supply of positive-negative-positive triode Q3, the first relay R L3, the second relay R L5, the first end of the switch of the 3rd relay R L4 meets respectively the first comparer U18B, the second comparer U17D, the in-phase input end of the 3rd comparer U16C, the first relay R L3, the second relay R L5, the second end of the switch of the 3rd relay R L4 is jointly as the port of the functional pin of corresponding chip wafer in the test termination probe 2 of frequency parameter test circuit 43.
The frequency parameter test namely is the frequency of operation of test wafer chip.
The principle of frequency parameter test is: measure the cycle of large clock to be measured with one period little standard time, and then calculate frequency.
In the frequency parameter test circuit 51 that present embodiment provides, need altogether test three frequency values: F1K, DIS, IND, 3 ends of the first relay R L3, the second relay R L5, the 3rd relay R L4 connect respectively probe 2 corresponding to three the frequency pins that will test of chip wafer.The comparative level setting be+0.75V obtains by regulating swept resistance R27, because the clock waveform of chip wafer reality is sinusoidal wave, for the ease of actual measurement, here adopt with the first comparer U18B, the second comparer U17D, the 3rd comparer U16C, the sine wave shaped of chip wafer is become square wave, measure again.The first comparer U18B, the second comparer U17D, the 3rd comparer U16C waveform after with shaping transfers to control chip 3, interrupts finishing the measurement of frequency with timer in control chip 3 inside, calculates the result who changes into actual needs again.
Adopt this frequency parameter test circuit can measure the following frequency of 100K, can satisfy the frequency test of numeric class electronic watch chip.
With reference to Fig. 5, the circuit theory diagrams of the logic function test circuit of the numeric class electronic watch chip tester that the embodiment of the invention provides.
Logic function test circuit 44 comprises:
E818AHF functional test chip U23;
The function logic input pin DATA of E818AHF functional test chip U23, enable pin EN, sampling logic output pin QA, sampling logic output pin QB jointly as the output terminal of logic function test circuit 44 connect respectively main control chip 3 the function logic output pin, enable output pin, sampling logic input pin, the function logic output pin DOUT of E818AHF functional test chip U23, sampling logic input pin VINP jointly as in the test termination probe 2 of logic function test circuit 44 corresponding to the port of the functional pin of chip wafer.
The logic function test mainly adopts the method for excitation vector test to realize.The excitation vector test is the Serial No. that a string continuous " 0 " and " 1 " forms.Before the test wafer chip, by the analysis to test request and chip functions, utilize vectorial programmable device to write the required excitation vector of test, define the sequential requirement of vector, and download it in the storer of tester, then start the control module of test macro.Control module is read test vector and delivers to the Vector Modulation module in order according to finishing writing in advance the test procedure statement from storer.The Vector Modulation module is carried out the waveform modulated voltage modulated to sequence vector, sends at last the wave sequence with chip wafer operating voltage coupling to be measured.Test macro is also monitored the output waveform of chip wafer to be measured simultaneously, convert thereof into the digital signal of mating with the test macro operation level by the Vector Modulation module, tester compares loopback digital signal and predefined vector, and gives control module with comparative result and process.
Be in this logic function test circuit 52 and adopt this principle to carry out the logic function test, adopt special-purpose E818AHF functional test chip U23 to test.
The function logic input pin DATA of Master control chip 3 from function logic output pin output test signal to E818AHF functional test chip U23, Master control chip 3 enable the test signal that output pin output enable signal makes E818AHF functional test chip U23 enter work and receives Master control chip 3 output, this test signal exports chip wafer to from function logic output pin DOUT after processing through E818AHF functional test chip U23, chip wafer is inputted this test signal afterwards with output waveform, to the sampling logic input pin VINP of E818AHF functional test chip U23, after this waveform is processed through E818AHF functional test chip U23 from sampling logic output pin QA, sampling logic output pin QB exports Master control chip 3 to.Master control chip 3 pre-stored correct logic functions compare, and judge whether test result is correct.
In the logic function test for the chip wafer of numeric class electronic watch, need altogether to connect 4 groups of above logic input pin DATA, enable pin EN, sampling logic output pin QA, sampling logic output pin QB, function logic output pin DOUT, sampling logic input pin VINP.
With reference to Fig. 6, the circuit theory diagrams of the display circuit of the numeric class electronic watch chip tester that the embodiment of the invention provides.
The demonstration output terminal that connects main control chip 3 of LCM3310 liquid crystal display J1, the grounding leg GND ground connection of LCM3310 liquid crystal display J1, VLCD pin are by capacitor C 1 ground connection.
Display circuit is mainly used to show the data in the test process.LCM3310 liquid crystal display J1 is that monochrome is with lattice lcd screen backlight, can show 48*84 and pixel.Here the model and the actual test parameter that are mainly used to show the chip wafer of test divide BIN and percent.
LCM3310 adopts SPI agreement connected mode with being connected of CPU.
With reference to Fig. 7, the circuit theory diagrams of the button inputting circuits of the numeric class electronic watch chip tester that the embodiment of the invention provides.
The first button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10, resistance R 6, resistance R 7, resistance R 8, resistance R 9, resistance R 10;
The first end of the first button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10 connects the 5V power supply by resistance R 6, resistance R 7, resistance R 8, resistance R 9, resistance R 10 respectively, and the second end of the first button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10 connects the key-press input end of main control chip 3 jointly.
This button inputting circuits 7 provides following 5 function button: START, STOP, SINGLE, STROBE, READ successively; Be mainly used to realize test and debugging and control in the actual test production run.
With reference to Fig. 8, the circuit theory diagrams of the TTL interface circuit of the numeric class electronic watch chip tester that the embodiment of the invention provides.
TTL interface J3, NPN type triode Q1, NPN type triode Q2, a TLP521-1 photoelectrical coupler U7A, the 2nd TLP521-1 photoelectrical coupler U7B, resistance R 15, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, polar capacitor C15, polar capacitor C16;
3 pin of TTL interface J3 and 4 pin connect the base stage of NPN type triode Q1,17 pin and 18 pin connect the base stage of NPN type triode Q2, the collector of NPN type triode Q1 connects the 5V power supply, emitter is by resistance R 15 ground connection, the positive pole of polar capacitor C15 connects the emitter of NPN type triode Q1, minus earth, 1 pin of the one TLP521-1 photoelectrical coupler U7A connects the emitter of NPN type triode Q1 by resistance R 17,2 pin ground connection, 3 pin are by resistance R 19 ground connection, 4 pin connect the 5V power supply, the collector of NPN type triode Q2 connects the 5V power supply, emitter is by resistance R 16 ground connection, the positive pole of polar capacitor C16 connects the emitter of NPN type triode Q2, minus earth, 1 pin of the 2nd TLP521-2 photoelectrical coupler U7B connects the emitter of NPN type triode Q2 by resistance R 18,2 pin ground connection, 3 pin are by resistance R 20 ground connection, 4 pin connect the 5V power supply, TTL interface J3 7 pin and 8 pin, 3 pin of 11 pin and 12 pin and a TLP521-1 photoelectrical coupler U7A, 3 pin of the 2nd TLP521-2 photoelectrical coupler U7B connect probe station 1 control end of main control chip 3.
With reference to Fig. 9, the circuit theory diagrams of the RS-232 interface circuit of the numeric class electronic watch chip tester that the embodiment of the invention provides.
The numeric class electronic watch chip tester that the embodiment of the invention provides also comprises: the RS-232 interface circuit 9 that connects PC; RS-232 interface circuit 9 comprises: MAX232 chip U5, RS232 interface P1; The T2in pin of MAX232 chip U5 and R2out pin connect respectively 3 pin of RS232 interface P1 and the PC communication ends that 2 pin, T2out pin and R2in pin connect control chip 3.
With reference to Figure 10, in the embodiment of the invention, control chip 3 adopts the ATmega128 single-chip microcomputer.
To sum up, numeric class electronic watch chip tester provided by the invention, its circuit structure is simple, and possess the required test functions of numeric class electronic watch chip such as OS parameter testing, IDD parameter testing, frequency parameter test, logic function test, therefore when guaranteeing test request, reduced testing cost and the production cost of numeric class electronic watch chip.
Be the preferred embodiment of the present invention only below, be not limited to the present invention, all any modifications of within principle of the present invention, doing, be equal to and replace and improvement etc., all should be included within the scope of protection of the invention.
Claims (10)
1. a numeric class electronic watch chip tester is characterized in that, comprising:
Probe station (1);
Probe (2);
Main control chip (3);
Whether the protection diode on the pin of test wafer chip intact OS parameter detecting circuit (41), the OS parameter testing end of the OS parameter testing control end of the described probe of test termination (2) of described OS parameter detecting circuit (41), the described main control chip of controlled termination (3), the output described main control chip of termination (3);
The test wafer chip is powering on and the IDD parameter detecting circuit (42) of the power consumption when working in the situation of clock, the IDD parameter testing end of the described probe of test termination (2) of described IDD parameter detecting circuit (42), the output described main control chip of termination (3) is being arranged;
The frequency parameter test circuit (43) of the frequency of operation of test wafer chip, the frequency parameter test lead of the frequency parameter test control end of the described probe of test termination (2) of described frequency parameter test circuit (43), the described main control chip of controlled termination (3), the output described main control chip of termination (3);
The logic function test circuit (44) of the logic function of test wafer chip, the logic function test lead of the described probe of test termination (2) of described logic function test circuit (44), the output described main control chip of termination (3);
Show the display circuit (6) of the parameter information of the chip wafer of testing, described display circuit (6) connects the demonstration output terminal of described main control chip (3);
The button inputting circuits of input control signal (7), described button inputting circuits (7) connects the key-press input end of described main control chip (3);
The control signal of described main control chip (3) is transferred to the TTL interface circuit (8) of described probe station (1), and described TTL interface circuit (8) connects the probe station control end of described main control chip (3).
2. numeric class electronic watch chip tester as claimed in claim 1 is characterized in that, described OS parameter detecting circuit (41) comprising:
The first operational amplifier U14A, the second operational amplifier U14D, CD4051 analog switch U13, resistance R 21, resistance R 22, resistance R 23, swept resistance R24;
The in-phase input end of described the first operational amplifier U14A connects 5V power supply, inverting input by described resistance R 22 and connects its inverting input, output terminal by the first fixed end of described swept resistance R24 by described resistance R 21 ground connection, positive supply termination 5V power supply, negative supply termination-5V power supply, output terminal by described resistance R 23
Its first fixed end of the slip termination of described swept resistance R24,
The in-phase input end of described the second operational amplifier U14D connects the in-phase input end of the second fixed end, output its inverting input of termination and described the first operational amplifier U14A of described swept resistance R24;
The supply pin VDD of described CD4051 analog switch U13 connects the 5V power supply, negative electricity presser feet VEE connects-the 5V power supply, forbid pin INH and digital signal grounding leg VSS ground connection, input and output pin 1-5 as in the described probe of test termination (2) of described OS parameter detecting circuit (41) corresponding to the port of the functional pin of chip wafer, address pin A-C is as the DC parameter testing control end of the described main control chip of controlled termination (3) of described OS parameter detecting circuit (41), and public input and output pin OUT/IN is as the OS parameter testing end of the described main control chip of output termination (3) of described OS parameter detecting circuit (41).
3. numeric class electronic watch chip tester as claimed in claim 1 is characterized in that, described IDD parameter detecting circuit (42) comprises the 3rd operational amplifier U15A, swept resistance R25, resistance R 26, capacitor C 17;
The fixed end of described swept resistance R25 is connected between 5V power supply and the ground, the in-phase input end of described the 3rd operational amplifier U15A of slip termination,
Described resistance R 26 is connected between the inverting input and output terminal of described the 3rd operational amplifier U15A,
Described capacitor C 17 is connected between the inverting input and output terminal of described the 3rd operational amplifier U15A,
The in-phase input end of described the 3rd operational amplifier U15A as in the described probe of test termination (2) of described IDD parameter detecting circuit (42) corresponding to the port of the power pins of chip wafer, the output terminal IDD parameter testing end as described IDD parameter detecting circuit (42) the output described main control chip of termination (3).
4. numeric class electronic watch chip tester as claimed in claim 1, it is characterized in that described frequency parameter test circuit (43) comprises the first comparer U18B, the second comparer U17D, the 3rd comparer U16C, the first relay R L3, the second relay R L5, the 3rd relay R L4, swept resistance R27, resistance R 28, resistance R 29, resistance R 30, resistance R 31, positive-negative-positive triode Q3;
The fixed end of described swept resistance R27 is connected between 5V power supply and the ground,
The emitter of described positive-negative-positive triode Q3 connects 5V power supply, grounded collector, base stage as the AC parameter testing control end of the described main control chip of controlled termination (3) of described frequency parameter test circuit (43) by described resistance R 31,
The inverting input of described the first comparer U18B, the second comparer U17D, the 3rd comparer U16C all connects the sliding end of described swept resistance R27, output terminal all connects the 5V power supply,
The output terminal of described the first comparer U18B, the second comparer U17D, the 3rd comparer U16C is jointly as the frequency parameter test lead of the described main control chip of output termination (3) of described frequency parameter test circuit (43),
The two ends of the control coil of described the first relay R L3, the second relay R L5, the 3rd relay R L4 all are connected between the emitter and 5V power supply of described positive-negative-positive triode Q3, the first end of switch connects respectively the in-phase input end of described the first comparer U18B, the second comparer U17D, the 3rd comparer U16C, and the second end of switch is jointly as the port of the functional pin of corresponding chip wafer in the described probe of test termination (2) of described frequency parameter test circuit (43).
5. numeric class electronic watch chip tester as claimed in claim 1 is characterized in that, described logic function test circuit (44) comprising:
E818AHF functional test chip U23;
The function logic input pin DATA of described E818AHF functional test chip U23, enable pin EN, sampling logic output pin QA, sampling logic output pin QB connects respectively the function logic output pin of described main control chip (3) jointly as the output terminal of described logic function test circuit (44), enable output pin, sampling logic input pin, the function logic output pin DOUT of described E818AHF functional test chip U23, sampling logic input pin VINP jointly as in the described probe of test termination (2) of described logic function test circuit (44) corresponding to the port of the functional pin of chip wafer.
6. numeric class electronic watch chip tester as claimed in claim 1 is characterized in that, described display circuit (6) comprises LCM3310 liquid crystal display J1, capacitor C 1;
The demonstration output terminal that connects described main control chip (3) of described LCM3310 liquid crystal display J1,
The grounding leg GND ground connection of described LCM3310 liquid crystal display J1, VLCD pin are by described capacitor C 1 ground connection.
7. numeric class electronic watch chip tester as claimed in claim 1 is characterized in that, described button inputting circuits (7) comprising:
The first button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10, resistance R 6, resistance R 7, resistance R 8, resistance R 9, resistance R 10;
The first end of described the first button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10 connects the 5V power supply by described resistance R 6, resistance R 7, resistance R 8, resistance R 9, resistance R 10 respectively,
The second end of described the first button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10 connects the key-press input end of described main control chip (3) jointly.
8. numeric class electronic watch chip tester as claimed in claim 1 is characterized in that, described TTL interface circuit (8) comprising:
TTL interface J3, NPN type triode Q1, NPN type triode Q2, a TLP521-1 photoelectrical coupler U7A, the 2nd TLP521-1 photoelectrical coupler U7B, resistance R 15, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, polar capacitor C15, polar capacitor C16;
Base stage, 17 pin and 18 pin that 3 pin of described TTL interface J3 and 4 pin meet described NPN type triode Q1 connect the base stage of described NPN type triode Q2,
The collector of described NPN type triode Q1 connects 5V power supply, emitter by described resistance R 15 ground connection,
The positive pole of described polar capacitor C15 connects emitter, the minus earth of described NPN type triode Q1,
1 pin of a described TLP521-1 photoelectrical coupler U7A connects the 5V power supply by emitter, 2 pin ground connection, 3 pin that described resistance R 17 meets described NPN type triode Q1 by described resistance R 19 ground connection, 4 pin,
The collector of described NPN type triode Q2 connects 5V power supply, emitter by described resistance R 16 ground connection,
The positive pole of described polar capacitor C16 connects emitter, the minus earth of described NPN type triode Q2,
1 pin of described the 2nd TLP521-2 photoelectrical coupler U7B connects the 5V power supply by emitter, 2 pin ground connection, 3 pin that described resistance R 18 meets described NPN type triode Q2 by described resistance R 20 ground connection, 4 pin,
Described TTL interface J3 7 pin and 3 pin of 3 pin of 8 pin, 11 pin and 12 pin and a described TLP521-1 photoelectrical coupler U7A, described the 2nd TLP521-2 photoelectrical coupler U7B connect probe station (1) control end of described main control chip (3).
9. numeric class electronic watch chip tester as claimed in claim 1 is characterized in that, also comprises:
The RS-232 interface circuit (9) that connects PC (5);
Described RS-232 interface circuit (9) comprising: MAX232 chip U5, RS232 interface P1;
The T2in pin of described MAX232 chip U5 and R2out pin connect respectively 3 pin of described RS232 interface P1 and the PC communication ends that 2 pin, T2out pin and R2in pin connect control chip (3).
10. such as the described numeric class electronic watch chip of claim 1-9 tester, it is characterized in that described control chip (3) adopts the ATmega128 single-chip microcomputer.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103616632A (en) * | 2013-11-23 | 2014-03-05 | 大连尚能科技发展有限公司 | Tool and method for testing photoelectric conversion circuit |
| CN104459514A (en) * | 2014-11-04 | 2015-03-25 | 兵器工业卫生研究所 | I/O port logical detection method and system |
| CN105182265A (en) * | 2015-09-29 | 2015-12-23 | 中国电力科学研究院 | Metering chip model selection testing system |
| CN107547149A (en) * | 2016-06-27 | 2018-01-05 | 中兴通讯股份有限公司 | Radio frequency testing chip |
| CN107817386A (en) * | 2017-09-15 | 2018-03-20 | 北方电子研究院安徽有限公司 | A kind of CCD wafers test device for insulation resistance |
| CN109239575A (en) * | 2018-08-01 | 2019-01-18 | 上海移远通信技术股份有限公司 | A kind of detection device, detection method and automated detection system |
| CN110007218A (en) * | 2018-01-04 | 2019-07-12 | 中国航发商用航空发动机有限责任公司 | Digital circuit product tester |
| CN111983427A (en) * | 2020-08-11 | 2020-11-24 | 中国兵器工业集团第二一四研究所苏州研发中心 | 16-channel analog switch circuit test system and test method |
| CN112198421A (en) * | 2020-12-01 | 2021-01-08 | 上海伟测半导体科技股份有限公司 | Method and device for expanding number of ATE digital channels |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58213266A (en) * | 1982-06-07 | 1983-12-12 | Hitachi Ltd | Digital semiconductor integrated circuit |
| CN101552458A (en) * | 2008-12-29 | 2009-10-07 | 浙江中凯科技股份有限公司 | Protective circuit of a control and protection switch |
| JP2010040875A (en) * | 2008-08-06 | 2010-02-18 | Sharp Corp | Semiconductor integrated circuit, method of testing probe card and semiconductor integrated circuit |
| CN201417297Y (en) * | 2009-04-29 | 2010-03-03 | 深圳安博电子有限公司 | Power management chip test device |
| CN201417296Y (en) * | 2009-04-28 | 2010-03-03 | 深圳安博电子有限公司 | Indicator integrated circuit test device |
| CN102401876A (en) * | 2010-09-17 | 2012-04-04 | 深圳安博电子有限公司 | Testing system and testing method for optoelectronic integrated circuit chip |
-
2012
- 2012-12-31 CN CN201210593692.6A patent/CN103064012B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58213266A (en) * | 1982-06-07 | 1983-12-12 | Hitachi Ltd | Digital semiconductor integrated circuit |
| JP2010040875A (en) * | 2008-08-06 | 2010-02-18 | Sharp Corp | Semiconductor integrated circuit, method of testing probe card and semiconductor integrated circuit |
| CN101552458A (en) * | 2008-12-29 | 2009-10-07 | 浙江中凯科技股份有限公司 | Protective circuit of a control and protection switch |
| CN201417296Y (en) * | 2009-04-28 | 2010-03-03 | 深圳安博电子有限公司 | Indicator integrated circuit test device |
| CN201417297Y (en) * | 2009-04-29 | 2010-03-03 | 深圳安博电子有限公司 | Power management chip test device |
| CN102401876A (en) * | 2010-09-17 | 2012-04-04 | 深圳安博电子有限公司 | Testing system and testing method for optoelectronic integrated circuit chip |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103616632A (en) * | 2013-11-23 | 2014-03-05 | 大连尚能科技发展有限公司 | Tool and method for testing photoelectric conversion circuit |
| CN103616632B (en) * | 2013-11-23 | 2016-05-11 | 大连尚能科技发展有限公司 | Photoelectric switching circuit test fixture and method of testing |
| CN104459514A (en) * | 2014-11-04 | 2015-03-25 | 兵器工业卫生研究所 | I/O port logical detection method and system |
| CN105182265A (en) * | 2015-09-29 | 2015-12-23 | 中国电力科学研究院 | Metering chip model selection testing system |
| CN107547149A (en) * | 2016-06-27 | 2018-01-05 | 中兴通讯股份有限公司 | Radio frequency testing chip |
| CN107547149B (en) * | 2016-06-27 | 2021-03-30 | 中兴通讯股份有限公司 | Radio frequency test chip |
| CN107817386A (en) * | 2017-09-15 | 2018-03-20 | 北方电子研究院安徽有限公司 | A kind of CCD wafers test device for insulation resistance |
| CN110007218A (en) * | 2018-01-04 | 2019-07-12 | 中国航发商用航空发动机有限责任公司 | Digital circuit product tester |
| CN109239575A (en) * | 2018-08-01 | 2019-01-18 | 上海移远通信技术股份有限公司 | A kind of detection device, detection method and automated detection system |
| CN111983427A (en) * | 2020-08-11 | 2020-11-24 | 中国兵器工业集团第二一四研究所苏州研发中心 | 16-channel analog switch circuit test system and test method |
| CN111983427B (en) * | 2020-08-11 | 2023-10-20 | 中国兵器工业集团第二一四研究所苏州研发中心 | 16-channel analog switch circuit testing system and testing method |
| CN112198421A (en) * | 2020-12-01 | 2021-01-08 | 上海伟测半导体科技股份有限公司 | Method and device for expanding number of ATE digital channels |
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