CN103064012B - Chip detector for digital electronic watches - Google Patents
Chip detector for digital electronic watches Download PDFInfo
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- CN103064012B CN103064012B CN201210593692.6A CN201210593692A CN103064012B CN 103064012 B CN103064012 B CN 103064012B CN 201210593692 A CN201210593692 A CN 201210593692A CN 103064012 B CN103064012 B CN 103064012B
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Abstract
The invention relates to the chip detecting field and in particular to a chip detector for digital electronic watches. The chip detector for the digital electronic watches comprises a probe station, a probe card, a main control chip, a parameter testing circuit, an international direct dial (IDD) parameter testing circuit, a frequency parameter testing circuit and a logical function testing circuit. The parameter testing circuit can be used for testing whether a protection diode on a base pin of a wafer chip is sound. The IDD parameter testing circuit is used for testing the power consumption of the wafer chip which works under the conditions of being provided with a power-on and a clock. The frequency parameter testing circuit is used for testing the work frequency of the wafer chip. The logical function testing circuit is used for testing the logical function of the wafer chip. The control signal of the main control chip can be transmitted to a transistor-transistor logic (TTL) interface circuit of the probe station. The chip detector for digital electronic watches is simple in circuit structure and provided with testing functions which are essential for digital electronic watch chips of an operating system (OS) parameter test, an IDD parameter test, a frequency parameter test, logical function test and the like. At the same time of guaranteeing testing requests, the testing cost and the production cost of the digital electronic watch chips can be reduced.
Description
Technical field
The present invention relates to chip testing field, be specifically related to numeric class electronic watch chip tester.
Background technology
Along with the application of digital integrated circuit (chip) is increasingly extensively supported semiconductor industry development with country, domestic cmos digital integrated circuit (IC) design ability obtains significant progress, and industry size also reaches unprecedented prosperity.But the domestic enterprise being engaged in the processing of integrated circuit postorder is from scale or say backwardness all relatively in quantity; used test instrument also major part is from outer introduction; these testers are expensive, complicated operation, add the production cost of integrated circuit to a certain extent.
Nowadays, along with improving constantly of wafer flow blade technolgy and technology, the area of single chips is more and more less, integration complexity is more and more higher, also more and more higher to the requirement of tester in the test process of postorder, thus force enterprise must constantly introduce more high-grade tester to meet need of production.Simultaneously, the digital consumer products of relative low side are because of its output is large, function simply also occupies integrated circuit (IC) products larger a part of market, according to import tester produce, certainly will production cost be increased, reduce the competitive power of enterprise to a certain extent.Therefore, developing for this type of low side digit chip tester, is one of method reducing production cost.
At present, in the digital consumer products of low side, the chip that numeric class electronic watch adopts is low side chip, and prior art not yet provides the tester for numeric class electronic watch chip.
Summary of the invention
The object of the present invention is to provide a kind of numeric class electronic watch chip tester, be intended to solve the problem that prior art not yet provides the tester for numeric class electronic watch chip.
The present invention is by the following technical solutions:
A kind of numeric class electronic watch chip tester, comprising:
Probe station;
Probe;
Main control chip;
The OS parameter detecting circuit whether the protection diode on the pin of test wafer chip is intact, the OS parameter testing control end of main control chip described in probe, controlled termination described in the test termination of described OS parameter detecting circuit, exports the OS parameter testing end of main control chip described in termination;
The IDD parameter detecting circuit of power consumption when test wafer chip works when powering on and have clock, the IDD parameter testing end of main control chip described in probe, output termination described in the test termination of described IDD parameter detecting circuit;
The frequency parameter test circuit of the frequency of operation of test wafer chip, the frequency parameter test control end of main control chip described in probe, controlled termination described in the test termination of described frequency parameter test circuit, exports the frequency parameter test lead of main control chip described in termination;
The logic function test circuit of the logic function of test wafer chip, the logic function test lead of main control chip described in probe, output termination described in the test termination of described logic function test circuit;
Show the display circuit of the parameter information of the chip wafer tested, described display circuit connects the display translation end of described main control chip;
The button inputting circuits of input control signal, described button inputting circuits connects the key-press input end of described main control chip;
The control signal of described main control chip is transferred to the TTL interface circuit of described probe station, described TTL interface circuit connects the probe station control end of described main control chip.
Numeric class electronic watch chip tester provided by the invention, its circuit structure is simple, and possess the test function needed for numeric class electronic watch chip such as OS parameter testing, IDD parameter testing, frequency parameter test, logic function test, while ensureing test request, therefore reduce testing cost and the production cost of numeric class electronic watch chip.
Accompanying drawing explanation
The schematic block circuit diagram of the numeric class electronic watch chip tester that Fig. 1 provides for the embodiment of the present invention;
The circuit theory diagrams of the OS parameter detecting circuit of the numeric class electronic watch chip tester that Fig. 2 provides for the embodiment of the present invention;
The circuit theory diagrams of the IDD parameter detecting circuit of the numeric class electronic watch chip tester that Fig. 3 provides for the embodiment of the present invention;
The circuit theory diagrams of the frequency parameter test circuit of the numeric class electronic watch chip tester that Fig. 4 provides for the embodiment of the present invention;
The circuit theory diagrams of the logic function test circuit of the numeric class electronic watch chip tester that Fig. 5 provides for the embodiment of the present invention;
The circuit theory diagrams of the display circuit of the numeric class electronic watch chip tester that Fig. 6 provides for the embodiment of the present invention;
The circuit theory diagrams of the button inputting circuits of the numeric class electronic watch chip tester that Fig. 7 provides for the embodiment of the present invention;
The circuit theory diagrams of the TTL interface circuit of the numeric class electronic watch chip tester that Fig. 8 provides for the embodiment of the present invention;
The circuit theory diagrams of the RS-232 interface circuit of the numeric class electronic watch chip tester that Fig. 9 provides for the embodiment of the present invention;
The ATmega128 single-chip microcomputer schematic diagram that the numeric class electronic watch tester that the non-embodiment of the present invention of Figure 10 provides adopts.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.Should be appreciated that specific embodiment described herein only for explaining the present invention, being not limited to the present invention.
With reference to Fig. 1, the schematic block circuit diagram of the numeric class electronic watch chip tester that the embodiment of the present invention provides.
A kind of numeric class electronic watch chip tester, comprising:
Probe station 1;
Probe 2;
Main control chip 3;
The OS parameter testing control end of the test termination probe 2 of OS parameter detecting circuit 41, the OS parameter detecting circuit 41 whether the protection diode on the pin of test wafer chip is intact, controlled termination main control chip 3, the OS parameter testing end of output termination main control chip 3;
The test termination probe 2 of IDD parameter detecting circuit 42, the IDD parameter detecting circuit 42 of power consumption when test wafer chip works when powering on and have clock, the IDD parameter testing end of output termination main control chip 3;
The frequency parameter test circuit 43 of the frequency of operation of test wafer chip, the frequency parameter test lead of the test termination probe 2 of frequency parameter test circuit 43, the frequency parameter test control end of controlled termination main control chip 3, output termination main control chip 3;
The logic function test circuit 44 of the logic function of test wafer chip, the test termination probe 2 of logic function test circuit 44, the logic function test lead of output termination main control chip 3;
Show the display circuit 6 of the parameter information of the chip wafer tested, display circuit 6 connects the display translation end of main control chip 3;
The button inputting circuits 7 of input control signal, button inputting circuits 7 connects the key-press input end of main control chip 3;
TTL interface circuit 8, the TTL interface circuit 8 control signal of main control chip 3 being transferred to probe station 1 connects the probe station control end of main control chip 3.
With reference to Fig. 2, the circuit theory diagrams of the OS parameter detecting circuit of the numeric class electronic watch chip tester that the embodiment of the present invention provides.
OS parameter detecting circuit 41 comprises:
First operational amplifier U14A, second operational amplifier U14D, CD4051 analog switch U13, resistance R21, resistance R22, resistance R23, swept resistance R24;
The in-phase input end of the first operational amplifier U14A connects 5V power supply by resistance R22, inverting input is by resistance R21 ground connection, positive supply termination 5V power supply, negative supply termination-5V power supply, output terminal connects its inverting input by resistance R23, output terminal is by first fixed end of swept resistance R24, its first fixed end of the slip termination of swept resistance R24, the in-phase input end of the second operational amplifier U14D connects second fixed end of swept resistance R24, export the in-phase input end of its inverting input of termination and the first operational amplifier U14A, the supply pin VDD of CD4051 analog switch U13 connects 5V power supply, negative electricity presser feet VEE connects-5V power supply, forbid pin INH and digital signal grounding leg VSS ground connection, input and output pin 1-5 is as the port of functional pin corresponding to chip wafer in the test termination probe 2 of OS parameter detecting circuit 41, address pin A-C is as the DC parameter testing control end of the controlled termination main control chip 3 of OS parameter detecting circuit 41, public input and output pin OUT/IN is as the OS parameter testing end of the output termination main control chip 3 of OS parameter detecting circuit 41.
OS parameter testing, be namely test wafer chip pin on protection diode whether intact.Protection diode Main Function on the pin of chip wafer is that protection pin is not damaged by forward or repercussion high-voltage breakdown.
The principle of OS parameter testing is: by inputting forward current to the protection diode on the pin of chip wafer; pressure drop on the pin of this chip wafer of test is 0.7V ~ 0.9V, then illustrate that the protection diode on the pin that there is this chip wafer is intact.
In the OS parameter detecting circuit 41 that the present embodiment provides, because the passage tested here is fewer, the resource-constrained of selected control chip, therefore selects CD4051 analog switch U13 to switch as channel expansion.The OS parameter testing being specially main control chip 3 controls the address end A of termination CD4051 analog switch U13, B, C, by the address end A of control CD4051 analog switch U13, B, one of them pin in the input and output pin 1-5 of C gating CD4051 analog switch U13, the public input and output pin OUT/IN of the electric current input CD4051 analog switch U13 that 5V power supply is formed after process through the first operational amplifier U14A and the second operational amplifier U14D, this electric current exports on the pin of chip wafer from one of them pin the input and output pin 1-5 of CD4051 analog switch U13 again, while the public input and output pin OUT/IN input current of CD4051 analog switch U13 namely feedback voltage signal to the OS parameter testing end of main control chip 3.Thus whether the protection diode tested out on the pin of chip wafer is intact.
Because forward diode is only designed in the inside of numeric class electronic watch chip, therefore this OS parameter detecting circuit only provides and tests forward diode.
With reference to Fig. 3, the circuit theory diagrams of the IDD parameter detecting circuit of the numeric class electronic watch chip tester that the embodiment of the present invention provides.
IDD parameter detecting circuit 42 comprises the 3rd operational amplifier U15A, swept resistance R25, resistance R26, electric capacity C17;
The fixed end of swept resistance R25 is connected between 5V power supply and ground, the in-phase input end of slip termination the 3rd operational amplifier U15A, between the inverting input that resistance R26 is connected to the 3rd operational amplifier U15A and output terminal, between the inverting input that electric capacity C17 is connected to the 3rd operational amplifier U15A and output terminal, the in-phase input end of the 3rd operational amplifier U15A is as the port of power pins corresponding to chip wafer in the test termination probe 2 of IDD parameter detecting circuit 42, output terminal exports the IDD parameter testing end of termination main control chip 3 as IDD parameter detecting circuit 42.
IDD tests, and is namely the power consumption of test wafer chip when working under powering on and have clock case, because test wafer chip is powering on and voltage constant under having clock case, as long as so can measure electric current I DD size just can calculate power consumption number.
The principle of IDD test is: after the power pins making alive of chip wafer, test the electric current passed through in its circuit.
In the IDD parameter detecting circuit 42 that the present embodiment provides, resistance R26 is sampling resistor, regulates the sliding end of slip variable resistance R25 to make its voltage be the voltage 1.5V that chip wafer VCC holds, by the voltage V at sampling resistor R26 two ends
r26, by formula I=V
r26/ R26 can calculate the electric current passed through in chip wafer circuit.The electric current calculated according to operating voltage and this of this chip wafer again thus calculate the power consumption of chip wafer.
With reference to Fig. 4, the circuit theory diagrams of the frequency parameter test circuit of the numeric class electronic watch chip tester that the embodiment of the present invention provides.
Frequency parameter test circuit 43 comprises the first comparer U18B, the second comparer U17D, the 3rd comparer U16C, the first relay R L3, the second relay R L5, the 3rd relay R L4, swept resistance R27, resistance R28, resistance R29, resistance R30, resistance R31, PNP type triode Q3;
The fixed end of swept resistance R27 is connected between 5V power supply and ground, and the emitter of PNP type triode Q3 connects 5V power supply by resistance R31, grounded collector, base stage as the AC parameter testing control end of the controlled termination main control chip 3 of frequency parameter test circuit 43, the first comparer U18B, second comparer U17D, the inverting input of the 3rd comparer U16C all connects the sliding end of swept resistance R27, output terminal all connects 5V power supply, the first comparer U18B, second comparer U17D, the output terminal of the 3rd comparer U16C jointly as the frequency parameter test lead of the output termination main control chip 3 of frequency parameter test circuit 43, the first relay R L3, second relay R L5, the two ends of the control coil of the 3rd relay R L4 are all connected between the emitter of PNP type triode Q3 and 5V power supply, the first relay R L3, second relay R L5, the first end of the switch of the 3rd relay R L4 meets the first comparer U18B respectively, second comparer U17D, the in-phase input end of the 3rd comparer U16C, the first relay R L3, second relay R L5, second end of the switch of the 3rd relay R L4 is jointly as the port of the functional pin of corresponding chip wafer in the test termination probe 2 of frequency parameter test circuit 43.
Frequency parameter is tested, and is namely the frequency of operation of test wafer chip.
The principle of frequency parameter test is: the cycle measuring large clock to be measured with the standard time of one period little, and then calculates frequency.
In the frequency parameter test circuit 51 that the present embodiment provides, need test three frequency values altogether: F1K, DIS, IND, 3 ends of the first relay R L3, the second relay R L5, the 3rd relay R L4 connect three frequency pins that will test that probe 2 corresponds to chip wafer respectively.What comparative level was arranged is that+0.75V obtains by regulating swept resistance R27, clock waveform due to chip wafer reality is sinusoidal wave, for the ease of actual measurement, here adopt with the first comparer U18B, the second comparer U17D, the 3rd comparer U16C, the sine wave shaped of chip wafer is become square wave, then measure.Waveform transfer after shaping to control chip 3, is completed the measurement of frequency by the first comparer U18B, the second comparer U17D, the 3rd comparer U16C at control chip 3 inside timer interruption, then calculates the result changing into actual needs.
Adopt this frequency parameter test circuit can measure the frequency of below 100K, the frequency test of numeric class electronic watch chip can be met.
With reference to Fig. 5, the circuit theory diagrams of the logic function test circuit of the numeric class electronic watch chip tester that the embodiment of the present invention provides.
Logic function test circuit 44 comprises:
E818AHF functional test chip U23;
The function logic input pin DATA of E818AHF functional test chip U23, enable pin EN, sample logic output pin QA, sample logic output pin QB connect the function logic output pin of main control chip 3, enable output pin, sample logic input pin respectively as the output terminal of logic function test circuit 44 jointly, and function logic output pin DOUT, the sample logic input pin VINP of E818AHF functional test chip U23 are jointly as the port of functional pin corresponding to chip wafer in the test termination probe 2 of logic function test circuit 44.
Logic function is tested, and the main method of excitation vector test that adopts realizes.Excitation vector is tested, and is the Serial No. that a string continuous print " 0 " and " 1 " form.Before test wafer chip, by the analysis to test request and chip functions, utilize vectorial programmable device to write excitation vector needed for test, define the timing requirements of vector, and download it in the storer of tester, then start the control module of test macro.Test vector, according to finishing writing test procedure statement in advance, reads and delivers to Vector Modulation module by control module in order from storer.Vector Modulation module carries out waveform modulated voltage modulated to sequence vector, finally sends the wave sequence mated with chip wafer operating voltage to be measured.Test macro also monitors the output waveform of chip wafer to be measured simultaneously, the digital signal of mating with test macro operation level is converted thereof into by Vector Modulation module, loopback digital signal and the vector that presets compare by tester, and give control module by comparative result and process.
Be in this logic function test circuit 52 and adopt this principle to carry out logic function test, adopt special E818AHF functional test chip U23 to test.
Master control chip 3 exports the function logic input pin DATA of test signal to E818AHF functional test chip U23 from function logic output pin, the enable output pin output enable signal of Master control chip 3 makes E818AHF functional test chip U23 enter work and receives the test signal of Master control chip 3 output, this test signal exports chip wafer to from function logic output pin DOUT after E818AHF functional test chip U23 process, chip wafer input this test signal after by output waveform, to the sample logic input pin VINP of E818AHF functional test chip U23, this waveform after E818AHF functional test chip U23 process from sample logic output pin QA, sample logic output pin QB exports Master control chip 3 to.The correct logic function that Master control chip 3 prestores compares, and judges that whether test result is correct.
For in the logic function test of the chip wafer of numeric class electronic watch, need the logic input pin DATA of connection more than 4 groups, enable pin EN, sample logic output pin QA, sample logic output pin QB, function logic output pin DOUT, sample logic input pin VINP altogether.
With reference to Fig. 6, the circuit theory diagrams of the display circuit of the numeric class electronic watch chip tester that the embodiment of the present invention provides.
Display circuit 6 comprises LCM3310 liquid crystal display J1, electric capacity C1;
The display translation end connecing main control chip 3 of LCM3310 liquid crystal display J1, grounding leg GND ground connection, the VLCD pin of LCM3310 liquid crystal display J1 pass through electric capacity C1 ground connection.
Display circuit is mainly used to show the data in test process.LCM3310 liquid crystal display J1 is monochromatic band backlight lattice lcd screen, can show 48*84 and pixel.Here the model of chip wafer and the test parameter of reality that are mainly used to display test divide BIN and percent.
The connection of LCM3310 and CPU adopts SPI protocol connected mode.
With reference to Fig. 7, the circuit theory diagrams of the button inputting circuits of the numeric class electronic watch chip tester that the embodiment of the present invention provides.
Button inputting circuits 7 comprises:
First button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10;
The first end of the first button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10 connects 5V power supply respectively by resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, and second end of the first button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10 connects the key-press input end of main control chip 3 jointly.
This button inputting circuits 7 provides following 5 function buttons successively: START, STOP, SINGLE, STROBE, READ; Be mainly used to realize test and debugging and control in actual test production run.
With reference to Fig. 8, the circuit theory diagrams of the TTL interface circuit of the numeric class electronic watch chip tester that the embodiment of the present invention provides.
TTL interface circuit 8 comprises:
TTL interface J3, NPN type triode Q1, NPN type triode Q2, a TLP521-1 photoelectrical coupler U7A, the 2nd TLP521-1 photoelectrical coupler U7B, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, resistance R20, polar capacitor C15, polar capacitor C16;
3 pin of TTL interface J3 and 4 pin connect the base stage of NPN type triode Q1, 17 pin and 18 pin connect the base stage of NPN type triode Q2, and the collector of NPN type triode Q1 connects 5V power supply, emitter is by resistance R15 ground connection, and the positive pole of polar capacitor C15 connects the emitter of NPN type triode Q1, minus earth, 1 pin of a TLP521-1 photoelectrical coupler U7A connects the emitter of NPN type triode Q1 by resistance R17, 2 pin ground connection, 3 pin are by resistance R19 ground connection, 4 pin connect 5V power supply, and the collector of NPN type triode Q2 connects 5V power supply, emitter is by resistance R16 ground connection, and the positive pole of polar capacitor C16 connects the emitter of NPN type triode Q2, minus earth, 1 pin of the 2nd TLP521-2 photoelectrical coupler U7B connects the emitter of NPN type triode Q2 by resistance R18, 2 pin ground connection, 3 pin are by resistance R20 ground connection, 4 pin connect 5V power supply, TTL interface J3 7 pin and 8 pin, 3 pin of 11 pin and 12 pin and a TLP521-1 photoelectrical coupler U7A, 3 pin of the 2nd TLP521-2 photoelectrical coupler U7B connect probe station 1 control end of main control chip 3.
With reference to Fig. 9, the circuit theory diagrams of the RS-232 interface circuit of the numeric class electronic watch chip tester that the embodiment of the present invention provides.
The numeric class electronic watch chip tester that the embodiment of the present invention provides, also comprises: the RS-232 interface circuit 9 connecting PC; RS-232 interface circuit 9 comprises: MAX232 chip U5, RS232 interface P1; The T2in pin of MAX232 chip U5 and R2out pin connect the PC communication ends that 3 pin of RS232 interface P1 and 2 pin, T2out pin and R2in pin connect control chip 3 respectively.
With reference to Figure 10, in the embodiment of the present invention, control chip 3 adopts ATmega128 single-chip microcomputer.
To sum up, numeric class electronic watch chip tester provided by the invention, its circuit structure is simple, and possess the test function needed for numeric class electronic watch chip such as OS parameter testing, IDD parameter testing, frequency parameter test, logic function test, while ensureing test request, therefore reduce testing cost and the production cost of numeric class electronic watch chip.
These are only the preferred embodiment of the present invention, be not limited to the present invention, all do within principle of the present invention any amendment, equivalent to replace and improvement etc., all should be included within the scope of protection of the invention.
Claims (9)
1. a numeric class electronic watch chip tester, is characterized in that, comprising:
Probe station (1);
Probe (2);
Main control chip (3);
The OS parameter detecting circuit (41) whether the protection diode on the pin of test wafer chip is intact, the OS parameter testing control end of main control chip (3) described in probe (2), controlled termination described in the test termination of described OS parameter detecting circuit (41), exports the OS parameter testing end of main control chip (3) described in termination;
The IDD parameter detecting circuit (42) of power consumption when test wafer chip works when powering on and have clock, the IDD parameter testing end of main control chip (3) described in probe (2), output termination described in the test termination of described IDD parameter detecting circuit (42);
The frequency parameter test circuit (43) of the frequency of operation of test wafer chip, the frequency parameter test control end of main control chip (3) described in probe (2), controlled termination described in the test termination of described frequency parameter test circuit (43), exports the frequency parameter test lead of main control chip (3) described in termination;
The logic function test circuit (44) of the logic function of test wafer chip, the logic function test lead of main control chip (3) described in probe (2), output termination described in the test termination of described logic function test circuit (44);
Show the display circuit (6) of the parameter information of the chip wafer tested, described display circuit (6) connects the display translation end of described main control chip (3);
The button inputting circuits (7) of input control signal, described button inputting circuits (7) connects the key-press input end of described main control chip (3);
The control signal of described main control chip (3) is transferred to the TTL interface circuit (8) of described probe station (1), described TTL interface circuit (8) connects the probe station control end of described main control chip (3);
Wherein, described OS parameter detecting circuit (41) comprising:
First operational amplifier U14A, second operational amplifier U14D, CD4051 analog switch U13, resistance R21, resistance R22, resistance R23, swept resistance R24;
The in-phase input end of described first operational amplifier U14A connects 5V power supply by described resistance R22, inverting input connects its inverting input, output terminal by first fixed end of described swept resistance R24 by described resistance R21 ground connection, positive supply termination 5V power supply, negative supply termination-5V power supply, output terminal by described resistance R23
Its first fixed end of the slip termination of described swept resistance R24,
The in-phase input end of described second operational amplifier U14D connects second fixed end of described swept resistance R24, exports the in-phase input end of its inverting input of termination and described first operational amplifier U14A;
The supply pin VDD of described CD4051 analog switch U13 connects 5V power supply, negative electricity presser feet VEE connects-5V power supply, forbid pin INH and digital signal grounding leg VSS ground connection, input and output pin 1-5 as described OS parameter detecting circuit (41) test termination described in correspond to the port of the functional pin of chip wafer in probe (2), address pin A-C as described OS parameter detecting circuit (41) controlled termination described in the DC parameter testing control end of main control chip (3), public input and output pin OUT/IN as described OS parameter detecting circuit (41) output termination described in the OS parameter testing end of main control chip (3).
2. numeric class electronic watch chip tester as claimed in claim 1, it is characterized in that, described IDD parameter detecting circuit (42) comprises the 3rd operational amplifier U15A, swept resistance R25, resistance R26, electric capacity C17;
The fixed end of described swept resistance R25 is connected to the in-phase input end of the 3rd operational amplifier U15A between 5V power supply and ground, described in slip termination,
Between the inverting input that described resistance R26 is connected to described 3rd operational amplifier U15A and output terminal,
Between the inverting input that described electric capacity C17 is connected to described 3rd operational amplifier U15A and output terminal,
The in-phase input end of described 3rd operational amplifier U15A as described IDD parameter detecting circuit (42) test termination described in correspond to the port of the power pins of chip wafer, output terminal to export main control chip (3) described in termination IDD parameter testing end as described IDD parameter detecting circuit (42) in probe (2).
3. numeric class electronic watch chip tester as claimed in claim 1, it is characterized in that, described frequency parameter test circuit (43) comprises the first comparer U18B, the second comparer U17D, the 3rd comparer U16C, the first relay R L3, the second relay R L5, the 3rd relay R L4, swept resistance R27, resistance R28, resistance R29, resistance R30, resistance R31, PNP type triode Q3;
The fixed end of described swept resistance R27 is connected between 5V power supply and ground,
The emitter of described PNP type triode Q3 by described resistance R31 connect 5V power supply, grounded collector, base stage as described frequency parameter test circuit (43) controlled termination described in the AC parameter testing control end of main control chip (3),
The inverting input of described first comparer U18B, the second comparer U17D, the 3rd comparer U16C all connects the sliding end of described swept resistance R27, output terminal all connects 5V power supply,
The output terminal of described first comparer U18B, the second comparer U17D, the 3rd comparer U16C jointly as described frequency parameter test circuit (43) output termination described in the frequency parameter test lead of main control chip (3),
Described first relay R L3, second relay R L5, the two ends of the control coil of the 3rd relay R L4 are all connected between the emitter of described PNP type triode Q3 and 5V power supply, described first relay R L3, second relay R L5, the first end of the switch of the 3rd relay R L4 meets described first comparer U18B respectively, second comparer U17D, the in-phase input end of the 3rd comparer U16C, described first relay R L3, second relay R L5, second end of the switch of the 3rd relay R L4 jointly as described frequency parameter test circuit (43) test termination described in the port of the functional pin of corresponding chip wafer in probe (2).
4. numeric class electronic watch chip tester as claimed in claim 1, it is characterized in that, described logic function test circuit (44) comprising:
E818AHF functional test chip U23;
The function logic input pin DATA of described E818AHF functional test chip U23, enable pin EN, sample logic output pin QA, sample logic output pin QB connects the function logic output pin of described main control chip (3) jointly respectively as the output terminal of described logic function test circuit (44), enable output pin, sample logic input pin, the function logic output pin DOUT of described E818AHF functional test chip U23, sample logic input pin VINP jointly as described logic function test circuit (44) test termination described in correspond to the port of the functional pin of chip wafer in probe (2).
5. numeric class electronic watch chip tester as claimed in claim 1, it is characterized in that, described display circuit (6) comprises LCM 3310 liquid crystal display J1, electric capacity C1;
The display translation end connecing described main control chip (3) of described LCM 3310 liquid crystal display J1,
Grounding leg GND ground connection, the VLCD pin of described LCM 3310 liquid crystal display J1 pass through described electric capacity C1 ground connection.
6. numeric class electronic watch chip tester as claimed in claim 1, it is characterized in that, described button inputting circuits (7) comprising:
First button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10;
The first end of described first button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10 connects 5V power supply respectively by described resistance R6, resistance R7, resistance R8, resistance R9, resistance R10,
Second end of described first button SW6, the second button SW7, the 3rd button SW8, the 4th button SW9, the 5th button SW10 connects the key-press input end of described main control chip (3) jointly.
7. numeric class electronic watch chip tester as claimed in claim 1, it is characterized in that, described TTL interface circuit (8) comprising:
TTL interface J3, NPN type triode Q1, NPN type triode Q2, a TLP521-1 photoelectrical coupler U7A, the 2nd TLP521-2 photoelectrical coupler U7B, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, resistance R20, polar capacitor C15, polar capacitor C16;
3 pin of described TTL interface J3 and 4 pin connect the base stage that the base stage of described NPN type triode Q1,17 pin and 18 pin meet described NPN type triode Q2,
The collector of described NPN type triode Q1 connects 5V power supply, emitter by described resistance R15 ground connection,
The positive pole of described polar capacitor C15 connects emitter, the minus earth of described NPN type triode Q1,
1 pin of a described TLP521-1 photoelectrical coupler U7A connects the emitter of described NPN type triode Q1 by described resistance R17,2 pin ground connection, 3 pin connect 5V power supply by described resistance R19 ground connection, 4 pin,
The collector of described NPN type triode Q2 connects 5V power supply, emitter by described resistance R16 ground connection,
The positive pole of described polar capacitor C16 connects emitter, the minus earth of described NPN type triode Q2,
1 pin of described 2nd TLP521-2 photoelectrical coupler U7B connects the emitter of described NPN type triode Q2 by described resistance R18,2 pin ground connection, 3 pin connect 5V power supply by described resistance R20 ground connection, 4 pin,
3 pin of 7 pin of described TTL interface J3 and 8 pin, 11 pin and 12 pin and a described TLP521-1 photoelectrical coupler U7A, 3 pin of described 2nd TLP521-2 photoelectrical coupler U7B connect probe station (1) control end of described main control chip (3).
8. numeric class electronic watch chip tester as claimed in claim 1, is characterized in that, also comprise:
Connect the RS-232 interface circuit (9) of PC (5);
Described RS-232 interface circuit (9) comprising: MAX232 chip U5, RS232 interface P1;
The T2in pin of described MAX232 chip U5 and R2out pin connect the PC communication ends that 3 pin of described RS232 interface P1 and 2 pin, T2out pin and R2in pin connect control chip (3) respectively.
9. the numeric class electronic watch chip tester as described in any one of claim 1-8, is characterized in that, described control chip (3) adopts ATmega128 single-chip microcomputer.
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| CN103616632B (en) * | 2013-11-23 | 2016-05-11 | 大连尚能科技发展有限公司 | Photoelectric switching circuit test fixture and method of testing |
| CN104459514A (en) * | 2014-11-04 | 2015-03-25 | 兵器工业卫生研究所 | I/O port logical detection method and system |
| CN105182265A (en) * | 2015-09-29 | 2015-12-23 | 中国电力科学研究院 | Metering chip model selection testing system |
| CN107547149B (en) * | 2016-06-27 | 2021-03-30 | 中兴通讯股份有限公司 | Radio frequency test chip |
| CN107817386A (en) * | 2017-09-15 | 2018-03-20 | 北方电子研究院安徽有限公司 | A kind of CCD wafers test device for insulation resistance |
| CN110007218A (en) * | 2018-01-04 | 2019-07-12 | 中国航发商用航空发动机有限责任公司 | Digital circuit product tester |
| CN109239575B (en) * | 2018-08-01 | 2020-12-29 | 上海移远通信技术股份有限公司 | Detection device, detection method and automatic detection system |
| CN111983427B (en) * | 2020-08-11 | 2023-10-20 | 中国兵器工业集团第二一四研究所苏州研发中心 | 16-channel analog switch circuit testing system and testing method |
| CN112198421A (en) * | 2020-12-01 | 2021-01-08 | 上海伟测半导体科技股份有限公司 | Method and device for expanding number of ATE digital channels |
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| JP2010040875A (en) * | 2008-08-06 | 2010-02-18 | Sharp Corp | Semiconductor integrated circuit, method of testing probe card and semiconductor integrated circuit |
| CN101552458A (en) * | 2008-12-29 | 2009-10-07 | 浙江中凯科技股份有限公司 | Protective circuit of a control and protection switch |
| CN201417296Y (en) * | 2009-04-28 | 2010-03-03 | 深圳安博电子有限公司 | Indicator integrated circuit test device |
| CN201417297Y (en) * | 2009-04-29 | 2010-03-03 | 深圳安博电子有限公司 | Power management chip test device |
| CN102401876B (en) * | 2010-09-17 | 2014-02-12 | 深圳安博电子有限公司 | Testing system and testing method for optoelectronic integrated circuit chip |
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