CN103052268A - Method for making circuit structure - Google Patents
Method for making circuit structure Download PDFInfo
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- CN103052268A CN103052268A CN2011103056132A CN201110305613A CN103052268A CN 103052268 A CN103052268 A CN 103052268A CN 2011103056132 A CN2011103056132 A CN 2011103056132A CN 201110305613 A CN201110305613 A CN 201110305613A CN 103052268 A CN103052268 A CN 103052268A
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- layer
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- blind hole
- conducting material
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Abstract
The invention discloses a method for making a circuit structure. The method comprises the following steps: a dielectric layer with a second surface is laminated on a first surface of a circuit substrate and a first patterned circuit layer; at least one blind hole and an engraved pattern are formed, and the blind hole extends from the second surface to the first patterned circuit layer; a patterned photoresist layer is formed on the second surface and provided with at least one opening, and the blind hole and the engraved pattern are exposed by the opening; a region where the patterned photoresist layer is positioned is defined as a first region, and a region outside the first region is defined as a second region; an activating layer is formed in the first region and the second region; the patterned photoresist layer and the activating layer in the first region are removed so as to leave the activating layer in the second region; an electricity conducting material is formed on the activating layer in the second region; and partial electricity conducting material and partial activating layer in the second region are removed.
Description
Technical field
The present invention relates to a kind of manufacture method of line construction, and particularly relate to a kind of manufacture method with the line construction on fine rule road.
Background technology
In general, the line construction of wiring board all is by photoetching and etching process or the respectively formation of laser ablation mode institute usually.Take the existing manufacture craft of utilizing the formed embedded type circuit structure of laser ablation mode as example, it may further comprise the steps.At first, provide a dielectric layer.Then, to surface irradiation one laser beam of dielectric layer, be connected to the blind hole of line layer to form an intaglio pattern and.Then, carry out a pre-treatment glue slag or legacy residual behind the laser are removed (the line layer surface of especially being come out bottom the blind hole).Then, comprehensive formation one palladium layer is on the dielectric layer surface and in formed intaglio pattern and the blind hole.Afterwards, carry out a wireless plating technology (Electroless Plating), forming on the comprehensive palladium layer that is covered in the dielectric layer surface of a chemical copper layer, and be positioned on the palladium layer of intaglio pattern and blind hole.Then, carrying out one has electric galvanoplastic (Electrical Plating) to make the copper layer fill up intaglio pattern and blind hole again.At last, remove again the lip-deep conductive copper layer of dielectric layer after, so far, the embedded type circuit structure is roughly finished.
Yet, when forming conductive copper layer by electric plating of whole board, because the degree of depth of blind hole is different from the degree of depth of intaglio pattern, therefore for really filling up blind hole and intaglio pattern, just must prolong electroplating time.Thus, also relatively form thicker conductive copper layer on the dielectric layer surface, and the follow-up lip-deep copper layer of dielectric layer that must remove is to form the embedded type circuit structure.Therefore, need long electroplating time forming Material Cost and time cost, the Material Cost that removes the lip-deep conductive copper layer of dielectric layer and the time cost of thicker conductive copper layer, and the accessory substance of deriving for the aforementioned too much and unnecessary manufacturing conditions of processing and cost of manufacture and the time cost of discarded object all are a kind of wastes.Moreover, prolong the conductive copper layer that electroplating time increases, the inhomogeneous phenomenon of thickness distribution also may be arranged, to be unfavorable for the follow-up build-up circuit layer that carries out thereon again when making, more leisure opinion is manufactured with the line construction that the low manufacture craft yield problem of the design of folded hole or higher wiring density wiring board produces and hangs down reliability.In addition, if adopt photoetching and etching process to form line construction, then can face a large amount of use chemical liquids and cause environmental pollution and increase into the problem such as product cost.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of line construction, can promote the manufacture craft yield and reduce cost of manufacture.
The present invention proposes a kind of manufacture method of line construction, and it may further comprise the steps.Pressing one dielectric layer is on a circuit base plate, and wherein circuit base plate has a first surface and one first patterned line layer, and dielectric layer has a second surface, and dielectric layer covers first surface and first patterned line layer of circuit base plate.Form blind hole and an intaglio pattern that at least one second surface from dielectric layer extends to the first patterned line layer.Form a patterning photoresist layer on the second surface of dielectric layer, wherein patterning photoresist layer has at least one opening that exposes blind hole and intaglio pattern, and the edge of at least one opening of patterning photoresist layer is away from every side more than the certain distance of blind hole or intaglio pattern.The zone definitions at patterning photoresist layer place is a first area, and the zone definitions beyond the first area is a second area.Form an active layer in first area and second area, active layer is covered in patterning photoresist layer and is positioned on second surface, intaglio pattern and the blind hole of the dielectric layer of second area.Remove patterning photoresist layer and be positioned at the active layer of first area, to stay the active layer that is positioned at second area.Form an electric conducting material on the active layer that is positioned at second area, wherein electric conducting material fills up intaglio pattern and blind hole, and covers the active layer that is positioned at second area.Remove partially conductive material and the part active layer that is positioned at second area, so that the second surface of electric conducting material and dielectric layer trims.
Based on above-mentioned, because the present invention is after forming intaglio pattern and blind hole, cover first the part second surface of dielectric layer by patterning photoresist layer, then sequentially forming active layer and electric conducting material in intaglio pattern and blind hole, wherein electric conducting material flushes with the second surface of dielectric layer.Therefore, be compared to the making of existing line structure, cost of manufacture and the waste of time cost and the problem generation that conductive copper layer has thickness distribution inequality and surface irregularity that the making of line construction of the present invention can effectively avoid existing electric plating of whole board conductive copper layer to produce, and also can avoid using etching solution in a large number and the situation that causes environmental pollution.Thus, the manufacture method of line construction of the present invention can have better reliability and manufacture craft yield and can reduce production costs.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended accompanying drawing to be described in detail below.
Description of drawings
Figure 1A to Fig. 1 G is the schematic top plan view of manufacture method of a kind of line construction of one embodiment of the invention;
Fig. 2 A to Fig. 2 G illustrates respectively along the generalized section of the line I-I of Figure 1A to Fig. 1 G.
The main element symbol description
100: line construction
110: circuit base plate
112: the core dielectric layer
113: first surface
114: the first patterned line layer
115: the three surfaces
116: the second patterned line layer
120: dielectric layer
122: intaglio pattern
122a: circuit intaglio pattern
122b: connection pad intaglio pattern
123: second surface
124: blind hole
130: patterning photoresist layer
132: opening
140: active layer
150: Seed Layer
160: electric conducting material
D: certain distance
L: laser beam
A1: first area
A2: second area
Embodiment
Figure 1A to Fig. 1 G is the schematic top plan view of manufacture method of a kind of line construction of one of the present invention embodiment.Fig. 2 A to Fig. 2 G illustrates respectively along the generalized section of the line I-I of Figure 1A to Fig. 1 G.Please also refer to Figure 1A and Fig. 2 A, manufacture method according to the line construction of present embodiment, at first, one circuit base plate 110 is provided, and wherein circuit base plate 110 has a first surface 113 respect to one another and one the 3rd surface 115, one first patterned line layer 114 and one second patterned line layer 116.In the present embodiment, the first patterned line layer 114 is disposed on the first surface 113, and the second patterned line layer 116 is disposed on the second surface 115.
It should be noted that, in the embodiment that other do not illustrate, the first patterned line layer 114 and the second patterned line layer 116 also can in be embedded in the circuit base plate 110, that is to say that the first patterned line layer 114 and the second patterned line layer 116 also can be a kind of embedded line layer.In addition, the structure of the circuit base plate 110 of present embodiment also can only have the uniline layer, or has the multilayer line layer.That is to say that circuit base plate 110 can be single-layer wire base board (single layer circuit board), double-deck circuit base plate (double layer circuit board) or multilayer wiring board (multi-layer circuit board).At this, Fig. 2 A only describes take circuit base plate 110 as the pair of lamina circuit base plate.
Then, refer again to Figure 1A and Fig. 2 A, pressing one dielectric layer 120 is on circuit base plate 110, and its dielectric layer 120 has a second surface 123, and dielectric layer 120 covers first surface 113 and first patterned line layer 114 of circuit base plate 110.
Then, please refer to Figure 1B and Fig. 2 B, form blind hole 124 and an intaglio pattern 122 that at least one second surface 123 from dielectric layer 120 extends to the first patterned line layer 114 of circuit base plate 110.In the present embodiment, the method that forms blind hole 124 and intaglio pattern 122 for example is the second surface 123 irradiations one laser beam L to dielectric layer 120, and wherein irradiating light beam L for example is infrared laser light source, ultraviolet laser light source or quasi-molecule laser source.In this mandatory declaration be, in the present embodiment, intaglio pattern 122 is comprised of at least one circuit intaglio pattern 122a and at least one connection pad intaglio pattern 122b, wherein the width of circuit intaglio pattern 122a is less than the width of connection pad intaglio pattern 122b.
Then, please refer to Fig. 1 C and Fig. 2 C, form a patterning photoresist layer 130 on the second surface 123 of dielectric layer 120, wherein patterning photoresist layer 130 covers the part of the second surface 123 of dielectric layer 120, but part the first patterned line layer 114 that patterning photoresist layer 130 does not cover blind hole 124, intaglio pattern 122 and exposed by blind hole 124.Specifically, the zone definitions at patterning photoresist layer 130 place is a first area A1, and the zone definitions beyond the A1 of first area is a second area A2.Patterning photoresist layer 130 has at least one opening 132 that exposes blind hole 124 and intaglio pattern 122, and the edge of the opening 132 of patterning photoresist layer 130 away from blind hole 124 or intaglio pattern 122 around more than the certain distance D, wherein certain distance D for example is 1 micron.
Then, please refer to Fig. 1 D and Fig. 2 D, form an active layer 140 in first area A1 and second area A2, wherein active layer 140 overlay pattern photoresist layers 130, the second surface 123 that is positioned at the dielectric layer 120 of second area A2, intaglio pattern 122, blind hole 124 and part the first patterned line layer 114 of being exposed by blind hole 124.In addition, the material of active layer 140 for example is palladium.
Then, please refer to Fig. 1 E and Fig. 2 E, remove patterning photoresist layer 130 and be positioned at the active layer 140 of first area A1, with the part of the second surface 123 that exposes the dielectric layer 120 that is positioned at patterning photoresist layer 130 below, and stay the active layer 130 that is positioned at second area A2.
Afterwards, please refer to Fig. 1 F and Fig. 2 F, form a Seed Layer 150 on active layer 140, namely Seed Layer 150 is formed in the second area A2, and wherein Seed Layer 150 covers active layer 140, and the material of Seed Layer 150 for example is copper.Then, form an electric conducting material 160 on the active layer 130 that is positioned at second area A2.Specifically, take Seed Layer 150 as electrode, electroplate (plating) electric conducting material 160 on Seed Layer 150, wherein electric conducting material 160 be positioned on the second surface 123 of dielectric layer 120 of second area A2 and the Seed Layer 150 of intaglio pattern 122 and active layer 140 tops of blind hole 124 on, and electric conducting material 160 covers the Some Species sublayer 150 of second surface 123 tops of the dielectric layer 120 that is positioned at second area A2, and fills up intaglio pattern 122 and blind hole 124.In this, be filled in the electric conducting material 160 in the circuit intaglio pattern 122a, then can form circuit (trace), and be filled in the electric conducting material 160 in the connection pad intaglio pattern 122b, then can form connection pad (pad).In addition, the material of electric conducting material 160 for example is copper.
At last, please refer to Fig. 1 G and Fig. 2 G, electric conducting material 160 is carried out a grinding steps, to remove partially conductive material 160 and the part active layer 140 and the Seed Layer 150 that are positioned at second area A2, to the second surface 123 that exposes dielectric layer 120, wherein electric conducting material 160 trims in fact with the second surface 123 of dielectric layer 120.In addition, the grinding steps of present embodiment for example is cmp (chemical mechanical polish, CMP).So far, finished the making of line construction 100.
Because present embodiment is after forming intaglio pattern 122 and blind hole 124, cover first the part second surface 123 of dielectric layer 120 by patterning photoresist layer 130, then sequentially forming active layer 140 and employing galvanoplastic in active layer formation electric conducting material 160.Therefore, form conductive copper layer compared to existing by electric plating of whole board, the making of the line construction 100 of present embodiment is (and not the place of overlay pattern photoresist layer 130) local electric conducting material 160 that forms only in specific place, can effectively avoid having now the cost of manufacture that produces on manufacture craft and the waste of time cost.In addition, the making of the line construction 100 of present embodiment also can be avoided existing and produce the inhomogeneous phenomenon of conductive copper layer thickness distribution because prolonging electroplating time.Moreover, therefore follow-up when on this line construction 100, carrying out the making of build-up circuit again because the electric conducting material 160 of present embodiment flushes in fact with the second surface 123 of dielectric layer 120, be suitable for making the design of folding the hole and having better manufacture craft yield.In addition, because present embodiment only forms electric conducting material 160 in the place of active layer 140, not to carry out comprehensive electroplating manufacturing process, and need not remove unnecessary electric conducting material with etching solution in a large number, but so Decrease production cost.In addition, because present embodiment is to adopt the mode of irradiating laser light beam L to form intaglio pattern 124, then form again electric conducting material 160 in intaglio pattern 124, so the line construction 100 of present embodiment can have the fine rule road of better reliability.
In sum, because the present invention is after forming intaglio pattern and blind hole, cover first the part second surface of dielectric layer by patterning photoresist layer, then sequentially forming active layer, Seed Layer and electric conducting material in intaglio pattern and blind hole, wherein electric conducting material flushes with the second surface of dielectric layer.Therefore, be compared to the making of existing line structure, the manufacture method of line construction of the present invention can have better reliability and manufacture craft yield and can reduce production costs.
Although disclosed the present invention in conjunction with above embodiment; yet it is not to limit the present invention; be familiar with this operator in the technical field under any; without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention should be with appended being as the criterion that claim was defined.
Claims (9)
1. the manufacture method of a line construction comprises:
Pressing one dielectric layer is on a circuit base plate, and wherein this circuit base plate has first surface and the first patterned line layer, and this dielectric layer has second surface, and this dielectric layer covers this first surface and this first patterned line layer of this circuit base plate;
Form blind hole and an intaglio pattern that at least one this second surface from this dielectric layer extends to this first patterned line layer;
Form a patterning photoresist layer on this second surface of this dielectric layer, wherein this patterning photoresist layer has at least one opening that exposes this blind hole and this intaglio pattern, and the edge of this at least one opening of this patterning photoresist layer is away from every side more than the certain distance of this blind hole or this intaglio pattern, the zone definitions at this patterning photoresist layer place is a first area, and the zone definitions beyond this first area is a second area;
Form an active layer in this first area and this second area, this active layer is covered in this patterning photoresist layer and is positioned on this second surface, this intaglio pattern and this blind hole of this dielectric layer of this second area;
Remove this patterning photoresist layer and be positioned at this active layer of this first area, to stay this active layer that is positioned at this second area;
Form an electric conducting material on this active layer that is positioned at this second area, wherein this electric conducting material fills up this intaglio pattern and this blind hole, and covers this active layer that is positioned at this second area; And
Remove this electric conducting material of part and this active layer of part that is positioned at this second area, so that this second surface of this electric conducting material and this dielectric layer trims.
2. the manufacture method of line construction as claimed in claim 1 wherein forms the method for this blind hole and this intaglio pattern, comprising:
This second surface to this dielectric layer shines a laser beam.
3. the manufacture method of line construction as claimed in claim 1, wherein this certain distance is 1 micron.
4. the manufacture method of line construction as claimed in claim 1 also comprises:
Form this electric conducting material in this intaglio pattern and this blind hole before, form a Seed Layer on this active layer.
5. the manufacture method of line construction as claimed in claim 1, wherein the method for this electric conducting material comprises galvanoplastic.
6. the manufacture method of line construction as claimed in claim 1, wherein remove this electric conducting material of part and the method that is positioned at this active layer of part of this second area, comprise this electric conducting material is carried out a grinding steps, to this second surface that exposes this dielectric layer.
7. the manufacture method of line construction as claimed in claim 6, wherein this grinding steps comprises cmp (chemical mechanical polish, CMP).
8. the manufacture method of line construction as claimed in claim 1, wherein this first patterned line layer be disposed on this first surface of this circuit base plate or in be embedded in this circuit base plate.
9. the manufacture method of line construction as claimed in claim 1, wherein this circuit base plate also has one the 3rd surface and with respect to this first surface and is positioned at the 3rd lip-deep the second patterned line layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110305613.2A CN103052268B (en) | 2011-10-11 | 2011-10-11 | The manufacture method of line construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110305613.2A CN103052268B (en) | 2011-10-11 | 2011-10-11 | The manufacture method of line construction |
Publications (2)
| Publication Number | Publication Date |
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| CN103052268A true CN103052268A (en) | 2013-04-17 |
| CN103052268B CN103052268B (en) | 2016-03-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201110305613.2A Expired - Fee Related CN103052268B (en) | 2011-10-11 | 2011-10-11 | The manufacture method of line construction |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104602462A (en) * | 2013-10-30 | 2015-05-06 | 三星电机株式会社 | Printed circuit board and manufacturing method thereof |
| CN106158811A (en) * | 2016-08-23 | 2016-11-23 | 江阴芯智联电子科技有限公司 | A kind of multi-layer support structure and manufacture method thereof |
| TWI595820B (en) * | 2016-03-17 | 2017-08-11 | 頎邦科技股份有限公司 | Pattering process of circuit substrate and circuit substrate |
| CN114269065A (en) * | 2020-09-16 | 2022-04-01 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board with embedded conductive circuit and manufacturing method thereof |
| CN114885525A (en) * | 2022-03-25 | 2022-08-09 | 深圳市大族数控科技股份有限公司 | Circuit board manufacturing method and circuit board |
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| US20050247665A1 (en) * | 2004-05-10 | 2005-11-10 | Shinko Electric Industries Co., Ltd. | Method of manufacturing an electronic parts packaging structure |
| CN101351087A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structure and technique thereof |
| CN102083280A (en) * | 2009-11-30 | 2011-06-01 | Lg伊诺特有限公司 | Embedded printed circuit board, multi-layer printed circuit board and manufacturing method thereof |
| CN102131346A (en) * | 2010-01-15 | 2011-07-20 | 欣兴电子股份有限公司 | Circuit board and manufacturing process thereof |
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2011
- 2011-10-11 CN CN201110305613.2A patent/CN103052268B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20050247665A1 (en) * | 2004-05-10 | 2005-11-10 | Shinko Electric Industries Co., Ltd. | Method of manufacturing an electronic parts packaging structure |
| CN101351087A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structure and technique thereof |
| CN102083280A (en) * | 2009-11-30 | 2011-06-01 | Lg伊诺特有限公司 | Embedded printed circuit board, multi-layer printed circuit board and manufacturing method thereof |
| CN102131346A (en) * | 2010-01-15 | 2011-07-20 | 欣兴电子股份有限公司 | Circuit board and manufacturing process thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104602462A (en) * | 2013-10-30 | 2015-05-06 | 三星电机株式会社 | Printed circuit board and manufacturing method thereof |
| TWI595820B (en) * | 2016-03-17 | 2017-08-11 | 頎邦科技股份有限公司 | Pattering process of circuit substrate and circuit substrate |
| CN106158811A (en) * | 2016-08-23 | 2016-11-23 | 江阴芯智联电子科技有限公司 | A kind of multi-layer support structure and manufacture method thereof |
| CN106158811B (en) * | 2016-08-23 | 2019-05-14 | 江阴芯智联电子科技有限公司 | A kind of multi-layer support structure and its manufacturing method |
| CN114269065A (en) * | 2020-09-16 | 2022-04-01 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board with embedded conductive circuit and manufacturing method thereof |
| CN114269065B (en) * | 2020-09-16 | 2023-08-04 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board with embedded conductive circuit and manufacturing method thereof |
| CN114885525A (en) * | 2022-03-25 | 2022-08-09 | 深圳市大族数控科技股份有限公司 | Circuit board manufacturing method and circuit board |
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| CN103052268B (en) | 2016-03-02 |
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