TWI417012B - Manufacturing method of circuit structure - Google Patents
Manufacturing method of circuit structure Download PDFInfo
- Publication number
- TWI417012B TWI417012B TW100135036A TW100135036A TWI417012B TW I417012 B TWI417012 B TW I417012B TW 100135036 A TW100135036 A TW 100135036A TW 100135036 A TW100135036 A TW 100135036A TW I417012 B TWI417012 B TW I417012B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- region
- circuit
- conductive material
- patterned
- Prior art date
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
本發明是有關於一種線路結構的製作方法，且特別是有關於一種具有細線路之線路結構的製作方法。The present invention relates to a method of fabricating a wiring structure, and more particularly to a method of fabricating a wiring structure having a thin wiring.
一般來說，線路板的線路結構通常都是透過微影與蝕刻製程或雷射燒蝕方式所分別形成。以習知利用雷射燒蝕方式所形成之埋入式線路結構的製程為例，其包括以下步驟。首先，提供一介電層。接著，對介電層的表面照射一雷射光束，以形成一凹刻圖案以及一連接至線路層的盲孔。接著，進行一前處理以將雷射後所殘留的膠渣或遺留物移除(尤其盲孔底部所暴露出來的線路層表面)。接著，全面性形成一鈀層於介電層表面上以及所形成的凹刻圖案與盲孔內。之後，進行一無電電鍍法(Electroless Plating)，以形成一化學銅層全面性覆蓋於介電層表面的鈀層上，以及位於凹刻圖案及盲孔內的鈀層上。接著，再進行一有電電鍍法(Electrical Plating)使銅層填滿凹刻圖案及盲孔。最後，再移除介電層表面上的導電銅層後，至此，埋入式線路結構已大致完成。In general, the circuit structure of a circuit board is usually formed by a lithography and etching process or a laser ablation method. For example, a process of a buried line structure formed by a laser ablation method is taken as an example, which includes the following steps. First, a dielectric layer is provided. Next, a surface of the dielectric layer is irradiated with a laser beam to form an intaglio pattern and a blind via connected to the wiring layer. Next, a pre-treatment is performed to remove the slag or remnants remaining after the laser (especially the surface of the wiring layer exposed at the bottom of the blind hole). Next, a palladium layer is formed on the surface of the dielectric layer and the indented pattern and the blind holes are formed in a comprehensive manner. Thereafter, an electroless plating (Electroless Plating) is performed to form a layer of a chemically copper layer covering the palladium layer on the surface of the dielectric layer, and on the palladium layer in the intaglio pattern and the blind via. Then, an electroplating (Electrical Plating) is performed to fill the copper layer with the intaglio pattern and the blind holes. Finally, after removing the conductive copper layer on the surface of the dielectric layer, the buried wiring structure has been substantially completed.
然而，透過全板電鍍來形成導電銅層時，由於盲孔的深度與凹刻圖案的深度不同，因此為確實填滿盲孔與凹刻圖案，就必須延長電鍍時間。如此一來，介電層表面上也相對形成較厚的導電銅層，而後續又必須移除介電層表面上的銅層以形成埋入式線路結構。因此，需要較長的電鍍時間以形成較厚的導電銅層的物料成本與時間成本、移除介電層表面上的導電銅層的物料成本與時間成本，以及為處理前述過多且不必要的製作條件所衍生的副產物與廢棄物的製作成本與時間成本都是一種浪費。再者，延長電鍍時間所增加的導電銅層，也可能有厚度分佈不均勻的現象，將不利於後續再於其上進行增層線路層製作時，更遑論製作有疊孔設計或更高布線密度線路板的低製程良率問題產生以及低可靠度的線路結構。此外，若採用微影與蝕刻製程來形成線路結構，則會面臨大量使用化學藥液而造成環境污染及增加成產成本等問題。However, when the conductive copper layer is formed by full-plate plating, since the depth of the blind hole is different from the depth of the intaglio pattern, it is necessary to extend the plating time in order to surely fill the blind hole and the intaglio pattern. As a result, a thicker conductive copper layer is also formed on the surface of the dielectric layer, and subsequently the copper layer on the surface of the dielectric layer must be removed to form a buried wiring structure. Therefore, a longer plating time is required to form the material cost and time cost of the thicker conductive copper layer, the material cost and time cost of removing the conductive copper layer on the surface of the dielectric layer, and to deal with the aforementioned excessive and unnecessary The production cost and time cost of by-products and wastes derived from the production conditions are a waste. Furthermore, the conductive copper layer which is increased by the electroplating time may also have a non-uniform thickness distribution, which is disadvantageous for the subsequent fabrication of the build-up wiring layer thereon, let alone the fabrication of a stacked hole design or a higher cloth. Low process yield problems with line density boards and low reliability line structures. In addition, if a lithography and etching process is used to form a wiring structure, there is a problem that a large amount of chemical liquid is used to cause environmental pollution and increase production cost.
本發明提供一種線路結構的製作方法，可提升製程良率並降低製作成本。The invention provides a method for manufacturing a line structure, which can improve the process yield and reduce the production cost.
本發明提出一種線路結構的製作方法，其包括以下步驟。壓合一介電層於一線路基板上，其中線路基板具有一第一表面與一第一圖案化線路層，介電層具有一第二表面，且介電層覆蓋線路基板的第一表面與第一圖案化線路層。形成至少一從介電層的第二表面延伸至第一圖案化線路層的盲孔以及一凹刻圖案。形成一圖案化光阻層於介電層之第二表面上，其中圖案化光阻層具有至少一暴露出盲孔與凹刻圖案的開口，且圖案化光阻層的至少一開口的邊緣遠離盲孔或凹刻圖案之周圍一定距離以上。圖案化光阻層所在的區域定義為一第一區域，而第一區域以外的區域定義為一第二區域。形成一活化層於第一區域與第二區域，活化層覆蓋於圖案化光阻層與位於第二區域內的介電層之第二表面、凹刻圖案與盲孔上。移除圖案化光阻層及位於第一區域內的活化層，以留下位於第二區域內的活化層。形成一導電材料於位於第二區域內的活化層上，其中導電材料填滿凹刻圖案與盲孔，且覆蓋位於第二區域內的活化層。移除部分導電材料與位於第二區域內的部分活化層，以使導電材料與介電層的第二表面切齊。The invention provides a method for fabricating a line structure, which comprises the following steps. Pressing a dielectric layer on a circuit substrate, wherein the circuit substrate has a first surface and a first patterned circuit layer, the dielectric layer has a second surface, and the dielectric layer covers the first surface of the circuit substrate The first patterned circuit layer. Forming at least one blind via extending from the second surface of the dielectric layer to the first patterned wiring layer and an intaglio pattern. Forming a patterned photoresist layer on the second surface of the dielectric layer, wherein the patterned photoresist layer has at least one opening exposing the blind via and the recessed pattern, and the edge of the at least one opening of the patterned photoresist layer is away from Blind holes or intaglio patterns are more than a certain distance around. The area where the patterned photoresist layer is located is defined as a first area, and the area other than the first area is defined as a second area. An activation layer is formed on the first region and the second region, and the activation layer covers the patterned photoresist layer and the second surface of the dielectric layer located in the second region, the intaglio pattern and the blind via. The patterned photoresist layer and the active layer in the first region are removed to leave an active layer in the second region. A conductive material is formed on the active layer in the second region, wherein the conductive material fills the intaglio pattern and the blind via and covers the active layer in the second region. A portion of the electrically conductive material is removed from the portion of the active layer in the second region to align the electrically conductive material with the second surface of the dielectric layer.
基於上述，由於本發明是於形成凹刻圖案與盲孔後，先透過圖案化光阻層覆蓋介電層的部分第二表面，而後在依序形成活化層及導電材料於凹刻圖案與盲孔內，其中導電材料與介電層的第二表面齊平。因此，相較於習知線路結構的製作，本發明之線路結構的製作可有效避免習知全板電鍍導電銅層所產生的製作成本與時間成本的浪費及導電銅層有厚度分佈不均及表面不平整的問題產生，且亦可避免大量使用蝕刻液而造成環境污染的情形。如此一來，本發明之線路結構的製作方法可具有較佳的可靠度及製程良率且可降低生產成本。Based on the above, since the present invention forms a recessed pattern and a blind via, a portion of the second surface of the dielectric layer is first covered by the patterned photoresist layer, and then the active layer and the conductive material are sequentially formed in the recessed pattern and blind. Within the aperture, wherein the electrically conductive material is flush with the second surface of the dielectric layer. Therefore, compared with the fabrication of the conventional circuit structure, the circuit structure of the present invention can effectively avoid the waste of manufacturing cost and time cost caused by the conventional full-plate electroplating conductive copper layer, and the uneven distribution of thickness and surface of the conductive copper layer. The problem of leveling occurs, and it is also possible to avoid a situation in which environmental pollution is caused by the large use of the etching liquid. In this way, the manufacturing method of the circuit structure of the present invention can have better reliability and process yield and can reduce production cost.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1A至圖1G為本發明之一實施例之一種線路結構的製作方法的俯視示意圖。圖2A至圖2G分別繪示沿圖1A至圖1G之線I-I的剖面示意圖。請同時參考圖1A與圖2A，依據本實施例之線路結構的製作方法，首先，提供一線路基板110，其中線路基板110具有彼此相對的一第一表面113與一第三表面115、一第一圖案化線路層114以及一第二圖案化線路層116。在本實施例中，第一圖案化線路層114配置於第一表面113上，而第二圖案化線路層116配置於第二表面115上。1A to 1G are schematic top views of a method of fabricating a circuit structure according to an embodiment of the present invention. 2A to 2G are schematic cross-sectional views taken along line I-I of Figs. 1A to 1G, respectively. Referring to FIG. 1A and FIG. 2A , in accordance with the method for fabricating the circuit structure of the present embodiment, first, a circuit substrate 110 is provided, wherein the circuit substrate 110 has a first surface 113 and a third surface 115 opposite to each other. A patterned circuit layer 114 and a second patterned circuit layer 116. In the embodiment, the first patterned circuit layer 114 is disposed on the first surface 113, and the second patterned circuit layer 116 is disposed on the second surface 115.
需說明的是，於其他未繪示的實施例中，第一圖案化線路層114與第二圖案化線路層116亦可內埋於線路基板110中，也就是說，第一圖案化線路層114與第二圖案化線路層116亦可為一種內埋式線路層。此外，本實施例之線路基板110的結構亦可以僅具有單一線路層，或是具有多層線路層。也就是說，線路基板110可以是單層線路基板(single layer circuit board)、雙層線路基板(double layer circuit board)或多層線路基板(multi-layer circuit board)。在此，圖2A僅以線路基板110為一雙層線路基板來進行說明。It should be noted that, in other embodiments not shown, the first patterned circuit layer 114 and the second patterned circuit layer 116 may also be buried in the circuit substrate 110, that is, the first patterned circuit layer. The 114 and second patterned circuit layer 116 can also be a buried circuit layer. In addition, the structure of the circuit substrate 110 of this embodiment may also have only a single circuit layer or a plurality of circuit layers. That is, the circuit substrate 110 may be a single layer circuit board, a double layer circuit board, or a multi-layer circuit board. Here, FIG. 2A will be described only by using the circuit substrate 110 as a two-layer circuit substrate.
接著，請再參考圖1A與圖2A，壓合一介電層120於線路基板110上，其中介電層120具有一第二表面123，且介電層120覆蓋線路基板110的第一表面113與第一圖案化線路層114。Then, referring to FIG. 1A and FIG. 2A , a dielectric layer 120 is pressed onto the circuit substrate 110 , wherein the dielectric layer 120 has a second surface 123 , and the dielectric layer 120 covers the first surface 113 of the circuit substrate 110 . And the first patterned circuit layer 114.
接著，請參考圖1B與圖2B，形成至少一從介電層120的第二表面123延伸至線路基板110之第一圖案化線路層114的盲孔124以及一凹刻圖案122。在本實施例中，形成盲孔124與凹刻圖案122的方法例如是對介電層120的第二表面123照射一雷射光束L，其中射光束L例如為紅外線雷射光源，紫外線雷射光源或準分子雷射光源。於此必須說明的是，在本實施例中，凹刻圖案122是由至少一線路凹刻圖案122a以及至少一接墊凹刻圖案122b所組成，其中線路凹刻圖案122a的寬度小於接墊凹刻圖案122b的寬度。Next, referring to FIG. 1B and FIG. 2B, at least one blind via 124 extending from the second surface 123 of the dielectric layer 120 to the first patterned wiring layer 114 of the circuit substrate 110 and an intaglio pattern 122 are formed. In the present embodiment, the method of forming the blind via 124 and the recessed pattern 122 is, for example, irradiating a second surface 123 of the dielectric layer 120 with a laser beam L, wherein the beam L is, for example, an infrared laser source, an ultraviolet laser. Light source or excimer laser source. It should be noted that, in this embodiment, the indentation pattern 122 is composed of at least one line intaglio pattern 122a and at least one pad intaglio pattern 122b, wherein the width of the line intaglio pattern 122a is smaller than the pad recess. The width of the pattern 122b is engraved.
接著，請參考圖1C與圖2C，形成一圖案化光阻層130於介電層120的第二表面123上，其中圖案化光阻層130覆蓋介電層120之第二表面123的一部分，但圖案化光阻層130並未覆蓋盲孔124、凹刻圖案122以及被盲孔124所暴露出的部分第一圖案化線路層114。具體來說，圖案化光阻層130所在的區域定義為一第一區域A1，而第一區域A1以外的區域定義為一第二區域A2。圖案化光阻層130具有至少一暴露出盲孔124與凹刻圖案122的開口132，且圖案化光阻層130的開口132的邊緣遠離盲孔124或凹刻圖案122之周圍一定距離D以上，其中一定距離D例如是1微米。Next, referring to FIG. 1C and FIG. 2C, a patterned photoresist layer 130 is formed on the second surface 123 of the dielectric layer 120, wherein the patterned photoresist layer 130 covers a portion of the second surface 123 of the dielectric layer 120. However, the patterned photoresist layer 130 does not cover the blind vias 124, the recessed patterns 122, and a portion of the first patterned wiring layer 114 exposed by the blind vias 124. Specifically, the area where the patterned photoresist layer 130 is located is defined as a first area A1, and the area other than the first area A1 is defined as a second area A2. The patterned photoresist layer 130 has at least one opening 132 exposing the blind via 124 and the recessed pattern 122, and the edge of the opening 132 of the patterned photoresist layer 130 is away from the blind via 124 or the recessed pattern 122 by a distance D or more. Where a certain distance D is, for example, 1 micron.
接著，請參考圖1D與圖2D，形成一活化層140於第一區域A1與第二區域A2，其中活化層140覆蓋圖案化光阻層130、位於第二區域A2內的介電層120的第二表面123、凹刻圖案122、盲孔124以及被盲孔124所暴露出的部分第一圖案化線路層114。此外，活化層140的材質例如是鈀。Next, referring to FIG. 1D and FIG. 2D, an active layer 140 is formed on the first region A1 and the second region A2, wherein the active layer 140 covers the patterned photoresist layer 130 and the dielectric layer 120 located in the second region A2. The second surface 123, the intaglio pattern 122, the blind vias 124, and a portion of the first patterned wiring layer 114 exposed by the blind vias 124. Further, the material of the active layer 140 is, for example, palladium.
接著，請參考圖1E與圖2E，移除圖案化光阻層130及位於第一區域A1內的活化層140，以暴露出位於圖案化光阻層130下方之介電層120之第二表面123的部分，並留下位於第二區域A2內的活化層140。Next, referring to FIG. 1E and FIG. 2E, the patterned photoresist layer 130 and the active layer 140 located in the first region A1 are removed to expose the second surface of the dielectric layer 120 under the patterned photoresist layer 130. A portion of 123 and leaving an active layer 140 located within the second region A2.
之後，請參考圖1F與圖2F，形成一種子層150於活化層140上，即種子層150形成於第二區域A2內，其中種子層150覆蓋活化層140，且種子層150的材質例如是銅。接著，形成一導電材料160於位於第二區域A2內的活化層140上。具體來說，以種子層150為電極，電鍍(plating)導電材料160於種子層150上，其中導電材料160是位於第二區域A2內之介電層120之第二表面123上以及凹刻圖案122與盲孔124內之活化層140上方的種子層150上，且導電材料160覆蓋位於第二區域A2內之介電層120之第二表面123上方的部分種子層150，且填滿凹刻圖案122以及盲孔124。於此，填充於線路凹刻圖案122a內的導電材料160，而後可形成線路(trace)，而填充於接墊凹刻圖案122b內的導電材料160，而後可形成接墊(pad)。此外，導電材料160的材質例如是銅。Thereafter, referring to FIG. 1F and FIG. 2F, a sub-layer 150 is formed on the active layer 140, that is, the seed layer 150 is formed in the second region A2, wherein the seed layer 150 covers the active layer 140, and the material of the seed layer 150 is, for example, copper. Next, a conductive material 160 is formed on the active layer 140 located in the second region A2. Specifically, the seed layer 150 is used as an electrode, and the conductive material 160 is plated on the seed layer 150, wherein the conductive material 160 is on the second surface 123 of the dielectric layer 120 in the second region A2 and the intaglio pattern 122 and the seed layer 150 above the active layer 140 in the blind via 124, and the conductive material 160 covers a portion of the seed layer 150 above the second surface 123 of the dielectric layer 120 in the second region A2, and fills the intaglio Pattern 122 and blind holes 124. Here, the conductive material 160 filled in the line recess pattern 122a is formed, and then a trace is formed to fill the conductive material 160 in the pad recess pattern 122b, and then a pad can be formed. Further, the material of the conductive material 160 is, for example, copper.
最後，請參考圖1G與圖2G，對導電材料160進行一研磨步驟，以移除部分導電材料160與位於第二區域A2內的部分活化層140及種子層150，至暴露出介電層120的第二表面123，其中導電材料160與介電層120的第二表面123實質上切齊。此外，本實施例之研磨步驟例如是 化學機械研磨(chemical mechanical polish,CMP)。至此，已完成線路結構100的製作。Finally, referring to FIG. 1G and FIG. 2G, the conductive material 160 is subjected to a grinding step to remove a portion of the conductive material 160 and the partial active layer 140 and the seed layer 150 located in the second region A2 to expose the dielectric layer 120. The second surface 123, wherein the conductive material 160 is substantially aligned with the second surface 123 of the dielectric layer 120. In addition, the grinding step of the embodiment is, for example, Chemical mechanical polish (CMP). So far, the production of the line structure 100 has been completed.
由於本實施例是於形成凹刻圖案122與盲孔124後，先透過圖案化光阻層130覆蓋介電層120的部分第二表面123，而後在依序形成活化層140及採用電鍍法於活化層上形成導電材料160。因此，相較於習知透過全板電鍍來形成導電銅層而言，本實施例之線路結構100的製作僅於特定的地方(及未覆蓋圖案化光阻層130的地方)局部形成導電材料160，可有效避免習知於製程上所產生之製作成本與時間成本的浪費。此外，本實施例之線路結構100的製作亦可避免習知因延長電鍍時間而產生導電銅層厚度分佈不均勻的現象。再者，由於本實施例之導電材料160與介電層120的第二表面123實質上齊平，因此後續於此線路結構100上再進行增層線路的製作時，適於製作疊孔的設計且具有較佳的製程良率。此外，由於本實施例僅於活化層140的地方形成導電材料160，不是進行全面性的電鍍製程，且無須大量使用蝕刻液來移除多餘的導電材料，因此可減少生產成本。另外，由於本實施例是採用照射雷射光束L的方式來形成凹刻圖案124，而後再形成導電材料160於凹刻圖案124內，因此本實施例之線路結構100可具有較佳可靠度的細線路。In this embodiment, after the recessed pattern 122 and the blind vias 124 are formed, a portion of the second surface 123 of the dielectric layer 120 is first covered by the patterned photoresist layer 130, and then the active layer 140 is sequentially formed and electroplated. A conductive material 160 is formed on the active layer. Therefore, the fabrication of the wiring structure 100 of the present embodiment partially forms a conductive material only at a specific place (and where the patterned photoresist layer 130 is not covered) as compared with the conventional method of forming a conductive copper layer by full-plate plating. 160, can effectively avoid the waste of production cost and time cost generated by the process. In addition, the fabrication of the circuit structure 100 of the present embodiment can also avoid the phenomenon that the thickness distribution of the conductive copper layer is uneven due to prolonged plating time. Moreover, since the conductive material 160 of the embodiment is substantially flush with the second surface 123 of the dielectric layer 120, the design of the stacked holes is suitable for subsequent fabrication of the build-up line on the circuit structure 100. And has a better process yield. In addition, since the present embodiment forms the conductive material 160 only at the place of the active layer 140, it is not a comprehensive plating process, and it is not necessary to use a large amount of etching liquid to remove excess conductive material, so that the production cost can be reduced. In addition, since the embodiment forms the intaglio pattern 124 by irradiating the laser beam L, and then forms the conductive material 160 in the intaglio pattern 124, the line structure 100 of the embodiment can have better reliability. Fine line.
綜上所述，由於本發明是於形成凹刻圖案與盲孔後，先透過圖案化光阻層覆蓋介電層的部分第二表面，而後在依序形成活化層、種子層及導電材料於凹刻圖案與盲孔內，其中導電材料與介電層的第二表面齊平。因此，相較於習知線路結構的製作，本發明之線路結構的製作方法可具有較佳的可靠度及製程良率且可降低生產成本。In summary, the present invention is to form a recessed pattern and a blind via, and then cover a portion of the second surface of the dielectric layer through the patterned photoresist layer, and then sequentially form an active layer, a seed layer and a conductive material. The recessed pattern is in the blind hole, wherein the conductive material is flush with the second surface of the dielectric layer. Therefore, compared with the fabrication of the conventional circuit structure, the manufacturing method of the circuit structure of the present invention can have better reliability and process yield and can reduce production cost.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100．．．線路結構100. . . Line structure
110．．．線路基板110. . . Circuit substrate
112．．．核心介電層112. . . Core dielectric layer
113．．．第一表面113. . . First surface
114．．．第一圖案化線路層114. . . First patterned circuit layer
115．．．第三表面115. . . Third surface
116．．．第二圖案化線路層116. . . Second patterned circuit layer
120．．．介電層120. . . Dielectric layer
122．．．凹刻圖案122. . . Intaglio pattern
122a．．．線路凹刻圖案122a. . . Line intaglio pattern
122b．．．接墊凹刻圖案122b. . . Pad intaglio pattern
123．．．第二表面123. . . Second surface
124．．．盲孔124. . . Blind hole
130．．．圖案化光阻層130. . . Patterned photoresist layer
132．．．開口132. . . Opening
140．．．活化層140. . . Activation layer
150．．．種子層150. . . Seed layer
160．．．導電材料160. . . Conductive material
D．．．一定距離D. . . a certain distance
L．．．雷射光束L. . . Laser beam
A1．．．第一區域A1. . . First area
A2．．．第二區域A2. . . Second area
圖1A至圖1G為本發明之一實施例之一種線路結構的製作方法的俯視示意圖。1A to 1G are schematic top views of a method of fabricating a circuit structure according to an embodiment of the present invention.
圖2A至圖2G分別繪示沿圖1A至圖1G之線I-I的剖面示意圖。2A to 2G are schematic cross-sectional views taken along line I-I of Figs. 1A to 1G, respectively.
100．．．線路結構100. . . Line structure
110．．．線路基板110. . . Circuit substrate
113．．．第一表面113. . . First surface
114．．．第一圖案化線路層114. . . First patterned circuit layer
120．．．介電層120. . . Dielectric layer
122．．．凹刻圖案122. . . Intaglio pattern
122a．．．線路凹刻圖案122a. . . Line intaglio pattern
122b．．．接墊凹刻圖案122b. . . Pad intaglio pattern
123．．．第二表面123. . . Second surface
124．．．盲孔124. . . Blind hole
140．．．活化層140. . . Activation layer
150．．．種子層150. . . Seed layer
160．．．導電材料160. . . Conductive material
A1．．．第一區域A1. . . First area
A2．．．第二區域A2. . . Second area
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100135036A TWI417012B (en) | 2011-09-28 | 2011-09-28 | Manufacturing method of circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100135036A TWI417012B (en) | 2011-09-28 | 2011-09-28 | Manufacturing method of circuit structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201315313A TW201315313A (en) | 2013-04-01 |
| TWI417012B true TWI417012B (en) | 2013-11-21 |
Family
ID=48802727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100135036A TWI417012B (en) | 2011-09-28 | 2011-09-28 | Manufacturing method of circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI417012B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI748758B (en) * | 2020-11-20 | 2021-12-01 | 健鼎科技股份有限公司 | Circuit board having asymmetrical structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200414838A (en) * | 2002-12-31 | 2004-08-01 | Intel Corp | Methods for performing substrate imprinting using thermoset resin varnishes and products formed therefrom |
| TW200850095A (en) * | 2006-12-06 | 2008-12-16 | Hitachi Via Mechanics Ltd | Laser machining method for printed circuit board |
| TW200950634A (en) * | 2008-04-30 | 2009-12-01 | Panasonic Elec Works Co Ltd | Method of producing circuit board by additive method, and circuit board and multilayer circuit board obtained by the method |
-
2011
- 2011-09-28 TW TW100135036A patent/TWI417012B/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200414838A (en) * | 2002-12-31 | 2004-08-01 | Intel Corp | Methods for performing substrate imprinting using thermoset resin varnishes and products formed therefrom |
| TW200850095A (en) * | 2006-12-06 | 2008-12-16 | Hitachi Via Mechanics Ltd | Laser machining method for printed circuit board |
| TW200950634A (en) * | 2008-04-30 | 2009-12-01 | Panasonic Elec Works Co Ltd | Method of producing circuit board by additive method, and circuit board and multilayer circuit board obtained by the method |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201315313A (en) | 2013-04-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI399150B (en) | Circuit board and process for fabricating the same | |
| TWI492690B (en) | Method for manufacturing circuit board | |
| KR101382811B1 (en) | The printed circuit board and the method for manufacturing the same | |
| TW201820944A (en) | Circuit board structure and manufacturing method thereof | |
| CN103052268B (en) | The manufacture method of line construction | |
| US9699916B2 (en) | Method of manufacturing wiring substrate, and wiring substrate | |
| US9549465B2 (en) | Printed circuit board and method of manufacturing the same | |
| TWI625991B (en) | Circuit board structure and method for forming the same | |
| CN103717014B (en) | Method for manufacturing substrate structure | |
| TWI417012B (en) | Manufacturing method of circuit structure | |
| TWI399143B (en) | Circuit board and process for fabricating the same | |
| CN102131346B (en) | Circuit board and manufacturing process thereof | |
| JP4470499B2 (en) | Multilayer wiring board manufacturing method and multilayer wiring board | |
| TWI393508B (en) | Circuit board and process for fabricating the same | |
| JP2005197418A (en) | Multilayer wiring board and manufacturing method therefor | |
| TWI405516B (en) | Circuit board and manufacturing method thereof | |
| CN210694480U (en) | Line structure with interlayer guide hole | |
| US8105938B2 (en) | Semiconductor substrate and method of manufacturing the same | |
| US9578742B1 (en) | Circuit board structure and method for manufacturing the same | |
| KR20130068658A (en) | The printed circuit board and the method for manufacturing the same | |
| KR101715941B1 (en) | The method for manufacturing the printed circuit board | |
| KR100630913B1 (en) | Making method of Printed circuit board | |
| TW201635876A (en) | Circuit board and manufacturing method thereof | |
| TWM590843U (en) | Circuit structure with inter-layer vias | |
| TW201446099A (en) | Method for manufacturing printed circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |