TW201446099A - Method for manufacturing printed circuit board - Google Patents
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本發明涉及電路板製作技術領域，尤其涉及一種封高密度電路板製作方法。The present invention relates to the field of circuit board manufacturing technology, and in particular, to a method for manufacturing a high density printed circuit board.
現有技術中，在電路板的製作過程中，通常採用增層法或者半加成法，從而得到的導電線路製作於介電層的表面。即導電線路全部凸出於介電層的表面。為了保護導電線路，通常需要在導電線路的表面形成防焊層。所述防焊層通常通過印刷防焊油墨的方式形成，在印刷形成防焊層時，需要形成的防焊層覆蓋需要覆蓋的導電線路及導電線路之間的空隙。由於導電線路層本身具有厚度，這樣，需要形成的防焊層的厚度大於導電線路的厚度。當導線線路的厚度較大時，形成的防焊層的厚度也需要增加，從而不利於電路板的薄型化的要求。In the prior art, in the process of manufacturing a circuit board, a build-up method or a semi-additive method is usually used, so that the obtained conductive line is formed on the surface of the dielectric layer. That is, the conductive lines all protrude from the surface of the dielectric layer. In order to protect the conductive lines, it is usually necessary to form a solder resist layer on the surface of the conductive lines. The solder resist layer is usually formed by printing a solder resist ink. When the solder resist layer is formed by printing, the solder resist layer to be formed covers the gap between the conductive trace and the conductive trace to be covered. Since the conductive wiring layer itself has a thickness, the thickness of the solder resist layer to be formed is larger than the thickness of the conductive wiring. When the thickness of the wire line is large, the thickness of the formed solder resist layer also needs to be increased, which is disadvantageous for the thinning of the circuit board.
並且，現有技術中的導電線路的製作方法也不利於細線路的製作。Moreover, the method of fabricating the conductive lines in the prior art is also disadvantageous for the fabrication of thin lines.
鑒於以上內容，有必要提供一種電路板的製作方法，降低電路板的防焊層的厚度，進而減小電路板的厚度。In view of the above, it is necessary to provide a method of manufacturing a circuit board, which reduces the thickness of the solder resist layer of the circuit board, thereby reducing the thickness of the circuit board.
一種電路板製作方法，包括步驟：提供覆銅基板，所述覆銅基板包括介電層及形成於介電層一表面的銅箔層；在所述覆銅基板內形成凹槽圖形，所述凹槽圖形貫穿所述銅箔層並延伸至與銅箔層相鄰的部分介電層，所述凹槽圖形的形狀與分佈與待形成的導電線路相對應；在所述凹槽圖形內及銅箔層表面形成面銅，所述面銅完全填充所述凹槽圖形；以及去除所述銅箔層及覆蓋於所述銅箔層表面的面銅，位於所述凹槽圖形內的面銅及覆蓋凹槽圖形的面銅構成導電線路。A circuit board manufacturing method comprising the steps of: providing a copper clad substrate, the copper clad substrate comprising a dielectric layer and a copper foil layer formed on a surface of the dielectric layer; forming a groove pattern in the copper clad substrate, a groove pattern extending through the copper foil layer and extending to a portion of the dielectric layer adjacent to the copper foil layer, the shape and distribution of the groove pattern corresponding to the conductive trace to be formed; Forming a surface copper on the surface of the copper foil layer, the surface copper completely filling the groove pattern; and removing the copper foil layer and the surface copper covering the surface of the copper foil layer, the copper surface located in the groove pattern And the surface copper covering the groove pattern constitutes a conductive line.
一種電路板製作方法，包括步驟：提供覆銅基板，所述覆銅基板包括介電層、形成於介電層一表面的第一銅箔層及形成於介電層另一相對表面的第二銅箔層；在所述覆銅基板內形成第一凹槽圖形和第二凹槽圖形，所述第一凹槽圖形貫穿所述第一銅箔層並延伸至與第一銅箔層相鄰的部分介電層，所述第一凹槽圖形的形狀與分佈與待形成的第一導電線路相對應，所述第二凹槽圖形貫穿所述第二銅箔層並延伸至與第二銅箔層相鄰的部分介電層，所述第二凹槽圖形的形狀與分佈與待形成的第二導電線路相對應；在所述第一凹槽圖形內及第一銅箔層表面形成第一面銅，所述第一面銅完全填充所述第一凹槽圖形，在所述第二凹槽圖形內及第二銅箔層表面形成第二面銅，所述第二面銅完全填充所述第二凹槽圖形；以及去除所述第一銅箔層及覆蓋於所述第一銅箔層表面的第一面銅，位於所述第一凹槽圖形內的第一面銅及覆蓋第一凹槽圖形的面銅構成導電線路。A circuit board manufacturing method comprising the steps of: providing a copper clad substrate, the copper clad substrate comprising a dielectric layer, a first copper foil layer formed on a surface of the dielectric layer, and a second surface formed on another opposite surface of the dielectric layer a copper foil layer; forming a first groove pattern and a second groove pattern in the copper clad substrate, the first groove pattern extending through the first copper foil layer and extending adjacent to the first copper foil layer a portion of the dielectric layer, the first groove pattern having a shape and distribution corresponding to the first conductive line to be formed, the second groove pattern extending through the second copper foil layer and extending to the second copper a portion of the dielectric layer adjacent to the foil layer, the shape and distribution of the second groove pattern corresponding to the second conductive line to be formed; forming a first surface in the first groove pattern and on the surface of the first copper foil layer a copper on one side, the first surface copper completely filling the first groove pattern, and a second surface copper is formed in the second groove pattern and on the surface of the second copper foil layer, the second surface copper is completely filled The second groove pattern; and removing the first copper foil layer and covering the first copper foil layer A first side surface of copper, and copper in the first surface of the first groove pattern coverage within a first groove pattern surface copper conductive traces.
本技術方案中，由於第一導電線路和第二導電線路部分設置於介電層內，部分凸出於介電層，這樣，在第一導電線路和第二導電線路表面形成防焊層時，可以採用厚度較小的防焊層便可以將第一導電線路層和第二導電線路層覆蓋，從而，可以降低防焊層的厚度，進而可以降低電路板的厚度。In the technical solution, since the first conductive line and the second conductive line portion are disposed in the dielectric layer, a portion protrudes from the dielectric layer, so that when the solder resist layer is formed on the surfaces of the first conductive line and the second conductive line, The first conductive wiring layer and the second conductive wiring layer can be covered by using a solder resist layer having a small thickness, so that the thickness of the solder resist layer can be reduced, and the thickness of the circuit board can be reduced.
100．．．電路板100. . . Circuit board
110．．．覆銅基板110. . . Copper clad substrate
111．．．第一銅箔層111. . . First copper foil layer
112．．．介電層112. . . Dielectric layer
1121．．．第一表面1121. . . First surface
1122．．．第二表面1122. . . Second surface
113．．．第二銅箔層113. . . Second copper foil layer
131．．．第一黑化層131. . . First blackening layer
141．．．第二黑化層141. . . Second blackening layer
130．．．第一凹槽圖形130. . . First groove pattern
140．．．第二凹槽圖形140. . . Second groove pattern
150．．．光致抗蝕劑層150. . . Photoresist layer
151．．．第一面銅151. . . First copper
152．．．第二面銅152. . . Second copper
161．．．第一導電線路161. . . First conductive line
162．．．第二導電線路162. . . Second conductive line
1611．．．第一導電部分1611. . . First conductive portion
1612．．．第二導電部分1612. . . Second conductive portion
1613．．．第一端部1613. . . First end
1614．．．第二端部1614. . . Second end
171．．．第一防焊層171. . . First solder mask
1711．．．第一開口1711. . . First opening
1615．．．第一電性接觸墊1615. . . First electrical contact pad
172．．．第二防焊層172. . . Second solder mask
1721．．．第二開口1721. . . Second opening
1621．．．第二電性接觸墊1621. . . Second electrical contact pad
圖1為本技術方案實施例提供的覆銅基板的剖面示意圖。FIG. 1 is a cross-sectional view of a copper clad substrate provided by an embodiment of the present technical solution.
圖2為圖1的覆銅基板的表面形成第一黑化層和第二黑化層後的剖面示意圖。2 is a schematic cross-sectional view showing the first blackening layer and the second blackening layer formed on the surface of the copper clad substrate of FIG. 1.
圖3為圖2的覆銅基板中形成第一凹槽圖形和第二凹槽圖形後的剖面示意圖。3 is a cross-sectional view showing the first groove pattern and the second groove pattern formed in the copper clad substrate of FIG. 2.
圖4為圖3的覆銅基板去除第一黑化層和第二黑化層後的剖面示意圖。4 is a schematic cross-sectional view showing the copper-clad substrate of FIG. 3 with the first blackening layer and the second blackening layer removed.
圖5為圖4的覆銅基板表面形成第一面銅和第二面銅後的剖面示意圖。FIG. 5 is a schematic cross-sectional view showing the first surface copper and the second surface copper formed on the surface of the copper clad substrate of FIG. 4. FIG.
圖6為圖5的第一面銅表面和第二面銅表面形成光致抗蝕劑層後的剖面示意圖。6 is a schematic cross-sectional view showing the photoresist layer formed on the first surface copper surface and the second surface copper surface of FIG. 5.
圖7為圖6形成第一導電線路和第二導電線路後的剖面示意圖。FIG. 7 is a schematic cross-sectional view showing the first conductive line and the second conductive line in FIG.
圖8為本技術方案實施例提供的電路板的剖面示意圖。FIG. 8 is a cross-sectional view of a circuit board according to an embodiment of the present technical solution.
以下，以具體事實例來說明本技術方案提供所述電路板製作方法。Hereinafter, the method for fabricating the circuit board provided by the present technical solution will be described by using a specific fact.
本技術方案實施例提供的電路板製作方法包括如下步驟:The circuit board manufacturing method provided by the embodiment of the technical solution includes the following steps:
第一步，請參閱圖1，提供覆銅基板110。In the first step, referring to FIG. 1, a copper clad substrate 110 is provided.
所述覆銅基板110為雙面覆銅基板，其包括第一銅箔層111、介電層112及第二銅箔層113。所述介電層112具有相對的第一表面1121和第二表面1122。所述第一銅箔層111形成於第一表面1121，所述第二銅箔層113形成於第二表面1122。The copper clad substrate 110 is a double-sided copper clad substrate including a first copper foil layer 111, a dielectric layer 112, and a second copper foil layer 113. The dielectric layer 112 has opposing first and second surfaces 1121, 1122. The first copper foil layer 111 is formed on the first surface 1121, and the second copper foil layer 113 is formed on the second surface 1122.
第二步，請一併參閱圖2至圖4，在所述覆銅基板110中形成第一凹槽圖形130和第二凹槽圖形140。In the second step, referring to FIG. 2 to FIG. 4, a first groove pattern 130 and a second groove pattern 140 are formed in the copper clad substrate 110.
所述第一凹槽圖形130及第二凹槽圖形140分別與欲形成的導電線路圖形相對應。所述第一凹槽圖形130貫穿第一銅箔層111並延伸至與第一銅箔層111相鄰的部分介電層112內。所述第二凹槽圖形140貫穿第二銅箔層113並延伸至與第二銅箔層113相鄰的部分介電層112內。The first groove pattern 130 and the second groove pattern 140 respectively correspond to the conductive line patterns to be formed. The first groove pattern 130 extends through the first copper foil layer 111 and extends into a portion of the dielectric layer 112 adjacent to the first copper foil layer 111. The second groove pattern 140 extends through the second copper foil layer 113 and extends into a portion of the dielectric layer 112 adjacent to the second copper foil layer 113.
在所述覆銅基板110內形成第一凹槽圖形130和第二凹槽圖形140可以採用如下方法形成：Forming the first groove pattern 130 and the second groove pattern 140 in the copper clad substrate 110 may be formed by the following method:
首先，在第一銅箔層111的表面形成第一黑化層131，在第二銅箔層113的表面形成第二黑化層141。First, a first blackening layer 131 is formed on the surface of the first copper foil layer 111, and a second blackening layer 141 is formed on the surface of the second copper foil layer 113.
具體的，可以將覆銅基板110置於黑化藥水中，使得黑化藥水於第一銅箔層111和第二銅箔層113表面的銅箔發生反應，使得第一銅箔層111和第二銅箔層113表面的銅箔被氧化而成為黑色，從而得到第一黑化層131和第二黑化層141。Specifically, the copper-clad substrate 110 can be placed in the blackening syrup so that the blackening syrup reacts on the copper foil on the surface of the first copper foil layer 111 and the second copper foil layer 113, so that the first copper foil layer 111 and the first The copper foil on the surface of the two copper foil layer 113 is oxidized to become black, thereby obtaining the first blackening layer 131 and the second blackening layer 141.
然後，採用鐳射從第一黑化層131一側在覆銅基板110內形成第一凹槽圖形130，採用鐳射從第二黑化層141一側在覆銅基板110中形成第二凹槽圖形140。本實施例中，採用的鐳射可以為準分子鐳射。通過控制採用的鐳射的能量，使得所述第一凹槽圖形130貫穿第一銅箔層111並延伸至與第一銅箔層111相鄰的部分介電層112內。所述第二凹槽圖形140貫穿第二銅箔層113並延伸至與第二銅箔層113相鄰的部分介電層112內。第一凹槽圖形130與第二凹槽圖形140並不相互連通。Then, a first groove pattern 130 is formed in the copper clad substrate 110 from the side of the first blackening layer 131 by laser, and a second groove pattern is formed in the copper clad substrate 110 from the side of the second blackening layer 141 by laser. 140. In this embodiment, the laser used may be an excimer laser. The first groove pattern 130 is penetrated through the first copper foil layer 111 and extends into a portion of the dielectric layer 112 adjacent to the first copper foil layer 111 by controlling the energy of the laser light employed. The second groove pattern 140 extends through the second copper foil layer 113 and extends into a portion of the dielectric layer 112 adjacent to the second copper foil layer 113. The first groove pattern 130 and the second groove pattern 140 are not in communication with each other.
最後，去除所述第一黑化層131和第二黑化層141。Finally, the first blackening layer 131 and the second blackening layer 141 are removed.
通過化學反應的方式，將第一黑化層131和第二黑化層141去除。The first blackening layer 131 and the second blackening layer 141 are removed by a chemical reaction.
第三步，請參閱圖5，在所述第一銅箔層111一側形成第一面銅151，在所述第二銅箔層113一側形成第二面銅152。所述第一面銅151填充所述第一凹槽圖形130並覆蓋第一銅箔層111。所述第二面銅152填充第二凹槽圖形140並覆蓋第二銅箔層113。In the third step, referring to FIG. 5, a first surface copper 151 is formed on one side of the first copper foil layer 111, and a second surface copper 152 is formed on a side of the second copper foil layer 113. The first face copper 151 fills the first groove pattern 130 and covers the first copper foil layer 111. The second face copper 152 fills the second groove pattern 140 and covers the second copper foil layer 113.
所述第一面銅151和第二面銅152可以採用如下方式形成：The first face copper 151 and the second face copper 152 may be formed as follows:
首先，在第一凹槽圖形130內、第二凹槽圖形140內、第一銅箔層111表面和第二銅箔層113表面形成金屬種子層。所述電鍍種子層可以採用化學鍍銅的方式形成。First, a metal seed layer is formed in the first groove pattern 130, in the second groove pattern 140, on the surface of the first copper foil layer 111, and on the surface of the second copper foil layer 113. The electroplated seed layer may be formed by electroless copper plating.
然後，採用電鍍的方式在所述金屬種子層表面形成電鍍銅層。形成於第一凹槽圖形130內及第一銅箔層111表面的所述電鍍銅層與所述金屬種子層共同構成第一面銅151。形成於第二凹槽圖形140內及第二銅箔層113表面的所述電鍍銅層與所述金屬種子層共同構成第二面銅152。Then, an electroplated copper layer is formed on the surface of the metal seed layer by electroplating. The electroplated copper layer formed in the first groove pattern 130 and on the surface of the first copper foil layer 111 and the metal seed layer together constitute the first face copper 151. The plated copper layer formed in the second groove pattern 140 and on the surface of the second copper foil layer 113 and the metal seed layer together constitute a second face copper 152.
第四步，請參閱圖6及圖7，通過影像轉移工藝及蝕刻工藝，去除第一銅箔層111及形成於第一銅箔層111表面的第一面銅151，從而形成於第一凹槽圖形130內及覆蓋於第一凹槽圖形130的第一面銅151構成第一導電線路161。通過影像轉移工藝及蝕刻工藝，去除第二銅箔層113及形成於第二銅箔層113表面的第二面銅152，從而形成於第二凹槽圖形140內及覆蓋於第二凹槽圖形140的第二面銅152構成第二導電線路162。In the fourth step, referring to FIG. 6 and FIG. 7, the first copper foil layer 111 and the first surface copper 151 formed on the surface of the first copper foil layer 111 are removed by the image transfer process and the etching process, thereby forming the first concave surface. The first surface copper 151 in the groove pattern 130 and covering the first groove pattern 130 constitutes the first conductive line 161. The second copper foil layer 113 and the second surface copper 152 formed on the surface of the second copper foil layer 113 are removed by the image transfer process and the etching process, thereby being formed in the second groove pattern 140 and covering the second groove pattern. The second side copper 152 of 140 constitutes a second conductive line 162.
本步驟具體可以採用如下方法實現:首先，在第一面銅151和第二面銅152的表面形成光致抗蝕劑層150。所述光致抗蝕劑層150可以通過壓合幹膜的方式形成，也可以通過印刷液態感光油墨的方式形成。然後，對所述光致抗蝕劑層150進行曝光及顯影，使得與第一凹槽圖形130對應的部分光致抗蝕劑層150留在第一面銅151表面，使得與第一銅箔層111對應的部分光致抗蝕劑層150被去除。並使得與第二凹槽圖形140對應的部分光致抗蝕劑層150留在第二面銅152表面，使得與第二銅箔層113對應的部分光致抗蝕劑層150被去除。接著，採用化學蝕刻的方式，將未被光致抗蝕劑層150覆蓋的第一面銅151、被第一面銅151覆蓋的第一銅箔層111去除，被光致抗蝕劑層150覆蓋的第一面銅151形成第一導電線路161。將未被光致抗蝕劑層150覆蓋的第二面銅152、被第二面銅152覆蓋的第二銅箔層113去除，被光致抗蝕劑層150覆蓋的第二面銅152形成第二導電線路162。最後，去除所述光致抗蝕劑層150。This step can be specifically achieved by the following method: First, a photoresist layer 150 is formed on the surfaces of the first side copper 151 and the second side copper 152. The photoresist layer 150 may be formed by pressing a dry film or by printing a liquid photosensitive ink. Then, the photoresist layer 150 is exposed and developed such that a portion of the photoresist layer 150 corresponding to the first groove pattern 130 remains on the surface of the first surface copper 151, so that the first copper foil is A portion of the photoresist layer 150 corresponding to layer 111 is removed. A portion of the photoresist layer 150 corresponding to the second groove pattern 140 is left on the surface of the second face copper 152 such that a portion of the photoresist layer 150 corresponding to the second copper foil layer 113 is removed. Next, the first copper layer 151 not covered by the photoresist layer 150 and the first copper foil layer 111 covered by the first surface copper 151 are removed by chemical etching, and the photoresist layer 150 is removed. The covered first side copper 151 forms a first conductive line 161. The second face copper 152 not covered by the photoresist layer 150, the second copper foil layer 113 covered by the second face copper 152, and the second face copper 152 covered by the photoresist layer 150 are formed. Second conductive line 162. Finally, the photoresist layer 150 is removed.
可以理解的是，在進行蝕刻的過程中，由於顯影後的光致抗蝕劑層與第一凹槽圖形130和第二凹槽圖形140相對應，即顯影後的光致抗蝕劑層與對應第一凹槽圖形130或者第二凹槽圖形140的形狀相同且寬度相等，這樣，在進行蝕刻時，由於側蝕現象的存在，使得突出於介電層112的部分導電線路的截面呈梯形。具體地，所述第一導電線路161包括位於第一凹槽圖形130內的第一導電部分1611和凸出於介電層112的第二導電部分1612。所述第一導電部分1611與第二導電部分1612相互連接。所述第二導電部分1612的橫截面的形狀為梯形。所述第二導電部分1612具有相對的第一端部1613和第二端部1614，所述第一端部1613遠離所述第一導電部分1611，所述第二端部1614與第一導電部分1611相連接。自所述第一端部1613向第二端部1614，所述第一導電部分1611的截面的寬度逐漸增加。所述第一端部1613的寬度小於所述第一導電部分1611的寬度，所述第二端部1614的寬度等於所述第一導電部分1161的寬度。It can be understood that, during the etching process, since the developed photoresist layer corresponds to the first groove pattern 130 and the second groove pattern 140, that is, the developed photoresist layer and Corresponding to the shape of the first groove pattern 130 or the second groove pattern 140 is the same and the width is equal, so that when etching is performed, the portion of the conductive line protruding from the dielectric layer 112 has a trapezoidal shape due to the existence of the side etching phenomenon. . Specifically, the first conductive line 161 includes a first conductive portion 1611 located within the first groove pattern 130 and a second conductive portion 1612 protruding from the dielectric layer 112. The first conductive portion 1611 and the second conductive portion 1612 are connected to each other. The shape of the cross section of the second conductive portion 1612 is trapezoidal. The second conductive portion 1612 has opposite first and second ends 1613, 1614, the first end 1613 being away from the first conductive portion 1611, the second end 1614 and the first conductive portion 1611 is connected. From the first end portion 1613 to the second end portion 1614, the width of the cross section of the first conductive portion 1611 gradually increases. The width of the first end portion 1613 is smaller than the width of the first conductive portion 1611, and the width of the second end portion 1614 is equal to the width of the first conductive portion 1161.
所述第二導電線路162的形狀與第一導電線路161的截面的形狀相同。The shape of the second conductive line 162 is the same as the shape of the cross section of the first conductive line 161.
第五步，請參閱圖8，在所述第一導電線路161表面及介電層112的第一表面1121形成第一防焊層171，在所述第二導電線路162表面及介電層112的第二表面1122形成第二防焊層172。進而，得到電路板100。In the fifth step, referring to FIG. 8 , a first solder resist layer 171 is formed on the surface of the first conductive line 161 and the first surface 1121 of the dielectric layer 112 , and the surface of the second conductive line 162 and the dielectric layer 112 . The second surface 1122 forms a second solder mask layer 172. Further, the circuit board 100 is obtained.
所述第一防焊層171和第二防焊層172可以採用印刷防焊油墨的方式形成。所述第一防焊層171內具有多個第一開口1711，部分第一導電線路161從第一開口1711露出，形成第一電性接觸墊1615。所述第二防焊層172內具有多個第二開口1721，部分第二導電線路162從第二開口1721露出，形成第二電性接觸墊1621。The first solder resist layer 171 and the second solder resist layer 172 may be formed by printing a solder resist ink. The first solder resist layer 171 has a plurality of first openings 1711 therein, and a portion of the first conductive traces 161 are exposed from the first openings 1711 to form a first electrical contact pad 1615. The second solder resist layer 172 has a plurality of second openings 1721 therein, and a portion of the second conductive traces 162 are exposed from the second openings 1721 to form a second electrical contact pad 1621.
可以理解的是，本技術方案的第一導電線路161和第二導電線路162可以相互電導通。即通過製作導電孔的方式將第一導電線路161和第二導電線路162相互電導通。當採用導電孔進行電導通時，可以在形成第一凹槽圖形130和第二凹槽圖形140之後，採用鐳射燒蝕的方式，將部分的第一凹槽圖形130和第二凹槽圖形140之間形成通孔而相互連通。在後續形成第一面銅151和第二面銅152時，使得所述通孔也被導電金屬填充成為導電孔，從而當形成第一導電線路161和第二導電線路162時，第一導電線路161和第二導電線路162通過所述導電孔相互電導通。It can be understood that the first conductive line 161 and the second conductive line 162 of the present technical solution can be electrically connected to each other. That is, the first conductive line 161 and the second conductive line 162 are electrically connected to each other by forming a conductive hole. When conductive holes are used for electrical conduction, portions of the first groove pattern 130 and the second groove pattern 140 may be formed by laser ablation after forming the first groove pattern 130 and the second groove pattern 140. Through holes are formed to communicate with each other. When the first surface copper 151 and the second surface copper 152 are subsequently formed, the through holes are also filled with conductive metal to form conductive holes, so that when the first conductive line 161 and the second conductive line 162 are formed, the first conductive line The 161 and the second conductive line 162 are electrically conducted to each other through the conductive via.
可以理解的是，本技術方案提供的電路板製作方法也可以用於單面電路板的製作，即提供的覆銅基板為單面覆銅基板，得到的電路板僅包括第一導電線路，而不具有第二導電線路。It can be understood that the circuit board manufacturing method provided by the technical solution can also be used for the fabrication of a single-sided circuit board, that is, the copper-clad substrate is provided as a single-sided copper-clad substrate, and the obtained circuit board only includes the first conductive line, and There is no second conductive line.
進一步地，本技術方案提供的電路板製作方法也可以用於多層電路板的製作，即在第四步之後，繼續進行增層製作，並重複第二步至第四步的操作，從而可以得到多層電路板。Further, the circuit board manufacturing method provided by the technical solution can also be used for the fabrication of the multi-layer circuit board, that is, after the fourth step, the layer-forming production is continued, and the operations of the second step to the fourth step are repeated, thereby obtaining Multi-layer circuit board.
本技術方案提供的電路板製作方法也可以應用於剛撓結合板的製作。The circuit board manufacturing method provided by the technical solution can also be applied to the fabrication of a rigid-flex board.
本技術方案中，由於第一導電線路161和第二導電線路162部分設置於介電層內，部分凸出於介電層，這樣，在第一導電線路161和第二導電線路162表面形成防焊層時，可以採用厚度較小的防焊層便可以將第一導電線路層和第二導電線路層覆蓋，從而，可以降低防焊層的厚度，進而可以降低電路板的厚度。In the technical solution, since the first conductive line 161 and the second conductive line 162 are partially disposed in the dielectric layer, a portion protrudes from the dielectric layer, so that the surfaces of the first conductive line 161 and the second conductive line 162 are formed. When the solder layer is soldered, the first conductive wiring layer and the second conductive wiring layer can be covered by using a solder mask having a small thickness, so that the thickness of the solder resist layer can be reduced, and the thickness of the circuit board can be reduced.
並且，相比於現有技術中具有相同厚度的導電電路板的電路板，第一導電線路161和第二導電線路162部分設置於介電層內，也可以降低電路板的厚度。Moreover, the first conductive line 161 and the second conductive line 162 are partially disposed in the dielectric layer compared to the circuit board having the same thickness of the conductive circuit board in the prior art, and the thickness of the circuit board can also be reduced.
進一步的，本技術方案提供的電路板製作方法也可以應用於具有細線路的電路板的製作。Further, the circuit board manufacturing method provided by the technical solution can also be applied to the fabrication of a circuit board with fine lines.
惟，以上所述者僅為本發明之較佳實施方式，自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士爰依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.
100．．．電路板100. . . Circuit board
112．．．介電層112. . . Dielectric layer
1121．．．第一表面1121. . . First surface
1122．．．第二表面1122. . . Second surface
171．．．第一防焊層171. . . First solder mask
1711．．．第一開口1711. . . First opening
1615．．．第一電性接觸墊1615. . . First electrical contact pad
172．．．第二防焊層172. . . Second solder mask
1721．．．第二開口1721. . . Second opening
1621．．．第二電性接觸墊1621. . . Second electrical contact pad
Claims (10)
提供覆銅基板，所述覆銅基板包括介電層及形成於介電層一表面的銅箔層；
在所述覆銅基板內形成凹槽圖形，所述凹槽圖形貫穿所述銅箔層並延伸至與銅箔層相鄰的部分介電層，所述凹槽圖形的形狀與分佈與待形成的導電線路相對應；
在所述凹槽圖形內及銅箔層表面形成面銅，所述面銅完全填充所述凹槽圖形；以及
去除所述銅箔層及覆蓋於所述銅箔層表面的面銅，位於所述凹槽圖形內的面銅及覆蓋凹槽圖形的面銅構成導電線路。A circuit board manufacturing method includes the steps of:
Providing a copper clad substrate, the copper clad substrate comprising a dielectric layer and a copper foil layer formed on a surface of the dielectric layer;
Forming a groove pattern in the copper clad substrate, the groove pattern extending through the copper foil layer and extending to a portion of the dielectric layer adjacent to the copper foil layer, the shape and distribution of the groove pattern to be formed Corresponding to the conductive lines;
Forming a surface copper in the groove pattern and the surface of the copper foil layer, the surface copper completely filling the groove pattern; and removing the copper foil layer and the surface copper covering the surface of the copper foil layer, located at the The surface copper in the groove pattern and the surface copper covering the groove pattern constitute a conductive line.
在所述銅箔層的表面形成黑化層；
採用準分子鐳射從黑化層一側燒蝕形成凹槽圖形；以及
去除所述黑化層。The method of fabricating a circuit board according to claim 2, wherein the forming the groove pattern comprises the steps of:
Forming a blackening layer on the surface of the copper foil layer;
Excimer laser ablation is performed from one side of the blackening layer to form a groove pattern; and the blackening layer is removed.
在所述凹槽圖形及所述銅箔層表面形成金屬種子層；以及
採用電鍍的方式在所述金屬種子層表面形成電鍍銅層，形成於凹槽圖形內及銅箔層表面的所述電鍍銅層與所述金屬種子層共同構成所述面銅。The method of fabricating a circuit board according to Item 1, wherein the forming the surface copper comprises the steps of:
Forming a metal seed layer on the surface of the groove pattern and the copper foil layer; and forming an electroplated copper layer on the surface of the metal seed layer by electroplating, forming the plating in the groove pattern and the surface of the copper foil layer The copper layer and the metal seed layer together constitute the face copper.
在所述面銅的表面形成光致抗蝕劑層；
對所述光致抗蝕劑層進行曝光及顯影，使得與所述凹槽圖形對應的部分光致抗蝕劑層留在面銅表面，使得與銅箔層對應的部分光致抗蝕劑層被去除；
採用化學蝕刻的方式，將未被光致抗蝕劑層覆蓋的面銅、被面銅覆蓋的銅箔層去除，被光致抗蝕劑層覆蓋的面銅形成導電線路，凸出於介電層的部分導電線路的截面呈梯形；以及
去除所述光致抗蝕劑層。The circuit board manufacturing method of claim 1, wherein the forming the conductive line comprises the steps of:
Forming a photoresist layer on the surface of the surface copper;
Exposing and developing the photoresist layer such that a portion of the photoresist layer corresponding to the recess pattern remains on the surface copper surface such that a portion of the photoresist layer corresponding to the copper foil layer Be removed
The surface copper not covered by the photoresist layer and the copper foil layer covered by the copper layer are removed by chemical etching, and the surface copper covered by the photoresist layer forms a conductive line, which is exposed to dielectric A portion of the conductive traces of the layer are trapezoidal in cross section; and the photoresist layer is removed.
提供覆銅基板，所述覆銅基板包括介電層、形成於介電層一表面的第一銅箔層及形成於介電層另一相對表面的第二銅箔層；
在所述覆銅基板內形成第一凹槽圖形和第二凹槽圖形，所述第一凹槽圖形貫穿所述第一銅箔層並延伸至與第一銅箔層相鄰的部分介電層，所述第一凹槽圖形的形狀與分佈與待形成的第一導電線路相對應，所述第二凹槽圖形貫穿所述第二銅箔層並延伸至與第二銅箔層相鄰的部分介電層，所述第二凹槽圖形的形狀與分佈與待形成的第二導電線路相對應；
在所述第一凹槽圖形內及第一銅箔層表面形成第一面銅，所述第一面銅完全填充所述第一凹槽圖形，在所述第二凹槽圖形內及第二銅箔層表面形成第二面銅，所述第二面銅完全填充所述第二凹槽圖形；以及
去除所述第一銅箔層及覆蓋於所述第一銅箔層表面的第一面銅，位於所述第一凹槽圖形內的第一面銅及覆蓋第一凹槽圖形的面銅構成導電線路。A circuit board manufacturing method includes the steps of:
Providing a copper clad substrate, the copper clad substrate comprising a dielectric layer, a first copper foil layer formed on a surface of the dielectric layer, and a second copper foil layer formed on another opposite surface of the dielectric layer;
Forming a first groove pattern and a second groove pattern in the copper clad substrate, the first groove pattern penetrating through the first copper foil layer and extending to a portion adjacent to the first copper foil layer a layer, the shape and distribution of the first groove pattern corresponding to a first conductive line to be formed, the second groove pattern extending through the second copper foil layer and extending adjacent to the second copper foil layer a portion of the dielectric layer, the shape and distribution of the second groove pattern corresponding to the second conductive line to be formed;
Forming a first surface copper in the first groove pattern and on a surface of the first copper foil layer, the first surface copper completely filling the first groove pattern, and in the second groove pattern and second Forming a second surface copper on the surface of the copper foil layer, the second surface copper completely filling the second groove pattern; and removing the first copper foil layer and the first surface covering the surface of the first copper foil layer Copper, the first surface copper located in the first groove pattern and the surface copper covering the first groove pattern constitute a conductive line.
在所述第一銅箔層的表面形成第一黑化層，並在所述第二銅箔層表面形成第二黑化層；
採用準分子鐳射從第一黑化層一側燒蝕形成第一凹槽圖形，從第二黑化層一側燒蝕形成第二凹槽圖形；以及
去除所述第一黑化層和第二黑化層。The method for fabricating a circuit board according to claim 7, wherein the forming the first groove pattern and the second groove pattern comprises the steps of:
Forming a first blackening layer on a surface of the first copper foil layer, and forming a second blackening layer on a surface of the second copper foil layer;
Forming a first groove pattern from one side of the first blackening layer by excimer laser, ablation forming a second groove pattern from a side of the second blackening layer; and removing the first blackening layer and the second Blackening layer.
在所述第一凹槽圖形內、第二凹槽圖形內、所述第一銅箔層表面及第二銅箔層表面形成金屬種子層；以及
採用電鍍的方式在所述金屬種子層表面形成電鍍銅層，形成於第一凹槽圖形內及第一銅箔層表面的所述電鍍銅層與所述金屬種子層共同構成所述第一面銅，形成於第二凹槽圖形內及第二銅箔層表面的所述電鍍銅層與所述金屬種子層共同構成所述第二面銅。The method of fabricating a circuit board according to claim 6, wherein the forming the first surface copper and the second surface copper comprises the steps of:
Forming a metal seed layer in the first groove pattern, in the second groove pattern, on the surface of the first copper foil layer and the surface of the second copper foil layer; and forming on the surface of the metal seed layer by electroplating An electroplated copper layer, the electroplated copper layer formed in the first groove pattern and the surface of the first copper foil layer and the metal seed layer together form the first surface copper, formed in the second groove pattern and The electroplated copper layer on the surface of the two copper foil layers and the metal seed layer together constitute the second surface copper.
在所述第一面銅的表面和第二面銅的表面形成光致抗蝕劑層；
對所述光致抗蝕劑層進行曝光及顯影，使得與所述第一凹槽圖形對應的部分光致抗蝕劑層留在第一面銅表面，使得與第一銅箔層對應的部分光致抗蝕劑層被去除，使得與所述第二凹槽圖形對應的部分光致抗蝕劑層留在第二面銅表面，使得與第二銅箔層對應的部分光致抗蝕劑層被去除；
採用化學蝕刻的方式，將未被光致抗蝕劑層覆蓋的第一面銅及被第一面銅覆蓋的第一銅箔層、未被光致抗蝕劑層覆蓋的第二面銅及被第二面銅覆蓋的第二銅箔層去除，被光致抗蝕劑層覆蓋的第一面銅形成第一導電線路，被光致抗蝕劑層覆蓋的第二面銅形成第二導電線路，凸出於介電層的部分第一導電線路和第二導電線路的截面呈梯形；以及
去除所述光致抗蝕劑層。
The method of fabricating a circuit board according to claim 6, wherein the forming the first conductive line and the second conductive line comprises the steps of:
Forming a photoresist layer on the surface of the first face copper and the surface of the second face copper;
Exposing and developing the photoresist layer such that a portion of the photoresist layer corresponding to the first recess pattern remains on the first surface copper surface such that a portion corresponding to the first copper foil layer The photoresist layer is removed such that a portion of the photoresist layer corresponding to the second groove pattern remains on the second face copper surface such that a portion of the photoresist corresponding to the second copper foil layer The layer is removed;
The first surface copper not covered by the photoresist layer and the first copper foil layer covered by the first surface copper, the second surface copper not covered by the photoresist layer, and the chemical etching method The second copper foil layer covered by the second copper is removed, the first surface copper covered by the photoresist layer forms a first conductive line, and the second surface copper covered by the photoresist layer forms a second conductive a portion of the first conductive line and the second conductive line protruding from the dielectric layer have a trapezoidal cross section; and the photoresist layer is removed.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310204276.7A CN104219892A (en) | 2013-05-29 | 2013-05-29 | A method for manufacturing circuit board |
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| TW201446099A true TW201446099A (en) | 2014-12-01 |
| TWI479965B TWI479965B (en) | 2015-04-01 |
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| CN106686893A (en) * | 2015-11-11 | 2017-05-17 | 上海嘉捷通电路科技股份有限公司 | Manufacturing method for pattern in stepped groove |
| CN112312671B (en) * | 2019-07-30 | 2024-03-12 | 宏恒胜电子科技（淮安）有限公司 | Circuit board and preparation method thereof |
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| DE102004005300A1 (en) * | 2004-01-29 | 2005-09-08 | Atotech Deutschland Gmbh | Process for treating carrier material for the production of powder carriers and application of the process |
| CN101124861B (en) * | 2005-11-02 | 2011-03-30 | 揖斐电株式会社 | Multilayer printed wiring board for semiconductor device and process for producing the same |
| CN101351088B (en) * | 2007-07-17 | 2010-06-23 | 欣兴电子股份有限公司 | Inside imbedded type line structure and technique thereof |
| CN101610646B (en) * | 2008-06-20 | 2012-05-30 | 欣兴电子股份有限公司 | Electrical connection structure as well as technology and circuit board structure thereof |
| TWI406384B (en) * | 2008-07-25 | 2013-08-21 | Unimicron Technology Corp | Package substrate and fabrication method thereof |
| JP5512562B2 (en) * | 2010-03-29 | 2014-06-04 | 日本特殊陶業株式会社 | Multilayer wiring board |
| KR101181048B1 (en) * | 2010-12-27 | 2012-09-07 | 엘지이노텍 주식회사 | The method for manufacturing the printed circuit board |
| CN103687339B (en) * | 2012-09-26 | 2017-03-01 | 碁鼎科技秦皇岛有限公司 | Circuit board and preparation method thereof |
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| CN104219892A (en) | 2014-12-17 |
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