CN102131346A - Circuit board and manufacturing process thereof - Google Patents
Circuit board and manufacturing process thereof Download PDFInfo
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- CN102131346A CN102131346A CN2010100045019A CN201010004501A CN102131346A CN 102131346 A CN102131346 A CN 102131346A CN 2010100045019 A CN2010100045019 A CN 2010100045019A CN 201010004501 A CN201010004501 A CN 201010004501A CN 102131346 A CN102131346 A CN 102131346A
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- layer
- conductive layer
- blind hole
- wiring board
- base plate
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Abstract
A circuit board comprises a circuit substrate, a medium layer, a first conductive layer and a second conductive layer. The circuit substrate has a first surface and a first circuit layer. The medium layer is arranged on the circuit substrate and covers the first surface and the first circuit layer. The medium layer has a second surface, at least one blind hole extending from the second surface to the first circuit layer and a first intagliated pattern. The first conductive layer is arranged in the blind hole. The second conductive layer is arranged in the intagliated pattern and the blind hole and covers the first conductive layer. The second conductive layer is electrically connected to the first circuit layer through the first conductive layer.
Description
Technical field
The invention relates to a kind of wiring board (circuit board) and processing procedure thereof, and particularly about a kind of wiring board and processing procedure thereof with preferable reliability.
Background technology
Wiring board technology now develops into buried circuit board (embedded circuit board) from general common non-buried circuit board.In detail, general common non-buried circuit board is characterised in that its circuit is to give prominence on the surface of dielectric layer, and buried circuit board is characterised in that its circuit is embedded in the dielectric layer in being.The line construction of wiring board all is to form respectively by lithographic process or laser ablation mode institute usually.
Utilizing the processing procedure of the build-up circuit structure of the formed buried circuit board of laser ablation mode with tradition is example, and it may further comprise the steps.At first, provide a dielectric layer to have on the circuit base plate of a line layer one.Then, at surface irradiation one laser beam of dielectric layer, to form the blind hole that an intaglio pattern and is connected to line layer.Afterwards, carry out electroplating process fills up blind hole and intaglio pattern with formation conductive layer.So far, the build-up circuit structure of buried circuit board is roughly finished.
Yet, therefore not good because of the control of plating condition easily when carrying out electroplating process because the degree of depth of blind hole is different with the degree of depth of intaglio pattern, and make formed conductive layer that the uneven phenomenon of thickness distribution be arranged.Thus, when follow-up when removing the conductive layer that is positioned at beyond intaglio pattern and the blind hole, with the thickness of the wayward conductive layer that removes so that easily in the process that removes the conductive layer of improper thinning built-in type or improper residual unnecessary electric conducting material on dielectric layer.In addition, the follow-up build-up circuit layer that carries out on this dielectric layer again is when making, and electroplating process has easily that quality is bad to be produced with problems such as yields are not high, thus, easily reduces the processing procedure yields of build-up circuit structure, and then reduces the reliability of wiring board.
Summary of the invention
The invention provides a kind of wiring board and processing procedure thereof, can promote the reliability of wiring board.
The present invention proposes a kind of wiring board, and it comprises a circuit base plate, a dielectric layer, one first conductive layer and one second conductive layer.Circuit base plate has a first surface and one first line layer.Dielectric layer is configured on the circuit base plate and covers the first surface and first line layer.Dielectric layer has a second surface, an at least one blind hole and intaglio pattern that extends to first line layer from second surface.First conductive layer is configured in the blind hole.Second conductive layer is configured in intaglio pattern and the blind hole, and covers first conductive layer.Second conductive layer is electrically connected to first line layer by first conductive layer.
In one embodiment of this invention, the degree of depth of above-mentioned blind hole is H, and the thickness of first conductive layer is h, and 0.2≤(h/H)≤0.9.
In one embodiment of this invention, above-mentioned intaglio pattern is connected with blind hole.
In one embodiment of this invention, above-mentioned wiring board also comprises an active layer, is configured between the intaglio pattern of dielectric layer and second conductive layer and is configured between first conductive layer and second conductive layer.
In one embodiment of this invention, be embedded in the circuit base plate in the first above-mentioned line layer, and a surface of first line layer trims in fact with first surface.
In one embodiment of this invention, the first above-mentioned line layer is configured on the first surface of circuit base plate.
In one embodiment of this invention, above-mentioned second conductive layer and the second surface of dielectric layer trim in fact.
The present invention also proposes a kind of processing procedure of wiring board.At first, provide a circuit base plate.Circuit base plate has a first surface and at least one first line layer.Then, form a dielectric layer on circuit base plate.Dielectric layer has a second surface, and dielectric layer covers the first surface and first line layer.Second surface to dielectric layer shines a laser beam, to form a blind hole and the intaglio pattern that at least one second surface from dielectric layer extends to first line layer.Then, form one first conductive layer in blind hole.At last, form one second conductive layer in intaglio pattern and blind hole.Second conductive layer covers first conductive layer, and second conductive layer is electrically connected to first line layer by first conductive layer.
In one embodiment of this invention, above-mentioned laser beam is infrared laser light source or ultraviolet laser light source.
In one embodiment of this invention, the method for above-mentioned formation first conductive layer in blind hole comprises chemical deposition.
In one embodiment of this invention, the degree of depth of above-mentioned blind hole is H, and the thickness of first conductive layer is h, and 0.2≤(h/H)≤0.9.
In one embodiment of this invention, before above-mentioned formation second conductive layer, also comprise forming an active layer on the second surface of dielectric layer, in the intaglio pattern and on first conductive layer.
In one embodiment of this invention, the method for above-mentioned formation second conductive layer in intaglio pattern and blind hole comprises chemical deposition.
In one embodiment of this invention, after above-mentioned formation second conductive layer, comprise that also second conductive layer is carried out one grinds processing procedure, to the second surface that exposes dielectric layer.
In one embodiment of this invention, be embedded in the circuit base plate in the first above-mentioned line layer, and a surface of first line layer trims in fact with first surface.
In one embodiment of this invention, the first above-mentioned line layer is configured on the first surface of circuit base plate.
In one embodiment of this invention, above-mentioned intaglio pattern is connected with blind hole.
In one embodiment of this invention, above-mentioned second conductive layer and the second surface of dielectric layer trim in fact.
Based on above-mentioned because the processing procedure of wiring board of the present invention is to form first conductive layer earlier in blind hole, to reduce difference in height between blind hole and the intaglio pattern, then, form again on first conductive layer of second conductive layer in blind hole with intaglio pattern in.Thus, can make the conductive layer that is formed in blind hole and the intaglio pattern can have preferable the thickness uniformity and surface smoothness.Compared to the making of traditional circuit plate, wiring board of the present invention and processing procedure thereof, it is not enough or excessively and problem such as the conductive layer uniformity is not good effectively to avoid tradition to electroplate the filling perforation effect, has better reliability degree.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the generalized section of a kind of wiring board of one embodiment of the present of invention.
Fig. 2 A to Fig. 2 F is the generalized section of processing procedure of a kind of wiring board of one embodiment of the present of invention.
The main element symbol description
100: wiring board
110: circuit base plate
112: first surface
114: the first line layers
120: dielectric layer
122: second surface
124a, 124b: blind hole
126: intaglio pattern
130: the first conductive layers
140: the second conductive layers
150: active layer
L: laser beam
H, h: thickness
Embodiment
Fig. 1 is the generalized section of a kind of wiring board of one embodiment of the present of invention.Please refer to Fig. 1, in the present embodiment, wiring board 100 comprises a circuit base plate 110, a dielectric layer 120, one first conductive layer 130 and one second conductive layer 140.What deserves to be mentioned is that the structure of wiring board 100 can only have the uniline layer, or have the multilayer line layer.That is to say that wiring board 100 can be individual layer wiring board (single layer circuit board), double-deck wiring board (double layer circuit board) or multilayer circuit board (multi-layer circuit board).In the present embodiment, Fig. 1 is that a build-up circuit board describes with wiring board 100 only.
In detail, circuit base plate 110 has a first surface 112 and one first line layer 114, and wherein first line layer 114 is configured on the first surface 112 of circuit base plate 110.That is to say that first line layer 114 can a kind of at last general line layer (non-embedded line layer).This mandatory declaration be, in the embodiment shown in fig. 1, though first line layer 114 is to be configured on the first surface 112 of circuit base plate 110.But, in other unshowned embodiment, first line layer 114 also can in be embedded in the circuit base plate 110, and a surface of first line layer 114 trims in fact with first surface 112.Anticipate promptly, first line layer 114 basically can a kind of at last embedded line layer.In other words, the structure of circuit base plate 110 shown in Figure 1 is only for illustrating, and non-limiting the present invention.
First conductive layer 130 is configured in blind hole 124a, the 124b, and wherein the degree of depth of blind hole 124b (or blind hole 124a) is H, and the thickness of first conductive layer 130 is h, preferably, and 0.2≤(h/H)≤0.9.Second conductive layer 140 is configured in intaglio pattern 126 and blind hole 124a, the 124b, and covers first conductive layer 130.That is to say that second conductive layer 140 is configured in the intaglio pattern 126 and on first conductive layer 130.Particularly, second conductive layer 140 can be electrically connected to first line layer 114 of circuit base plate 110 by first conductive layer 130, and the second surface 122 of second conductive layer 140 and dielectric layer 120 trims in fact.
In addition, the wiring board 100 of present embodiment also comprises an active layer 150, and wherein active layer 150 is configured between the intaglio pattern 126 of dielectric layer 120 and second conductive layer 140 and is configured between first conductive layer 130 and second conductive layer 140.Wherein, the material composition of active layer 150 comprises metal, and it for example is a palladium.
Owing to dispose first conductive layer 130 in blind hole 124a, the 124b of the dielectric layer 120 of present embodiment, therefore can reduce the difference in height between blind hole 124a, 124b and the intaglio pattern 126.If when (h/H) big more, the meaning i.e. thickness of first conductive layer 130 is thicker, can make the thickness of second conductive layer 140 of blind hole 124a, the configuration of 124b domestic demand level off to the thickness of second conductive layer 140 of intaglio pattern 126 desires configuration.Thus, when second conductive layer 140 is configured in blind hole 124a, 124b and intaglio pattern 126, can have preferable the thickness uniformity and surface smoothness.In other words, compared to conventional art, it is not enough or excessively and problem such as the conductive layer uniformity is not good that the design of the wiring board 100 of present embodiment can effectively avoid tradition to electroplate the filling perforation effect, has better reliability degree.
Below only introduce the structure of wiring board 100 of the present invention, do not introduce the processing procedure of wiring board 100 of the present invention.To this, below will illustrate as an example, and cooperate Fig. 2 A to Fig. 2 F that the processing procedure of wiring board 100 of the present invention is described in detail with the structure of the wiring board among Fig. 1 100.
Fig. 2 A to Fig. 2 F is the generalized section of processing procedure of a kind of wiring board of one embodiment of the present of invention.Please refer to Fig. 2 A, the processing procedure according to the wiring board 100 of present embodiment at first, provides a circuit base plate 110.Circuit base plate 110 has a first surface 112 and one first line layer 114, and wherein first line layer 114 is configured on the first surface 112 of circuit base plate 110.In other words, first line layer 114 basically can a kind of at last general line layer (being non-embedded line layer).This mandatory declaration be, in other unshowned embodiment, first line layer 114 also can in be embedded in the circuit base plate 110, and a surface of first line layer 114 trims in fact with first surface 112.Anticipate promptly, first line layer 114 basically can a kind of at last embedded line layer.Therefore, circuit base plate 110 structures shown in Fig. 2 A are only for illustrating, and non-limiting the present invention.
Then, refer again to Fig. 2 A, form a dielectric layer 120 on circuit base plate 110, wherein dielectric layer 120 has a second surface 122, and dielectric layer 120 covers the first surface 112 and first line layer 114.
Then, please refer to Fig. 2 B, to the second surface 122 irradiation one laser beam L of dielectric layer 120, at least onely extend to the blind hole (two blind hole 124a, 124b only schematically are shown Fig. 2 B) and an intaglio pattern 126 of first line layer 114 from the second surface 122 of dielectric layer 120 to form.Wherein, intaglio pattern 126 is connected with blind hole 124a.In the present embodiment, laser beam L for example is infrared laser light source or ultraviolet laser light source.
Then, please refer to Fig. 2 C, form one first conductive layer 130 in blind hole 124a, 124b.Wherein, form the method for first conductive layer 130 in blind hole 124a, 124b and comprise chemical deposition.Particularly, in the present embodiment, the degree of depth of blind hole 124b (or blind hole 124b) is H, and the thickness of first conductive layer 130 is h, preferably, and 0.2≤(h/H)≤0.9.
Then, please refer to Fig. 2 D, form an active layer 150 on the second surface 122 of dielectric layer 120, in the intaglio pattern 126 and on first conductive layer 130, make the initiation that produces the chemical deposition reaction in order on dielectric layer 120 surfaces, to have, in order to forming second conductive layer 140 (please refer to Fig. 2 E), and continue at first conductive layer 130 and to form second conductive layer 140, fill up electric conducting material and finish blind hole.In the present embodiment, the main material composition of active layer 150 for example is a palladium.
Then, please refer to Fig. 2 E, form one second conductive layer 140 in intaglio pattern 126 and blind hole 124a, 124b, wherein second conductive layer 140 covers first conductive layer 130, and second conductive layer 140 is electrically connected to first line layer 114 by first conductive layer 130.At this moment, the second surface 122 of second conductive layer, 140 blanket dielectric layer 120.In addition, form the method for second conductive layer 140 in intaglio pattern 126 and blind hole 124a, 124b and comprise chemical deposition.
At last, please refer to Fig. 2 F, second conductive layer 140 is carried out one grind processing procedure, to the second surface 122 that exposes dielectric layer 120.That is to say, can remove the active layer 150 on the second surface 122 that is positioned at dielectric layer 120 behind the grinding processing procedure, and expose second surface 122, so that the second surface 122 of second conductive layer 140 and dielectric layer 120 trims in fact.So far, to finish the making of wiring board 100.
In this mandatory declaration be, though present embodiment grinds processing procedure after forming second conductive layer 140, but in other unshowned embodiment, when preferable, then can omit the step of grinding processing procedure as if the surface smoothness of second conductive layer 140 that is deposited.In other words, the surface smoothness that the described grinding fabrication steps of present embodiment is visual second conductive layer 140 that deposits determines whether the selectivity step implemented and non-essential fabrication steps.
Because the processing procedure of the wiring board 100 of present embodiment is to form first conductive layer 130 earlier in blind hole 124a, 124b, to reduce difference in height between blind hole 124a, 124b and the intaglio pattern 126, then, form again on first conductive layer 130 of second conductive layer 140 in blind hole 124a, 124b with intaglio pattern 126 in.Thus, can make the conductive layer that is formed in blind hole 124a, 124b and the intaglio pattern 126 can have preferable the thickness uniformity and surface smoothness.Compared to the making of traditional circuit plate, it is not enough or excessively and problem such as the conductive layer uniformity is not good that the processing procedure of the wiring board 100 of present embodiment can effectively avoid tradition to electroplate the filling perforation effect, has better reliability degree.
In sum,, therefore can effectively reduce difference in height between blind hole and the intaglio pattern, so that the thickness of second conductive layer of blind hole domestic demand configuration levels off to the intaglio pattern desire and disposes the thickness of second conductive layer because the present invention disposes first conductive layer in blind hole.Thus, when second conductive layer is configured in blind hole and intaglio pattern, can have preferable the thickness uniformity and surface smoothness.Compared to conventional art, it is not enough or excessively and problem such as the conductive layer uniformity is not good that the design of wiring board of the present invention can effectively avoid tradition to electroplate the filling perforation effect, has better reliability degree.
Though the present invention with embodiment openly as above; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (15)
1. wiring board comprises:
One circuit base plate has a first surface and one first line layer;
One dielectric layer is configured on this circuit base plate and covers this first surface and this first line layer, and this dielectric layer has a second surface, an at least one blind hole and intaglio pattern that extends to this first line layer from this second surface;
One first conductive layer is configured in this blind hole; And
One second conductive layer is configured in this intaglio pattern and this blind hole, and covers this first conductive layer, and wherein this second conductive layer is electrically connected to this first line layer by this first conductive layer.
2. wiring board according to claim 1 also comprises an active layer, is configured between this intaglio pattern of this dielectric layer and this second conductive layer and is configured between this first conductive layer and this second conductive layer.
3. wiring board according to claim 1 and 2, wherein the degree of depth of this blind hole is H, and the thickness of this first conductive layer is h, and 0.2≤(h/H)≤0.9.
4. wiring board according to claim 1 wherein is embedded in this circuit base plate in this first line layer, and a surface of this first line layer trims in fact with this first surface.
5. wiring board according to claim 1, wherein this first line layer is configured on this first surface of this circuit base plate.
6. according to claim 1,4 or 5 described wiring boards, wherein this second surface of this second conductive layer and this dielectric layer trims in fact.
7. the processing procedure of a wiring board comprises:
One circuit base plate is provided, and this circuit base plate has a first surface and one first line layer;
Form a dielectric layer on this circuit base plate, this dielectric layer has a second surface, and this dielectric layer covers this first surface and this first line layer;
This second surface to this dielectric layer shines a laser beam, to form a blind hole and the intaglio pattern that at least one this second surface from this dielectric layer extends to this first line layer;
Form one first conductive layer in this blind hole; And
Form one second conductive layer in this intaglio pattern and this blind hole, wherein this second conductive layer covers this first conductive layer, and this second conductive layer is electrically connected to this first line layer by this first conductive layer.
8. the processing procedure of wiring board according to claim 7 wherein before forming this second conductive layer, also comprises:
Form an active layer on this second surface of this dielectric layer, in this intaglio pattern and on this first conductive layer.
9. the processing procedure of wiring board according to claim 7, wherein the degree of depth of this blind hole is H, and the thickness of this first conductive layer is h, and 0.2≤(h/H)≤0.9.
10. according to the processing procedure of claim 7 or 9 described wiring boards, wherein form the method for this first conductive layer in this blind hole and comprise chemical deposition.
11. the processing procedure of wiring board according to claim 7 wherein forms the method for this second conductive layer in this intaglio pattern and this blind hole and comprises chemical deposition.
12., wherein after forming this second conductive layer, also comprise according to the processing procedure of claim 7 or 11 described wiring boards:
This second conductive layer is carried out one grind processing procedure, to this second surface that exposes this dielectric layer.
13. the processing procedure of wiring board according to claim 7 wherein is embedded in this circuit base plate in this first line layer, and a surface of this first line layer trims in fact with this first surface.
14. the processing procedure of wiring board according to claim 7, wherein this first line layer is configured on this first surface of this circuit base plate.
15. according to the processing procedure of claim 7,13 or 14 described wiring boards, wherein this second surface of this second conductive layer and this dielectric layer trims in fact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010004501.9A CN102131346B (en) | 2010-01-15 | 2010-01-15 | Circuit board and manufacturing process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010004501.9A CN102131346B (en) | 2010-01-15 | 2010-01-15 | Circuit board and manufacturing process thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN102131346A true CN102131346A (en) | 2011-07-20 |
| CN102131346B CN102131346B (en) | 2014-08-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201010004501.9A Expired - Fee Related CN102131346B (en) | 2010-01-15 | 2010-01-15 | Circuit board and manufacturing process thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103052268A (en) * | 2011-10-11 | 2013-04-17 | 欣兴电子股份有限公司 | Method for making circuit structure |
| CN103517576A (en) * | 2012-06-19 | 2014-01-15 | 深南电路有限公司 | Printed circuit board processing method, printed circuit board and electronic device |
| CN107960009A (en) * | 2016-10-17 | 2018-04-24 | 南亚电路板股份有限公司 | Circuit board structure and manufacturing method thereof |
| CN114269065A (en) * | 2020-09-16 | 2022-04-01 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board with embedded conductive circuit and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1437244A (en) * | 2002-02-07 | 2003-08-20 | 矽统科技股份有限公司 | Method of improving surface flatness of embedded interlayer metal dielectric layer |
| CN101351087A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structure and technique thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0361195B1 (en) * | 1988-09-30 | 1993-03-17 | Siemens Aktiengesellschaft | Printed circuit board with moulded substrate |
| JP2008166736A (en) * | 2006-12-06 | 2008-07-17 | Hitachi Via Mechanics Ltd | Method for manufacturing printed-circuit board, and printed-circuit board finishing machine |
| KR20090036939A (en) * | 2007-10-10 | 2009-04-15 | 주식회사 하이닉스반도체 | Printed circuit board |
| CN101562944B (en) * | 2008-04-16 | 2011-06-29 | 欣兴电子股份有限公司 | Circuit board and manufacturing technology thereof |
-
2010
- 2010-01-15 CN CN201010004501.9A patent/CN102131346B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1437244A (en) * | 2002-02-07 | 2003-08-20 | 矽统科技股份有限公司 | Method of improving surface flatness of embedded interlayer metal dielectric layer |
| CN101351087A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structure and technique thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103052268A (en) * | 2011-10-11 | 2013-04-17 | 欣兴电子股份有限公司 | Method for making circuit structure |
| CN103052268B (en) * | 2011-10-11 | 2016-03-02 | 欣兴电子股份有限公司 | The manufacture method of line construction |
| CN103517576A (en) * | 2012-06-19 | 2014-01-15 | 深南电路有限公司 | Printed circuit board processing method, printed circuit board and electronic device |
| CN107960009A (en) * | 2016-10-17 | 2018-04-24 | 南亚电路板股份有限公司 | Circuit board structure and manufacturing method thereof |
| CN114269065A (en) * | 2020-09-16 | 2022-04-01 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board with embedded conductive circuit and manufacturing method thereof |
| CN114269065B (en) * | 2020-09-16 | 2023-08-04 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board with embedded conductive circuit and manufacturing method thereof |
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| CN102131346B (en) | 2014-08-06 |
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