CN114269065B - Circuit board with embedded conductive circuit and manufacturing method thereof - Google Patents
Circuit board with embedded conductive circuit and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a manufacturing method of a circuit board with embedded conductive circuits, which comprises the following steps: providing a circuit substrate, wherein the circuit substrate comprises a core layer and a first inner conductive circuit layer arranged on the core layer; forming a first insulating layer and a first copper foil layer on the first inner conductive circuit layer; a first opening is formed in the first copper foil layer; forming a second opening in the first insulating layer by plasma etching, wherein the second opening corresponds to the first opening to form a first opening area, and forming a first conductive layer at least in the first opening area; and removing the first copper foil layer and the first conductive layer above the first insulating layer, thereby obtaining the circuit board with the embedded conductive circuit. The impedance performance of the first conductive part manufactured by the method is good. The invention also provides a circuit board with the embedded conductive circuit manufactured by the manufacturing method.
Description
Technical Field
The invention relates to the technical field of circuit boards, in particular to a circuit board with embedded conductive circuits and a manufacturing method thereof.
Background
Currently, in the manufacture of circuit boards, it is often necessary to make openings in the circuit board, and then fill the openings with conductive material or plating to connect the circuit board to external electronic components. In making the openings, laser drilling is typically used.
However, the shape of the opening made by laser drilling is large at the top and small at the bottom, that is, the opening is approximately trapezoidal, and the shape of the opening is not easy to control, so that after the opening is filled with a conductive material or electroplated to form a conductive part, the shape of the conductive part is trapezoidal, which is not beneficial to controlling the impedance of the conductive part. At the same time, the heat generated during laser cutting also affects the shape of the openings. In addition, the cost of laser cutting is high.
Disclosure of Invention
In view of the above, the present invention provides a method for manufacturing a circuit board with embedded conductive traces, which can easily control the impedance of the conductive portion.
The invention also provides a circuit board with the embedded conductive circuit manufactured by the manufacturing method.
The preferred embodiment of the invention provides a manufacturing method of a circuit board with embedded conductive circuits, which comprises the following steps:
providing a circuit substrate, wherein the circuit substrate comprises a core layer and a first inner conductive circuit layer arranged on the core layer;
forming a first insulating layer and a first copper foil layer on the first inner conductive circuit layer;
a first opening is formed in the first copper foil layer, and the first insulating layer is exposed to the first opening;
forming a second opening in the first insulating layer through plasma etching, wherein the second opening corresponds to the first opening to form a first opening area, the second opening comprises a first side wall and a first bottom connected with the first side wall, and the first side wall is perpendicular to the first bottom;
etching in a region of the first copper foil layer except the first opening to form a first line slot;
a second circuit slot is formed in the first insulating layer, and the second circuit slot corresponds to the first circuit slot to form a first circuit slot area;
forming a first conductive layer at least in the first opening region and the first line slotting region; and
and removing the first copper foil layer and the first conductive layer positioned above the first insulating layer, wherein the first conductive layer positioned in the first circuit grooving region forms a first outer conductive circuit layer, the first conductive layer positioned in the first opening region forms a first conductive part, and the first outer conductive circuit layer is electrically connected with the first inner conductive circuit layer through the first conductive part, so that the circuit board with the embedded conductive circuit is obtained.
The preferred embodiment of the present invention also provides a circuit board with embedded conductive lines, comprising:
the circuit substrate comprises a core layer and a first inner conductive circuit layer arranged on the core layer;
the first insulating layer is arranged on the first inner conductive circuit layer, a first opening area and a first circuit grooving area are arranged in the first insulating layer, the first opening area comprises a first side wall and a first bottom connected with the first side wall, the first side wall is perpendicular to the first bottom, and a first conductive part is arranged in the first opening area; and
the first outer conductive circuit layer is positioned in the first circuit grooving area, and is electrically connected with the first inner conductive circuit layer through the first conductive part.
The shape of the second opening obtained by plasma etching is right angle, and compared with a trapezoid open pore obtained by laser cutting, the shape of the second opening is easier to control by the plasma etching, so that the impedance of the first conductive part is more beneficial to control. At the same time, the plasma etching generates less heat, thereby avoiding affecting the shape of the second opening. In addition, plasma etching is less costly than laser cutting, thereby reducing production costs.
Drawings
Fig. 1 is a schematic structural view of a core board according to a preferred embodiment of the present invention.
Fig. 2 is a schematic diagram of a structure in which the third copper foil layer and the fourth copper foil layer shown in fig. 1 are etched respectively.
Fig. 3 is a schematic view of the structure after forming a first insulating layer and a first copper foil layer on the first inner conductive trace layer shown in fig. 2, and forming a second insulating layer and a second copper foil layer on the second inner conductive trace layer.
Fig. 4 is a schematic structural diagram of the first copper foil layer and the second copper foil layer shown in fig. 3 after the first opening and the third opening are respectively opened.
Fig. 5 is a schematic structural diagram of the first insulating layer and the second insulating layer shown in fig. 4 after the second opening and the fourth opening are formed therein.
Fig. 6 is a schematic view of the structure after etching in the region of the first copper foil layer except the first opening and the region of the second copper foil layer except the third opening shown in fig. 5, respectively.
Fig. 7 is a schematic structural diagram of the first insulating layer and the second insulating layer shown in fig. 6 after the second circuit slot and the fourth circuit slot are formed therein.
Fig. 8 is a schematic structural view of the first opening region, the inner surface of the first circuit grooving region and the first copper foil layer shown in fig. 7 after forming a first surface treatment layer on the inner surface of the second opening region, the inner surface of the second circuit grooving region and the second copper foil layer.
Fig. 9 is a schematic structural view of the first surface treatment layer and the second surface treatment layer shown in fig. 8 after filling conductive materials respectively.
Fig. 10 is a schematic structural diagram of a circuit board with embedded conductive traces, which is obtained by removing the first copper foil layer and the first conductive layer above the first insulating layer, and removing the second copper foil layer and the second conductive layer above the second insulating layer, respectively, as shown in fig. 9.
Description of the main reference signs
Circuit board 100 with embedded conductive lines
Core board 10
Conductive post 11
Core layer 101
Third copper foil layer 102
Fourth copper foil layer 103
First inner conductive trace layer 104
Second inner conductive trace layer 105
Circuit board 20
First insulating layer 30
Second opening 301
First side wall 3011
First bottom 3012
Second line slot 302
First copper foil layer 31
First opening 311
First line slot 312
Second insulating layer 32
Fourth opening 321
Second side wall 3211
Second bottom 3212
Fourth line slot 322
Second copper foil layer 33
Third opening 331
Third line slot 332
First opening region 40
Second opening region 41
First line slotting region 42
Second line slotting region 43
First surface treatment layer 50
Second surface treatment layer 51
First conductive layer 60
Second conductive layer 61
First outer conductive trace layer 70
Second outer conductive trace layer 71
First conductive part 80
Second conductive part 81
The invention will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The invention will be described in detail below with reference to the drawings and preferred embodiments thereof, in order to further explain the technical means and effects of the invention to achieve the intended purpose.
The preferred embodiment of the invention provides a manufacturing method of a circuit board with embedded conductive circuits, which comprises the following steps:
in step S11, referring to fig. 1, a core board 10 is provided.
In this embodiment, the core board 10 includes a core layer 101, a third copper foil layer 102 and a fourth copper foil layer 103 respectively disposed on both side surfaces of the core layer 101.
The material of the core layer 101 may be one selected from prepregs (PP), epoxy resins (epoxy resins), polypropylene (polypropylene), BT resins, polyphenylene oxide (Polyphenylene Oxide, PPO), polyimide (PI), polyethylene terephthalate (Polyethylene Terephthalate, PET), and polyethylene naphthalate (Polyethylene Naphthalate, PEN). In this embodiment, the core layer 101 is made of PP.
In step S12, referring to fig. 2, a through hole (not shown) is formed in the core board 10.
Wherein the through hole penetrates through the third copper foil layer 102, the core layer 101 and the fourth copper foil layer 103 in sequence.
Step S13, electroplating in the through hole to form the conductive post 11.
Specifically, copper is electroplated in the through holes to form the conductive pillars 11. In other embodiments, a conductive paste may be filled in the via holes to form the conductive pillars 11.
In step S14, the third copper foil layer 102 and the fourth copper foil layer 103 are etched to form a first inner conductive circuit layer 104 and a second inner conductive circuit layer 105, respectively, so as to obtain the circuit substrate 20.
The first inner conductive circuit layer 104 and the second inner conductive circuit layer 105 are electrically connected through the conductive post 11.
It is understood that the number of circuit layers of the circuit substrate 20 is not limited to the above-described two-layer circuit, i.e., the number of circuit layers of the circuit substrate 20 may be changed as needed.
In step S15, referring to fig. 3, a first insulating layer 30 and a first copper foil layer 31 are sequentially laminated on the first inner conductive trace layer 104, and a second insulating layer 32 and a second copper foil layer 33 are sequentially laminated on the second inner conductive trace layer 105.
In the present embodiment, the material of the first insulating layer 30 and the second insulating layer 32 may be the same as that of the core layer 101, and will not be described in detail herein.
In step S16, referring to fig. 4, a first opening 311 and a third opening 331 are formed in the first copper foil layer 31 and the second copper foil layer 33, respectively.
Specifically, the first opening 311 and the third opening 331 may be formed by an etching method.
Wherein the first opening 311 penetrates through the first copper foil layer 31, and the third opening 331 penetrates through the second copper foil layer 33. I.e. the first insulating layer 30 is exposed to the first opening 311 and the second insulating layer 32 is exposed to the third opening 331. The first opening 311 and the third opening 331 correspond to the conductive pillar 11.
In step S17, referring to fig. 5, a second opening 301 and a fourth opening 321 are formed in the first insulating layer 30 and the second insulating layer 32 respectively by plasma etching.
The second opening 301 corresponds to the first opening 311 to form a first opening area 40, and the first inner conductive line layer 104 is exposed in the first opening area 40. The fourth opening 321 corresponds to the third opening 331 to form a second opening area 41, and the second inner conductive trace layer 105 is exposed in the second opening area 41.
The second opening 301 includes a first sidewall 3011 and a first bottom 3012 coupled to the first sidewall 3011. Wherein the first side wall 3011 is perpendicular to the first bottom 3012. The fourth opening 321 includes a second side wall 3211 and a second bottom 3212 connected to the second side wall 3211. Wherein the second side wall 3211 is perpendicular to the second bottom 3212. I.e. the second opening 301 and the fourth opening 321 are both right-angled.
In step S18, referring to fig. 6, a first circuit trench 312 and a third circuit trench 332 are respectively etched in the region of the first copper foil layer 31 except the first opening 311 and the region of the second copper foil layer 33 except the third opening 331.
Wherein the first insulating layer 30 is exposed to the first line slot 312 and the second insulating layer 32 is exposed to the third line slot 332.
In step S19, referring to fig. 7, a second circuit slot 302 and a fourth circuit slot 322 are formed in the first insulating layer 30 and the second insulating layer 32, respectively.
Specifically, the second line slot 302 and the fourth line slot 322 may be formed by a plasma etching method.
Wherein the second line slot 302 corresponds to the first line slot 312 to form a first line slot region 42 and the fourth line slot 322 corresponds to the third line slot 332 to form a second line slot region 43. The second line slot 302 does not extend through the first insulating layer 30, and the fourth line slot 322 does not extend through the second insulating layer 32.
In step S20, referring to fig. 8, a first surface treatment layer 50 is formed on the inner surface of the first opening area 40, the inner surface of the first line slotting area 42 and the first copper foil layer 31, and a second surface treatment layer 51 is formed on the inner surface of the second opening area 41, the inner surface of the second line slotting area 43 and the second copper foil layer 33.
The first surface treatment layer 50 and the second surface treatment layer 51 are used as seed layers for improving the bonding force between the conductive material formed later and the inner wall of the opening.
In the present embodiment, the first surface treatment layer 50 and the second surface treatment layer 51 are formed by sputtering. The materials of the first surface treatment layer 50 and the second surface treatment layer 51 may be conductive metals, such as nickel, gold, silver, etc.
In step S21, referring to fig. 9, a first conductive layer 60 and a second conductive layer 61 are formed on the first surface treated layer 50 and the second surface treated layer 51, respectively.
Specifically, the first conductive layer 60 and the second conductive layer 61 may be formed by electroplating copper or filling a conductive material.
Wherein the first conductive layer 60 over the first opening region 40 and the first line slotting region 42 is flush with the first conductive layer 60 on the first copper foil layer 31. The second conductive layer 61 over the second open area 41 and the second wire-grooved area 43 is flush with the second conductive layer 61 on the second copper foil layer 33.
In this embodiment, the conductive material may be a conductive paste. In other embodiments, the conductive material may also be a conductive metal, such as copper metal, and the like.
In step S22, referring to fig. 10, the first copper foil layer 31 and the first conductive layer 60 above the first insulating layer 30 are removed, and the second copper foil layer 33 and the second conductive layer 61 above the second insulating layer 32 are removed, so as to obtain the circuit board 100 with embedded conductive traces.
Wherein the first conductive layer 60 located in the first line slotting region 42 and the second conductive layer 61 located in the second line slotting region 43 form a first outer conductive line layer 70 and a second outer conductive line layer 71, respectively, and the first conductive layer 60 located in the first opening region 40 and the second conductive layer 61 located in the second opening region 41 form a first conductive portion 80 and a second conductive portion 81, respectively. The side and bottom surfaces of the first outer conductive trace layer 70 are embedded in the first insulating layer 30, and the side and bottom surfaces of the second outer conductive trace layer 71 are embedded in the second insulating layer 32. The first outer conductive trace layer 70 is electrically connected to the first inner conductive trace layer 104 through the first conductive portion 80, and the second outer conductive trace layer 71 is electrically connected to the second inner conductive trace layer 105 through the second conductive portion 81.
In this embodiment, the removal may be performed by chemical etching.
Referring to fig. 10, the present invention further provides a circuit board 100 with embedded conductive traces, wherein the circuit board 100 with embedded conductive traces includes a circuit substrate 20, a first insulating layer 30, a first outer conductive trace layer 70, a second insulating layer 32 and a second outer conductive trace layer 71.
In this embodiment, the circuit substrate 20 includes a core layer 101, and a first inner conductive circuit layer 104 and a second inner conductive circuit layer 105 respectively disposed on two side surfaces of the core layer 101.
The material of the core layer 101 may be one selected from prepregs (PP), epoxy resins (epoxy resins), polypropylene (polypropylene), BT resins, polyphenylene oxide (Polyphenylene Oxide, PPO), polyimide (PI), polyethylene terephthalate (Polyethylene Terephthalate, PET), and polyethylene naphthalate (Polyethylene Naphthalate, PEN). In this embodiment, the core layer 101 is made of PP.
The circuit substrate 20 is provided with a conductive post 11, and the first inner conductive circuit layer 104 and the second inner conductive circuit layer 105 are electrically connected through the conductive post 11.
It is understood that the number of circuit layers of the circuit substrate 20 is not limited to the above-described two-layer circuit, i.e., the number of circuit layers of the circuit substrate 20 may be changed as needed.
In this embodiment, the first insulating layer 30 is disposed on the first inner conductive trace layer 104. The first insulating layer 30 has a first opening region 40 and a first line trench region 42. The first opening area 40 includes a first sidewall 3011 and a first bottom 3012 connected to the first sidewall 3011, and the first sidewall 3011 is perpendicular to the first bottom 3012. I.e. the shape of the first open area 40 is a right angle. The first opening area 40 is provided therein with a first conductive portion 80. The material of the first conductive portion 80 may be conductive paste or copper.
The first outer conductive trace layer 70 is located in the first trace recessed area 42. The first outer conductive trace layer 70 is electrically connected to the first inner conductive trace layer 104 through the first conductive portion 80. The side and bottom surfaces of the first outer conductive trace layer 70 are buried in the first insulating layer 30.
In this embodiment, the second insulating layer 32 is disposed on the second inner conductive trace layer 105. The second insulating layer 32 has a second opening region 41 and a second line slot region 43. The second opening area 41 includes a second sidewall 3211 and a second bottom 3212 connected to the second sidewall 3211, and the second sidewall 3211 is perpendicular to the second bottom 3212. I.e. the shape of said second opening area 41 is right angle. The second opening area 41 is provided with a second conductive portion 81. The material of the second conductive portion 81 may be conductive paste or copper.
The second outer conductive trace layer 71 is located in the second trace trench region 43. The second outer conductive trace layer 71 is electrically connected to the second inner conductive trace layer 105 through the second conductive portion 81. The second outer conductive trace layer 71 is buried in the second insulating layer 32 on both sides and bottom.
In the present invention, the shapes of the second opening 301 and the fourth opening 321 obtained by plasma etching are right angles, and compared with a trapezoid opening obtained by laser cutting, the shapes of the second opening 301 and the fourth opening 321 are easier to control by plasma etching, so that the impedance of the first conductive portion 80 and the second conductive portion 81 is more beneficial to control. Meanwhile, when the first opening 311 and the second opening 301 are formed by plasma etching, the first opening 311 and the second opening 301 may be manufactured by one step, thereby simplifying the process and improving the production efficiency.
In addition, the plasma etching in the present invention generates less heat, thereby avoiding affecting the shapes of the second opening 301 and the fourth opening 321. Meanwhile, the plasma etching cost is lower, so that the production cost is reduced.
The above description is only one preferred embodiment of the present invention, but is not limited to this embodiment during actual application. Other modifications and variations to the present invention will be apparent to those of ordinary skill in the art in light of the present teachings.
Claims (8)
1. The manufacturing method of the circuit board with the embedded conductive circuit is characterized by comprising the following steps of:
providing a circuit substrate, wherein the circuit substrate comprises a core layer, a first inner-layer conductive circuit layer and a second inner-layer conductive circuit layer, the second inner-layer conductive circuit layer and the first inner-layer conductive circuit layer are respectively arranged on two sides of the core layer, and the second inner-layer conductive circuit layer is electrically connected with the first inner-layer conductive circuit layer;
forming a first insulating layer and a first copper foil layer on the first inner conductive circuit layer, and forming a second insulating layer and a second copper foil layer on the second inner conductive circuit layer;
a first opening is formed in the first copper foil layer, the first insulating layer is exposed to the first opening, a third opening is formed in the second copper foil layer, and the second insulating layer is exposed to the third opening;
forming a second opening in the first insulating layer through plasma etching, wherein the second opening corresponds to the first opening to form a first opening area, the second opening comprises a first side wall and a first bottom connected with the first side wall, and the first side wall is perpendicular to the first bottom;
forming a fourth opening in the second insulating layer through plasma etching, wherein the fourth opening corresponds to the third opening to form a second opening area, the fourth opening comprises a second side wall and a second bottom connected with the second side wall, and the second side wall is perpendicular to the second bottom;
etching in a region of the first copper foil layer except the first opening to form a first line slot, and etching in a region of the second copper foil layer except the third opening to form a third line slot;
a second circuit slot is formed in the first insulating layer, and the second circuit slot corresponds to the first circuit slot to form a first circuit slot area;
a fourth line slotting is formed in the second insulating layer, and the fourth line slotting corresponds to the third line slotting to form a second line slotting region;
forming a first conductive layer in at least the first opening region and the first line slotting region, and forming a second conductive layer in at least the second opening region and the second line slotting region; and
removing the first copper foil layer, the first conductive layer positioned above the first insulating layer, the second copper foil layer and the second conductive layer positioned above the second insulating layer, wherein the first conductive layer positioned in the first line slotting region forms a first outer conductive line layer, the second conductive layer positioned in the second line slotting region forms a second outer conductive line layer, the first conductive layer positioned in the first opening region forms a first conductive part, the second conductive layer positioned in the second opening region forms a second conductive part, the first outer conductive line layer is electrically connected with the first inner conductive line layer through the first conductive part, and the second outer conductive line layer is electrically connected with the second inner conductive line layer through the second conductive part, so that the circuit board with the embedded conductive line is obtained.
2. The method for manufacturing a circuit board with embedded conductive lines as claimed in claim 1, further comprising:
forming a first surface treatment layer on at least an inner surface of the first opening region and the first line slotting region;
wherein the first conductive layer is formed on the first surface treatment layer.
3. The method for manufacturing a circuit board with embedded conductive lines as claimed in claim 1, wherein the forming of the first conductive layer comprises:
and filling conductive materials or electroplating in the first opening area and the first line slotting area.
4. The method of manufacturing a circuit board with embedded conductive traces of claim 3, wherein the conductive material is conductive paste or copper.
5. The method for manufacturing a circuit board with embedded conductive traces of claim 4, further comprising:
forming a second surface treatment layer on at least the inner surface of the second opening region and the second line slotting region;
wherein the second conductive layer is formed on the second surface treatment layer.
6. The method of manufacturing a circuit board with embedded conductive traces according to claim 1, wherein the first openings are formed by plasma etching.
7. A wiring board with embedded conductive lines, wherein the wiring board is manufactured by any one of the manufacturing methods of claims 1 to 6, comprising:
the circuit substrate comprises a core layer, a first inner-layer conductive circuit layer and a second inner-layer conductive circuit layer, wherein the second inner-layer conductive circuit layer and the first inner-layer conductive circuit layer are respectively arranged on two sides of the core layer, and the second inner-layer conductive circuit layer is electrically connected with the first inner-layer conductive circuit layer;
the first insulating layer is arranged on the first inner conductive circuit layer, a first opening area and a first circuit grooving area are arranged in the first insulating layer, the first opening area comprises a first side wall and a first bottom connected with the first side wall, the first side wall is perpendicular to the first bottom, and a first conductive part is arranged in the first opening area;
the second insulating layer is arranged on the second inner conductive circuit layer, a second opening area and a second circuit grooving area are arranged in the second insulating layer, the second opening area comprises a second side wall and a second bottom connected with the second side wall, the second side wall is perpendicular to the second bottom, and a second conductive part is arranged in the second opening area; and
the first outer conductive circuit layer is positioned in the first circuit grooving area and is electrically connected with the first inner conductive circuit layer through the first conductive part;
the second outer conductive circuit layer is positioned in the second circuit grooving area, and is electrically connected with the second inner conductive circuit layer through the second conductive part.
8. The circuit board of claim 7, wherein the first conductive portion is made of conductive paste or copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010973756.XA CN114269065B (en) | 2020-09-16 | 2020-09-16 | Circuit board with embedded conductive circuit and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010973756.XA CN114269065B (en) | 2020-09-16 | 2020-09-16 | Circuit board with embedded conductive circuit and manufacturing method thereof |
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| CN114269065A CN114269065A (en) | 2022-04-01 |
| CN114269065B true CN114269065B (en) | 2023-08-04 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1387239A (en) * | 2001-05-21 | 2002-12-25 | 新光电气工业株式会社 | Circuit board, semiconductor device mfg. method, and electroplating system |
| CN102123566A (en) * | 2010-01-12 | 2011-07-13 | 欣兴电子股份有限公司 | Embedded circuit board and manufacturing method thereof |
| CN102131346A (en) * | 2010-01-15 | 2011-07-20 | 欣兴电子股份有限公司 | Circuit board and manufacturing process thereof |
| CN103052268A (en) * | 2011-10-11 | 2013-04-17 | 欣兴电子股份有限公司 | Method for making circuit structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103179806B (en) * | 2011-12-21 | 2019-05-28 | 奥特斯有限公司 | The method of combined through-hole plating and hole filling |
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2020
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1387239A (en) * | 2001-05-21 | 2002-12-25 | 新光电气工业株式会社 | Circuit board, semiconductor device mfg. method, and electroplating system |
| CN102123566A (en) * | 2010-01-12 | 2011-07-13 | 欣兴电子股份有限公司 | Embedded circuit board and manufacturing method thereof |
| CN102131346A (en) * | 2010-01-15 | 2011-07-20 | 欣兴电子股份有限公司 | Circuit board and manufacturing process thereof |
| CN103052268A (en) * | 2011-10-11 | 2013-04-17 | 欣兴电子股份有限公司 | Method for making circuit structure |
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