CN103050592A - LED (Light Emitting Diode) epitaxial structure with P (Positive) type superlattice and preparation method thereof - Google Patents
LED (Light Emitting Diode) epitaxial structure with P (Positive) type superlattice and preparation method thereof Download PDFInfo
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Abstract
The invention discloses an LED (Light Emitting Diode) epitaxial structure with a P (Positive) type superlattice and a preparation method thereof. The epitaxial structure comprises a substrate, wherein a GaN (Gallium Nitride) buffer layer, an undoped GaN layer, an n (negative) type GaN layer, a multi-quantum well luminous layer, a first P type GaN layer, a P type AlGaN (Aluminium Gallium Nitride) electronic blocking layer and a second P type GaN layer are sequentially arranged on the substrate from bottom to top, and the P type superlattice formed by a PInGaN (P type Indium Gallium Nitride) potential well layer and a PAlGaN potential barrier layer in a periodic interactive overlapping way is arranged between the P type AlGaN electronic blocking layer and the second P type GaN layer. The PInGaN potential well layer in the P type superlattice generates and constrains a great number of holes for the formation of a two-dimensional hole high-density state; the PAlGaN potential barrier layer hinders the escape of the holes; in such a way, the transverse spreading of the holes is improved, the electron overflow can be prevented, the hole injection efficiency is increased and the electron and hole recombination probability is improved; and therefore, the brightness of a chip can be improved by 5-10%.
Description
Technical field
The present invention relates to technical field of semiconductors, especially, relate to LED epitaxial structure of a kind of P of having type superlattice and preparation method thereof.
Background technology
GaN is because its good characteristic has become the important materials of making luminescent device, high temperature high power device and ultraviolet detector.It is to make the requisite important step of GaN device that the P type mixes, and has therefore attracted the attention of a lot of research groups.Because the passivation (passivation) of Mg, undressed GaN:Mg resistivity must activate (Activation) to Mg up to 10Qcm after growth, to obtain being applied to the P type GaN of device.H.Amano had obtained the important breakthrough of P type in 1989, and he utilizes low-energy electron beam radiation (IEEBI) to process the GaN that mixes Mg, has obtained the P type GaN of low-resistance.1991, S.Nakamura etc. invented rapid thermal annealing method (Rapid Thermal Annealing), had successfully obtained the GaN of P type, had greatly accelerated with the process of blue green light LED so that Design and manufacture is commercial.
During with MOCVD technology growth p-type GaN, by the serious passivation of H, the method with thermal annealing under N2 atmosphere can obtain the uniform p-type GaN of hole concentration to acceptor Mg atom in growth course.In order to obtain well behaved P type GaN material, people have studied the impact of the high temperature anneal on GaN electric property, the characteristics of luminescence, and the passivation effect, acceptor activation mechanism etc. of Mg2H complex among the p-type GaN.Although changed into the p-type sample through the sample after the suitable annealing in process, the hole concentration that obtains is still lower, representative value is 2 * 10
17Cm
-3, than low 2～3 orders of magnitude of doping content.
Therefore, the hole concentration that how to improve the P layer becomes the key of P type GaN growth, and traditional comprises common P layer LED epitaxial structure as shown in Figure 1, and its preparation method is: at high temperature, and H
2Atmosphere is processed substrate 1 and is continued 5～6min; Regrowth GaN resilient coating 2; Regrowth is Doped GaN layer 3(U-GaN not); Regrowth N-shaped GaN layer (Si doping type N-GaN); Regrowth multiple quantum well light emitting layer 5; Regrowth the one P type GaN layer 6(LTP, low temperature P type GaN); Secondly growing P-type AlGaN electronic barrier layer 7(is called for short PAlGaN), the 2nd P type GaN layer 8(HTP that grow at last, high temperature P type GaN).Wherein, HTP thickness 140-150nm, PAlGaN thickness 50～60nm, LTP thickness 50～60nm, the HTP hole concentration is high, PAlGaN, the LTP hole concentration is on the low side, and the hole is injected into the multiple quantum well light emitting layer through HTP, PAlGaN, LTP.According to the electronic theory of PN junction, hole migration is actual to be the propagation of electric field, the height of the hole concentration of HTP, PAlGaN, LTP will determine the efficiency of hole injection multiple quantum well light emitting layer 5, traditional PAlGaN, the thinner thickness of LTP, and nearest apart from quantum well, thereby so that the hole concentration of traditional PAlGaN, LTP is not high and then to be injected into the efficient of multiple quantum well light emitting layer low in the hole, thereby reduced the luminosity of the led chip of unit are.
Summary of the invention
The object of the invention is to provide a kind of can fetter the hole, pass through to improve hole concentration, and then the LED epitaxial structure with P type superlattice of the brightness of raising chip and preparation method thereof, not high with the hole concentration that solves traditional PAlGaN, LTP, hole injection efficiency is low, the technical problem that the luminosity of led chip is low.
For achieving the above object, the invention provides a kind of LED epitaxial structure of the P of having type superlattice, comprise substrate, be disposed with from the bottom to top GaN resilient coating, not Doped GaN layer, N-shaped GaN layer, multiple quantum well light emitting layer, a P type GaN layer, P type AlGaN electronic barrier layer, the 2nd P type GaN layer on the described substrate
Be provided with the P type superlattice that consisted of by PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing between described P type AlGaN electronic barrier layer and described the 2nd P type GaN layer.
Further improvement as epitaxial structure of the present invention:
Preferably, described P type superlattice are made of PInGaN potential well layer and the PAlGaN barrier layer intermeshing in 2～4 cycles; And the described PInGaN potential well layer of described period 1 is overlying on the described PAlGaN electronic barrier layer.
Preferably, the thickness of described P type superlattice is 12nm～40nm;
Preferably, in the described P type superlattice, the thickness of the described PInGaN potential well layer in single cycle is 3nm～5nm; The thickness of the described PAlGaN barrier layer in single cycle is 3nm～5nm.
Preferably, the thickness of described GaN resilient coating is 20nm～30nm;
The thickness of described not Doped GaN layer is 2 μ m～2.5 μ m;
The thickness of described N-shaped GaN layer is 2 μ m～2.5 μ m;
The thickness of described multiple quantum well light emitting layer is 200nm～260nm;
The thickness of a described P type GaN layer is 50nm～60nm;
The thickness of described P type InAlGaN electronic barrier layer is 30nm～40nm;
The thickness of described P type GaN layer is 200nm～250nm.
Preferably, described multiple quantum well light emitting layer is made of InGaN potential well layer and the mutual stack of GaN barrier layer in 15～16 cycles;
In the described multiple quantum well light emitting layer: the thickness of the described InGaN potential well layer in single cycle is 2.5nm～3nm; The thickness of the described GaN barrier layer in single cycle is 12nm～13nm.
Preferably, the P type GaN layer of a described P type GaN layer under 800 ℃～850 ℃ temperature conditions, generating; The P type GaN layer of described the 2nd P type GaN layer under 1050 ℃～1100 ℃ temperature conditions, generating.
As a total technical conceive, the present invention also provides a kind of preparation method of LED epitaxial structure of the P of having type superlattice, it is characterized in that, may further comprise the steps:
S1: select substrate;
S2: take TMGa as the Ga source, take TMAl as the Al source, take TMIn as the In source, with NH
3Be the N source, on described substrate, carry out successively following steps:
S201: growing GaN resilient coating;
S202: the not Doped GaN layer of growing;
S203: growing n-type GaN layer;
S204: growth multiple quantum well light emitting layer;
S205: the P type GaN layer of growing;
S206: growing P-type AlGaN electronic barrier layer;
Among the described step S2, finish described S206 after, described method is further comprising the steps of:
S207: the P type superlattice that growth is made of PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing;
S208: the 2nd P type GaN layer of growing.
As further improvements in methods of the present invention:
Preferably, described step S207 may further comprise the steps:
Carry out the following operation in 2～4 cycles:
S2071: growth thickness is the PInGaN potential well layer of 3nm～5nm;
S2072: growth thickness is the PAlGaN barrier layer of 3nm～5nm.
Preferably, described step S204 may further comprise the steps:
Carry out the following operation in 13～15 cycles:
S2041: growth thickness is the InGaN potential well layer of 2.5nm～3nm;
S2042: growth thickness is the GaN barrier layer of 12nm～13nm.
Preferably, the technological parameter of described each step of preparation method is as follows:
Among the described step S201, be that the flow of described TMGa is 55mL/min～75mL/min, described NH under 530 ℃～570 ℃ conditions in temperature
3Flow be 1.1 * 10
4ML/min～1.3 * 10
4Growth thickness is the GaN resilient coating of 20nm～30nm under the process conditions of mL/min; Then be warming up to 1030 ℃～1100 ℃, and keep 180s～210s, make described GaN resilient coating recrystallization;
Among the described step S202, temperature is 1000 ℃～1250 ℃, and the flow of described TMGa is 180mL/min～210mL/min, described NH
3Flow be 2.1 * 10
4ML/min～2.4 * 10
4ML/min; Growth thickness is 2 μ m～2.5 μ m;
Among the described step S203, temperature is 1000 ℃～1250 ℃, and the flow of described TMGa is 200mL/min～250mL/min, described NH
3Flow be 2.5 * 10
4ML/min～3 * 10
4ML/min, described SiH
4Flow be 14mL/min～18mL/min; Growth thickness is 2 μ m～2.5 μ m;
Among the described step S2041, temperature is 730 ℃～800 ℃, and the flow of described TMGa is 10mL/min～15mL/min, and the flow of described TMIn is 650mL/min～750mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min;
Among the described step S2042, temperature is 730 ℃～800 ℃, and the flow of described TMGa is 10mL/min～15mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min;
Among the described step S205, temperature is 800 ℃～850 ℃, and the flow of described TMGa is 40mL/min～60mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min; Described Cp
2The flow of Mg is 600mL/min～700mL/min; Growth thickness is 50nm～60nm;
Among the described step S206, temperature is 900 ℃～950 ℃, and chamber pressure is 150mbar～250mbar, and the flow of described TMGa is 30mL/min～45mL/min, and the flow of described TMAl is 50mL/min～80mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min; Described Cp
2The flow of Mg is 700mL/min～800mL/min; Growth thickness is 30nm～40nm;
Among the described step S2071, temperature is 900 ℃～950 ℃, and chamber pressure is 150mbar～250mbar, and the flow of described TMGa is 30mL/min～45mL/min, and the flow of described TMIn is 300mL/min～450mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min, described Cp
2The flow of Mg is 700mL/min～800mL/min;
Among the described step S2072, temperature is 900 ℃～950 ℃, and chamber pressure is 150mbar～250mbar, and the flow of described TMGa is 30mL/min～45mL/min, and the flow of described TMAl is 60mL/min～80mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min, described Cp
2The flow of Mg is 700mL/min～800mL/min;
Among the described step S8, temperature is 1050 ℃～1100 ℃, and the flow of described TMGa is 55mL/min～70mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min, described Cp
2The flow of Mg is 400mL/min～750mL/min, and growth thickness is 200nm～250nm.
The present invention has following beneficial effect:
1, the LED epitaxial structure with P type superlattice of the present invention arranges the P type superlattice that are made of PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing between P type AlGaN electronic barrier layer and the 2nd P type GaN layer.PInGaN potential well layer in the P type superlattice will produce and fetter a large amount of holes, form the Two-Dimensional Hole high-density state; The PAlGaN barrier layer will hinder the escape in hole, improve the extending transversely of hole, and will be can block electrons excessive, increase hole injection efficiency, improve electronics and hole-recombination probability, and then improve the brightness of chip.
2, the preparation method with LED epitaxial structure of P type superlattice of the present invention, simple, the P type superlattice by between P type AlGaN electronic barrier layer and the 2nd P type GaN layer, growing and being consisted of by PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing of processing step.Can prepare the LED epitaxial structure of the P of having type superlattice of the present invention, and be suitable for suitability for industrialized production.
Except purpose described above, feature and advantage, the present invention also has other purpose, feature and advantage.The below is with reference to figure, and the present invention is further detailed explanation.
Description of drawings
The accompanying drawing that consists of the application's a part is used to provide a further understanding of the present invention, and illustrative examples of the present invention and explanation thereof are used for explaining the present invention, do not consist of improper restriction of the present invention.In the accompanying drawings:
Fig. 1 is traditional cross-sectional view that comprises common P layer LED epitaxial structure;
Fig. 2 is the cross-sectional view of the LED epitaxial structure with P type superlattice of the preferred embodiment of the present invention 1;
Fig. 3 is that the LED epitaxial structure with P type superlattice of the preferred embodiment of the present invention 1 and traditional being with of common P layer LED epitaxial structure that comprise contrast schematic diagram; Wherein, Fig. 3 (1) can be with for the LED epitaxial structure with P type superlattice of invention preferred embodiment 1; Fig. 3 (2) comprises being with of common P layer LED epitaxial structure for traditional.
Fig. 4 is the distribution contrast schematic diagram of hole concentration of P layer of the LED epitaxial structure of the LED epitaxial structure of the preferred embodiment of the present invention 1 and Comparative Examples 1; Wherein, " ■ " is the distribution schematic diagram of hole concentration of P layer of the LED epitaxial structure of traditional Comparative Examples 1; " ▲ " is the distribution schematic diagram of hole concentration of P layer of the LED epitaxial structure of the preferred embodiment of the present invention 1.
Fig. 5 is the brightness contrast schematic diagram that the epitaxial wafer of the epitaxial wafer of the preferred embodiment of the present invention 1 and Comparative Examples 1 is prepared into respectively the led chip of 10mil*23mil size; Wherein, " ▲ " is prepared into the brightness schematic diagram of the led chip of 10mil*23mil size for the epitaxial wafer of Comparative Examples 1; "-" is prepared into the brightness schematic diagram of the led chip of 10mil*23mil size for the epitaxial wafer of the preferred embodiment of the present invention 1;
Fig. 6 is the brightness contrast schematic diagram that the epitaxial wafer of the epitaxial wafer of the preferred embodiment of the present invention 1 and Comparative Examples 1 is prepared into respectively the led chip of 45mil*45mil size; Wherein, " ◆ " is prepared into the brightness schematic diagram of the led chip of 45mil*45mil size for the epitaxial wafer of Comparative Examples 1; "-" is prepared into the brightness schematic diagram of the led chip of 45mil*45mil size for the epitaxial wafer of the preferred embodiment of the present invention 1;
Fig. 7 is the brightness contrast schematic diagram that the epitaxial wafer of the epitaxial wafer of the preferred embodiment of the present invention 2 and Comparative Examples 2 is prepared into respectively the led chip of 10mil*23mil size; Wherein, " ▲ " is prepared into the brightness schematic diagram of the led chip of 10mil*23mil size for the epitaxial wafer of Comparative Examples 2; "-" is prepared into the brightness schematic diagram of the led chip of 10mil*23mil size for the epitaxial wafer of the preferred embodiment of the present invention 2; And
Fig. 8 is the brightness contrast schematic diagram that the epitaxial wafer of the epitaxial wafer of the preferred embodiment of the present invention 2 and Comparative Examples 2 is prepared into respectively the led chip of 45mil*45mil size; Wherein,
Be prepared into the brightness schematic diagram of the led chip of 45mil*45mil size for the epitaxial wafer of Comparative Examples 2;
Be prepared into the brightness schematic diagram of the led chip of 45mil*45mil size for the epitaxial wafer of the preferred embodiment of the present invention 1.
Marginal data:
1, substrate; 2, GaN resilient coating; 3, Doped GaN layer not; 4, N-shaped GaN layer; 5, multiple quantum well light emitting layer; 6, a P type GaN layer; 7, P type AlGaN electronic barrier layer; 8, the 2nd P type GaN layer; 9, P type superlattice; 91, PInGaN potential well layer; 92, PAlGaN barrier layer.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are elaborated, but the multitude of different ways that the present invention can be defined by the claims and cover is implemented.
The invention provides a kind of LED epitaxial structure of the P of having type superlattice, by at P type AlGaN electronic barrier layer 7 and the 2nd P type GaN layer 8(HTP) between periodically P type superlattice 9 structures that consist of of intermeshings of PInGaN potential well layer 91 and PAlGaN barrier layer 92 are set, PInGaN potential well layer 91 in the P type superlattice 9 will produce and fetter a large amount of holes, form the Two-Dimensional Hole high-density state; PAlGaN barrier layer 92 will hinder the escape in hole, improve the extending transversely of hole, and will be can block electrons excessive, increase hole injection efficiency, improve electronics and hole-recombination probability, and then reach the purpose of the brightness that improves chip.
Potential well refers to potential energy than near potential energy low area of space all in the literary composition, and potential barrier refers to that potential energy is than near potential energy high area of space all.Be converted to quantum level between the potential well in the superlattice herein and potential barrier.As shown in Figure 3, be converted to vertical transition between potential well and potential barrier.
As shown in Figure 2, LED epitaxial structure with P type superlattice of the present invention, comprise substrate 1, be disposed with from the bottom to top on the substrate 1 GaN resilient coating 2, not Doped GaN layer 3, N-shaped GaN layer 4, multiple quantum well light emitting layer 5, a P type GaN layer 6, P type AlGaN electronic barrier layer 7, by PInGaN potential well layer 91 and the PAlGaN barrier layer 92 P type superlattice 9, the 2nd P type GaN layer 8 that consist of of intermeshings periodically.During practical application, P type superlattice 9 are made of PInGaN potential well layer 91 and PAlGaN barrier layer 92 intermeshings in 2～4 cycles, and effect is better.The period 1 PInGaN potential well layer 91 of (from the bottom to top for suitable several) is overlying on the PAlGaN electronic barrier layer, and namely P type superlattice are that PInGaN potential well layer 91 is descending in 9 single cycles, and PAlGaN barrier layer 92 is in upper structure.Preferably, the P type GaN layer (LTP, low temperature P type GaN) of a P type GaN layer 6 under 800 ℃～850 ℃ temperature conditions, generating, the P type GaN layer (HTP, high temperature P type GaN) of the 2nd P type GaN layer 8 under 1050 ℃～1100 ℃ temperature conditions, generating.
PInGaN is can bandwidth narrower, and PAlGaN can broader bandwidth, because the difference that can be with, PInGaN and PAlGaN structure will produce quantum well structure, and it is more intense to the control ability in hole that thickness preferably is controlled at 3-5nm, to the binding energy force rate of electronics a little less than.In conjunction with among Fig. 3 shown in (2), narrow can be with the more close Mg of valence band of PInGaN, the activation energy that Mg needs is lower, the easier hole that discharges of the Mg of identical doping content, have the quantum well structure of depth stop to possess the ability of bound hole, opposite wide PAlGaN that can band is unfavorable for the activation of Mg, and it is few that the Mg of identical doping content discharges number of cavities, resistance is higher, and hole mobility is low.PInGaN trap layer hole concentration is high, and mobility is higher, and horizontal and vertical conduction is strengthened, because the PInGaN trap layer longitudinally horizontal width of Width is little a lot, longitudinally conduction is strengthened becoming not obvious, mainly is that ability extending transversely is strengthened, can the homogenizing conduction current on the macroscopic view.The opposite wide PAlGaN that can be with will be unfavorable for the conduction in hole, hinder the escape in PInGaN trap layer hole, and in conjunction with (2) among Fig. 3, the PAlGaN of high conduction band will stop the electronics of N Es-region propagations, prevent that electronics is excessive to the P layer; Escape, block electrons extending transversely, that hinder the hole that the effect that this structure plays is summed up as bound hole, improve the hole are excessive; Need to replenish to be that traditional LED epitaxial structure only comprises block electrons excessive, and be the PAlGaN component, hole concentration low (detailed in Fig. 4) injection efficiency is poor.Structure of the present invention addresses this problem emphatically, the electron concentration that is presented as luminescent layer on the macroscopic view remains unchanged, and hole concentration is because of the reinforcement of injecting and the increase of quantity, and the electronics of luminescent layer and the combined efficiency in hole improve, improve the chip internal quantum efficiency, thereby the brightness of LED gets a promotion.
During practical application, the thickness of each layer of LED epitaxial structure is rationally arranged, also will affect the effect that electronic blocking in the LED epitaxial structure and hole are injected.When the thickness of each layer preferably was arranged in the following scope, effect is better: the thickness of GaN resilient coating 2 was 20nm～30nm; The thickness of Doped GaN layer 3 is not 2 μ m～2.5 μ m; The thickness of N-shaped GaN layer 4 is 2 μ m～2.5 μ m; The thickness of multiple quantum well light emitting layer 5 is 200nm～260nm, and preferably, multiple quantum well light emitting layer 5 is made of InGaN potential well layer and the mutual stack of GaN barrier layer in 15～16 cycles; In the multiple quantum well light emitting layer 5: the thickness of the InGaN potential well layer in single cycle is 2.5nm～3nm; The thickness of the GaN barrier layer in single cycle is 12nm～13nm.The thickness of the one P type GaN layer 6 is 50nm～60nm; The thickness of P type GaN layer is 200nm～250nm.More importantly, the thickness of P type InAlGaN electronic barrier layer is set to 30nm～40nm; The thickness of P type superlattice 9 is 12nm～40nm.In the P type superlattice 9, the thickness of the PInGaN potential well layer 91 in single cycle is 3nm～5nm; The thickness of the PAlGaN barrier layer 92 in single cycle is 3nm～5nm.P type InAlGaN electronic blocking is placed on the lower floor of superlattice, can stop the electronics of being come by the N layer under it, then, superlattice thereon layer solve hole injection problem, so both can prevent that electronics from leaking, and can keep the effect of conventional P type InAlGaN block electrons, can improve hole concentration again, and then the raising hole injection efficiency, improve electronics and hole-recombination probability, and then improve the brightness of chip.
The present invention also provides a kind of preparation method of LED epitaxial structure of the P of having type superlattice, by the P type superlattice 9 that PInGaN potential well layer 91 and PAlGaN barrier layer 92 periodicity intermeshings consist of, can make the LED epitaxial structure of the P of having type superlattice of the present invention by growth between P type AlGaN electronic barrier layer 7 and the 2nd P type GaN layer 8.
Below by specific embodiment, this preparation method of analytic explanation.
Used trimethyl gallium (TMGa), trimethyl aluminium (TMAl), trimethyl indium (TMIn), two luxuriant U.S. (Cp in following examples
2Mg), silane (SiH
4), ammonia (NH3) and unclassified stores be common commercially available.Used Preparation equipment is MOCVD equipment in following examples, also be common commercially available equipment, and use MOCVD equipment only for needing for example in following examples, and the used equipment of non-limiting preparation method of the present invention, other can all be applicable to preparation method of the present invention for the preparation of the equipment of each semiconductor layer of the method.
The preparation method of the LED epitaxial structure of following examples may further comprise the steps:
S1: when selecting Sapphire Substrate 1(practical application, also can select SiC substrate or Si substrate); Sapphire Substrate 1 is placed H
2Under the atmosphere, be heated to 1100 ℃ and keep 400s, to remove the H on substrate 1 surface
2O and O
2Cool to again 500 ℃, and pass into NH
3Substrate 1 is carried out the nitrogen treatment of 200s.
S2: take TMGa as the Ga source, take TMAl as the Al source, take TMIn as the In source, with NH
3Be the N source, on substrate 1, carry out successively following steps:
S201: be that the flow of TMGa is 55mL/min～75mL/min, NH under 530 ℃～570 ℃ conditions in temperature
3Flow be 1.1 * 10
4ML/min～1.3 * 10
4Growth thickness is the GaN resilient coating 2 of 20nm～30nm under the process conditions of mL/min; Then be warming up to 1030 ℃～1100 ℃, and keep 180s～210s, make GaN resilient coating 2 recrystallizations.
S202: temperature is 1000 ℃～1250 ℃, and the flow of TMGa is 180mL/min～210mL/min, NH
3Flow be 2.1 * 10
4ML/min～2.4 * 10
4ML/min; Growth thickness is the not Doped GaN layer 3 of 2 μ m～2.5 μ m.
S203: temperature is 1000 ℃～1250 ℃, and the flow of TMGa is 200mL/min～250mL/min, NH
3Flow be 2.5 * 10
4ML/min～3 * 10
4ML/min, SiH
4Flow be 14mL/min～18mL/min; Growth thickness is the N-shaped GaN layer 4 of 2 μ m～2.5 μ m.
S204: growth multiple quantum well light emitting layer 5, preferred step is:
Carry out the following operation in 13～15 cycles:
S2041: temperature is 730 ℃～800 ℃, and the flow of TMGa is 10mL/min～15mL/min, and the flow of TMIn is 650mL/min～750mL/min, NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min, growth thickness are the InGaN potential well layer of 2.5nm～3nm.
S2042: temperature is 730 ℃～800 ℃, and the flow of TMGa is 10mL/min～15mL/min, NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min; Growth thickness is the GaN barrier layer of 12nm～13nm.
S205: temperature is 800 ℃～850 ℃, and the flow of TMGa is 40mL/min～60mL/min, NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min; Cp
2The flow of Mg is 600mL/min～700mL/min; Growth thickness is the P type GaN layer 6 of 50nm～60nm.
S206: temperature is 900 ℃～950 ℃, and chamber pressure is 150mbar～250mbar, and the flow of TMGa is 30mL/min～45mL/min, and the flow of TMAl is 50mL/min～80mL/min, NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min; Cp
2The flow of Mg is 700mL/min～800mL/min; Continue duration 120s～200s, growth thickness is to be called for short PAlGaN among the P type AlGaN electronic barrier layer 7(embodiment of 30nm～40nm).
S207: the P type superlattice 9 that growth is made of PInGaN potential well layer 91 and PAlGaN barrier layer 92 periodicity intermeshings.The preferred following steps that adopt:
Carry out the following operation in 2～4 cycles:
S2071: temperature is 900 ℃～950 ℃, and chamber pressure is 150mbar～250mbar, and the flow of TMGa is 30mL/min～45mL/min, and the flow of TMIn is 300mL/min～450mL/min, NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min, Cp
2The flow of Mg is 700mL/min～800mL/min; Continue duration 10s～20s, growth thickness is the PInGaN potential well layer 91 of 3nm～5nm.
S2072: temperature is 900 ℃～950 ℃, and chamber pressure is 150mbar～250mbar, and the flow of TMGa is 30mL/min～45mL/min, and the flow of TMAl is 60mL/min～80mL/min, NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min, Cp
2The flow of Mg is 700mL/min～800mL/min; Continue duration 10s～20s, growth thickness is the PAlGaN barrier layer 92 of 3nm～5nm.
S208: temperature is 1050 ℃～1100 ℃, and the flow of TMGa is 55mL/min～70mL/min, NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min, Cp
2The flow of Mg is 400mL/min～750mL/min, and growth thickness is the 2nd P type GaN layer 8 of 200nm～250nm.
S3: the product that above-mentioned steps is obtained places 650 ℃～700 ℃ N
215min～the 20min that anneals under the atmosphere makes LED epitaxial structure of the present invention.
The preparation method of the LED epitaxial structure of following Comparative Examples comprises above-mentioned step S1, step S201 to step S206, step S208 and step S3, but does not comprise step S207.And, in the Comparative Examples, be called for short PAlGaN in the P type AlGaN electronic barrier layer 7(Comparative Examples for preparing among the step S206) thickness range be 50nm～60nm.
The technological parameter of the step S206 of embodiment 1 and step S207, and the technological parameter of the step S206 of Comparative Examples 1 is as shown in table 1.And the thickness PAlGaN(P type AlGaN electronic barrier layer 7 of growth among the embodiment 1) is 30nm, P type superlattice 9 by the thickness in 2 cycles be the PInGaN potential well layer 91 of 5nm and PAlGaN barrier layer 92 that thickness is 5nm periodically intermeshings consist of.The PAlGaN(P type AlGaN electronic barrier layer 7 of growth in the Comparative Examples 1) thickness is 50nm.
The step S206 of table 1 embodiment 1 and step S207, and the technological parameter of the step S206 of Comparative Examples 1
In the table 1, each source gas all is to pass into simultaneously, does not pass into during without the expression growth.
Make embodiment 1 and Comparative Examples 1 to such an extent that epitaxial wafer carries out respectively the C-V test, obtain the P layer hole concentration distribution map of epitaxial wafer as shown in Figure 4.2 kinds of epitaxial wafers are made respectively the chip of 10mil*23mil, 45mil*45mil size in same chip technology, the electrical parameter of detection chip under identical testing environment, test condition: the 10mil*23mil chip is measured under 20mA, 45mil*45mil measures under 350mA, obtains the test result shown in Fig. 5 (10mil*23mil size), Fig. 6 (45mil*45mil size).
Can be got by Fig. 4, Fig. 5, Fig. 6 analysis:
1, ECV test result (Fig. 4) draws, in the time of etching depth h=0.2 μ m, in the epitaxial wafer of embodiment 1, PAlGaN(P type AlGaN electronic barrier layer 7) with the position at P type superlattice 9 places, it is maximum that the hole concentration value reaches, PAlGaN(P type AlGaN electronic barrier layer 7 in the epitaxial wafer of Comparative Examples 1) locate hole concentration value basis and improve 4～5 times.Simultaneously the hole concentration at HTP and LTP place also is subject to aforementioned affect and increases in the epitaxial wafer of embodiment 1.
2, chip electric parameter detecting result (Fig. 5, Fig. 6) draws, the led chip brightness of 10mil*23mil size: the chip that embodiment 1 makes promotes 5～8% than the chip brightness that Comparative Examples 1 makes; The led chip brightness of 45mil*45mil size: the chip that embodiment 1 makes promotes 8～10% than the chip that Comparative Examples 1 makes.
The technological parameter of the step S206 of embodiment 2 and step S207, and the technological parameter of the step S206 of Comparative Examples 2 is as shown in table 2.And the thickness PAlGaN(P type AlGaN electronic barrier layer 7 of growth among the embodiment 2) is 32nm, P type superlattice 9 by the thickness in 3 cycles be the PInGaN potential well layer 91 of 3nm and PAlGaN barrier layer 92 that thickness is 3nm periodically intermeshings consist of.The PAlGaN(P type AlGaN electronic barrier layer 7 of growth in the Comparative Examples 2) thickness is 50nm.
The step S206 of table 2 embodiment 2 and step S207, and the technological parameter of the step S206 of Comparative Examples 2
In the table 2: each source gas all is to pass into simultaneously, does not pass into during without the expression growth.
Make embodiment 2 and Comparative Examples 2 to such an extent that epitaxial wafer is made respectively the chip of 10mil*23mil, 45mil*45mil size in same chip technology, the electrical parameter of detection chip under identical testing environment, test condition: the 10mil*23mil chip is measured under 20mA, 45mil*45mil measures under 350mA, obtains the test result shown in Fig. 7 (10mil*23mil size), Fig. 8 (45mil*45mil size).
Can be got by Fig. 7, Fig. 8 analysis:
1, chip electric parameter detecting result (Fig. 7, Fig. 8) draws, the led chip brightness of 10mil*23mil size: the chip that embodiment 2 makes promotes 5～8% than the chip brightness that Comparative Examples 2 makes; The led chip brightness of 45mil*45mil size: the chip that embodiment 2 makes promotes 8～10% than the chip that Comparative Examples 2 makes.
Embodiment 3:
The technological parameter of the step S206 of embodiment 3 and step S207 is as shown in table 3.And the thickness PAlGaN(P type AlGaN electronic barrier layer 7 of growth among the embodiment 3) is 36nm, P type superlattice 9 by the thickness in 2 cycles be the PInGaN potential well layer 91 of 4nm and PAlGaN barrier layer 92 that thickness is 4nm periodically intermeshings consist of.
The technological parameter of the step S206 of table 3 embodiment 3 and step S207
In the table 3: each source gas all is to pass into simultaneously, does not pass into during without the expression growth.
Embodiment 4:
The technological parameter of the step S206 of embodiment 4 and step S207 is as shown in table 4.And the thickness PAlGaN(P type AlGaN electronic barrier layer 7 of growth among the embodiment 4) is 40nm, P type superlattice 9 by the thickness in 4 cycles be the PInGaN potential well layer 91 of 5nm and PAlGaN barrier layer 92 that thickness is 5nm periodically intermeshings consist of.
The technological parameter of the step S206 of table 4 embodiment 4 and step S207
In the table 4: each source gas all is to pass into simultaneously, does not pass into during without the expression growth.
In above embodiment 1～embodiment 4, Comparative Examples 1, the Comparative Examples 2 NM step S1, step S201 to step S205, step S208 and the step S3 technological parameter and the growth thickness numerical value of each layer, can in aforesaid number range, adopt according to actual needs existing technological means to adjust arbitrarily, not affect whole structure of the present invention.
By embodiment 1, embodiment 2 respectively with the contrast of the test result of Comparative Examples 1 and Comparative Examples 2 as can be known, the LED epitaxial structure with P type superlattice 9 of the present invention can be by improving hole concentration, and then the brightness 5～10% of raising chip.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. LED epitaxial structure with P type superlattice, comprise substrate, be disposed with from the bottom to top GaN resilient coating, not Doped GaN layer, N-shaped GaN layer, multiple quantum well light emitting layer, a P type GaN layer, P type AlGaN electronic barrier layer, the 2nd P type GaN layer on the described substrate, it is characterized in that
Be provided with the P type superlattice that consisted of by PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing between described P type AlGaN electronic barrier layer and described the 2nd P type GaN layer.
2. LED epitaxial structure according to claim 1 is characterized in that, described P type superlattice are made of PInGaN potential well layer and the PAlGaN barrier layer intermeshing in 2～4 cycles; And the described PInGaN potential well layer of described period 1 is overlying on the described PAlGaN electronic barrier layer.
3. LED epitaxial structure according to claim 3 is characterized in that,
The thickness of described P type superlattice is 12nm～40nm;
In the described P type superlattice, the thickness of the described PInGaN potential well layer in single cycle is 3nm～5nm; The thickness of the described PAlGaN barrier layer in single cycle is 3nm～5nm.
4. LED epitaxial structure according to claim 2 is characterized in that,
The thickness of described GaN resilient coating is 20nm～30nm;
The thickness of described not Doped GaN layer is 2 μ m～2.5 μ m;
The thickness of described N-shaped GaN layer is 2 μ m～2.5 μ m;
The thickness of described multiple quantum well light emitting layer is 200nm～260nm;
The thickness of a described P type GaN layer is 50nm～60nm;
The thickness of described P type InAlGaN electronic barrier layer is 30nm～40nm;
The thickness of described P type GaN layer is 200nm～250nm.
5. each described LED epitaxial structure in 4 according to claim 1 is characterized in that described multiple quantum well light emitting layer is made of InGaN potential well layer and the mutual stack of GaN barrier layer in 15～16 cycles;
In the described multiple quantum well light emitting layer: the thickness of the described InGaN potential well layer in single cycle is 2.5nm～3nm; The thickness of the described GaN barrier layer in single cycle is 12nm～13nm.
6. LED epitaxial structure according to claim 5 is characterized in that, the P type GaN layer of a described P type GaN layer for generating under 800 ℃～850 ℃ temperature conditions; The P type GaN layer of described the 2nd P type GaN layer under 1050 ℃～1100 ℃ temperature conditions, generating.
7. the preparation method with LED epitaxial structure of P type superlattice is characterized in that, may further comprise the steps:
S1: select substrate;
S2: take TMGa as the Ga source, take TMAl as the Al source, take TMIn as the In source, with NH
3Be the N source, on described substrate, carry out successively following steps:
S201: growing GaN resilient coating;
S202: the not Doped GaN layer of growing;
S203: growing n-type GaN layer;
S204: growth multiple quantum well light emitting layer;
S205: the P type GaN layer of growing;
S206: growing P-type AlGaN electronic barrier layer;
It is characterized in that, among the described step S2, finish described S206 after, further comprising the steps of:
S207: the P type superlattice that growth is made of PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing;
S208: the 2nd P type GaN layer of growing.
8. preparation method according to claim 7 is characterized in that, described step S207 may further comprise the steps:
Carry out the following operation in 2～4 cycles:
S2071: growth thickness is the PInGaN potential well layer of 3nm～5nm;
S2072: growth thickness is the PAlGaN barrier layer of 3nm～5nm.
9. preparation method according to claim 8 is characterized in that, described step S204 may further comprise the steps:
Carry out the following operation in 13～15 cycles:
S2041: growth thickness is the InGaN potential well layer of 2.5nm～3nm;
S2042: growth thickness is the GaN barrier layer of 12nm～13nm.
10. preparation method according to claim 8 is characterized in that, the technological parameter of described each step of preparation method is as follows:
Among the described step S201, be that the flow of described TMGa is 55mL/min～75mL/min, described NH under 530 ℃～570 ℃ conditions in temperature
3Flow be 1.1 * 10
4ML/min～1.3 * 10
4Growth thickness is the GaN resilient coating of 20nm～30nm under the process conditions of mL/min; Then be warming up to 1030 ℃～1100 ℃, and keep 180s～210s, make described GaN resilient coating recrystallization;
Among the described step S202, temperature is 1000 ℃～1250 ℃, and the flow of described TMGa is 180mL/min～210mL/min, described NH
3Flow be 2.1 * 10
4ML/min～2.4 * 10
4ML/min; Growth thickness is 2 μ m～2.5 μ m;
Among the described step S203, temperature is 1000 ℃～1250 ℃, and the flow of described TMGa is 200mL/min～250mL/min, described NH
3Flow be 2.5 * 10
4ML/min～3 * 10
4ML/min, described SiH
4Flow be 14mL/min～18mL/min; Growth thickness is 2 μ m～2.5 μ m;
Among the described step S2041, temperature is 730 ℃～800 ℃, and the flow of described TMGa is 10mL/min～15mL/min, and the flow of described TMIn is 650mL/min～750mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min;
Among the described step S2042, temperature is 730 ℃～800 ℃, and the flow of described TMGa is 10mL/min～15mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min;
Among the described step S205, temperature is 800 ℃～850 ℃, and the flow of described TMGa is 40mL/min～60mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min; Described Cp
2The flow of Mg is 600mL/min～700mL/min; Growth thickness is 50nm～60nm;
Among the described step S206, temperature is 900 ℃～950 ℃, and chamber pressure is 150mbar～250mbar, and the flow of described TMGa is 30mL/min～45mL/min, and the flow of described TMAl is 50mL/min～80mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min; Described Cp
2The flow of Mg is 700mL/min～800mL/min; Growth thickness is 30nm～40nm;
Among the described step S2071, temperature is 900 ℃～950 ℃, and chamber pressure is 150mbar～250mbar, and the flow of described TMGa is 30mL/min～45mL/min, and the flow of described TMIn is 300mL/min～450mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min, described Cp
2The flow of Mg is 700mL/min～800mL/min;
Among the described step S2072, temperature is 900 ℃～950 ℃, and chamber pressure is 150mbar～250mbar, and the flow of described TMGa is 30mL/min～45mL/min, and the flow of described TMAl is 60mL/min～80mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min, described Cp
2The flow of Mg is 700mL/min～800mL/min;
Among the described step S8, temperature is 1050 ℃～1100 ℃, and the flow of described TMGa is 55mL/min～70mL/min, described NH
3Flow be 3 * 10
4ML/min～3.3 * 10
4ML/min, described Cp
2The flow of Mg is 400mL/min～750mL/min, and growth thickness is 200nm～250nm.
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