CN103050592B - There is LED epitaxial structure of P type superlattice and preparation method thereof - Google Patents
There is LED epitaxial structure of P type superlattice and preparation method thereof Download PDFInfo
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- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 24
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Abstract
The invention discloses and a kind of there is LED epitaxial structure of P type superlattice and preparation method thereof.This epitaxial structure comprises substrate, substrate is disposed with from the bottom to top GaN resilient coating, layer of undoped gan, n-type GaN layer, multiple quantum well light emitting layer, a P type GaN layer, P type AlGaN electronic barrier layer, the 2nd P type GaN layer, between P type AlGaN electronic barrier layer and the 2nd P type GaN layer, is provided with the P type superlattice be made up of PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing.PInGaN potential well layer in P type superlattice is by generation and fetter a large amount of hole, forms Two-Dimensional Hole high-density state; PAlGaN barrier layer will hinder the escape in hole, improve the extending transversely of hole, can block electrons excessive, increase hole injection efficiency, improve electronics and hole-recombination probability, the brightness 5 ~ 10% of chip can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, especially, relate to and a kind of there is LED epitaxial structure of P type superlattice and preparation method thereof.
Background technology
GaN, due to its excellent characteristic, has become the important materials manufacturing luminescent device, high temperature high power device and ultraviolet detector.The doping of P type manufactures the requisite important step of GaN device, therefore attracted the attention of a lot of research group.Due to the passivation (passivation) of Mg, undressed GaN:Mg resistivity, up to 10Qcm, must activate (Activation) Mg after growth, to obtain the P type GaN that can be applied to device.Within 1989, H.Amano achieves the important breakthrough of P type, and he utilizes low-energy electron beam radiation (IEEBI) to process the GaN mixing Mg, obtains the P type GaN of low-resistance.1991, S.Nakamura etc. invented rapid thermal anneal methods (RapidThermalAnnealing), have successfully been obtained the GaN of P type, and the process of Design and manufacture business blue green light LED is accelerated greatly.
During with MOCVD technology growth p-type GaN, acceptor Mg atom by the serious passivation of H, can obtain the uniform p-type GaN of hole concentration by the method for thermal annealing in growth course under N2 atmosphere.In order to obtain P type GaN material of good performance, people have studied the impact of the high temperature anneal on GaN electric property, the characteristics of luminescence, and Mg in p-type GaN
2the passivation effect, acceptor activation mechanism etc. of H complex.Although the sample after suitable annealing in process has changed into p-type sample, the hole concentration obtained is still lower, and representative value is 2 × 10
17cm
-3, 2 ~ 3 orders of magnitude lower than doping content.
Therefore, the hole concentration how improving P layer becomes the key of P type GaN growth, and traditional comprises common P layer LED epitaxial structure as shown in Figure 1, and its preparation method is: at high temperature, H
2atmosphere process substrate 1 continues 5 ~ 6min; Regrowth GaN resilient coating 2; Regrowth layer of undoped gan 3 (U-GaN); Regrowth n-type GaN layer (Si doping type N-GaN); Regrowth multiple quantum well light emitting layer 5; Regrowth the one P type GaN layer 6 (LTP, low temperature P type GaN); Secondly growing P-type AlGaN electronic barrier layer 7 (being called for short PAlGaN), finally grows the 2nd P type GaN layer 8 (HTP, high temperature P type GaN).Wherein, HTP thickness 140-150nm, PAlGaN thickness 50 ~ 60nm, LTP thickness 50 ~ 60nm, HTP hole concentration is high, and PAlGaN, LTP hole concentration is on the low side, and hole is injected into multiple quantum well light emitting layer through HTP, PAlGaN, LTP.According to the electronic theory of PN junction, hole migration is actual is the propagation of electric field, the height of the hole concentration of HTP, PAlGaN, LTP will determine that the efficiency of multiple quantum well light emitting layer 5 is injected in hole, the thinner thickness of traditional PAlGaN, LTP, and it is nearest apart from quantum well, thus it is low to make the not high and then hole of the hole concentration of traditional PAlGaN, LTP be injected into the efficiency of multiple quantum well light emitting layer, thus reduce the luminosity of the LED chip of unit are.
Summary of the invention
The object of the invention is to provide a kind of energy bound hole, by improving hole concentration, and then the brightness of raising chip has LED epitaxial structure of P type superlattice and preparation method thereof, not high with the hole concentration solving traditional PAlGaN, LTP, hole injection efficiency is low, the technical problem that the luminosity of LED chip is low.
For achieving the above object, the invention provides a kind of LED epitaxial structure with P type superlattice, comprise substrate, described substrate is disposed with from the bottom to top GaN resilient coating, layer of undoped gan, n-type GaN layer, multiple quantum well light emitting layer, a P type GaN layer, P type AlGaN electronic barrier layer, the 2nd P type GaN layer
The P type superlattice be made up of PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing are provided with between described P type AlGaN electronic barrier layer and described 2nd P type GaN layer.
Further improvement as epitaxial structure of the present invention:
Preferably, described P type superlattice are made up of the PInGaN potential well layer in 2 ~ 4 cycles and PAlGaN barrier layer intermeshing; And the described PInGaN potential well layer of described period 1 is overlying on described PAlGaN electronic barrier layer.
Preferably, the thickness of described P type superlattice is 12nm ~ 40nm;
Preferably, in described P type superlattice, the thickness of the described PInGaN potential well layer in single cycle is 3nm ~ 5nm; The thickness of the described PAlGaN barrier layer in single cycle is 3nm ~ 5nm.
Preferably, the thickness of described GaN resilient coating is 20nm ~ 30nm;
The thickness of described layer of undoped gan is 2 μm ~ 2.5 μm;
The thickness of described n-type GaN layer is 2 μm ~ 2.5 μm;
The thickness of described multiple quantum well light emitting layer is 200nm ~ 260nm;
The thickness of a described P type GaN layer is 50nm ~ 60nm;
The thickness of described P type AlGaN electronic barrier layer is 30nm ~ 40nm;
The thickness of described P type GaN layer is 200nm ~ 250nm.
Preferably, described multiple quantum well light emitting layer is superposed alternately by the InGaN potential well layer in 15 ~ 16 cycles and GaN barrier layer and forms;
In described multiple quantum well light emitting layer: the thickness of the described InGaN potential well layer in single cycle is 2.5nm ~ 3nm; The thickness of the described GaN barrier layer in single cycle is 12nm ~ 13nm.
Preferably, a described P type GaN layer is the P type GaN layer generated under 800 DEG C ~ 850 DEG C temperature conditions; Described 2nd P type GaN layer is the P type GaN layer generated under 1050 DEG C ~ 1100 DEG C temperature conditions.
As a total technical conceive, present invention also offers a kind of preparation method with the LED epitaxial structure of P type superlattice, it is characterized in that, comprise the following steps:
S1: select substrate;
S2: be Ga source with TMGa, being Al source with TMAl, is In source with TMIn, with NH
3for N source, carry out following steps successively over the substrate:
S201: growing GaN resilient coating;
S202: growth layer of undoped gan;
S203: growing n-type GaN layer;
S204: growth multiple quantum well light emitting layer;
S205: growth the one P type GaN layer;
S206: growing P-type AlGaN electronic barrier layer;
In described step S2, after completing described S206, described method is further comprising the steps of:
S207: grow the P type superlattice be made up of PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing;
S208: growth the 2nd P type GaN layer.
As further improvements in methods of the present invention:
Preferably, described step S207 comprises the following steps:
Carry out the following operation in 2 ~ 4 cycles:
S2071: growth thickness is the PInGaN potential well layer of 3nm ~ 5nm;
S2072: growth thickness is the PAlGaN barrier layer of 3nm ~ 5nm.
Preferably, described step S204 comprises the following steps:
Carry out the following operation in 13 ~ 15 cycles:
S2041: growth thickness is the InGaN potential well layer of 2.5nm ~ 3nm;
S2042: growth thickness is the GaN barrier layer of 12nm ~ 13nm.
Preferably, the technological parameter of each step of described preparation method is as follows:
In described step S201, under temperature is 530 DEG C ~ 570 DEG C conditions, the flow of described TMGa is 55mL/min ~ 75mL/min, described NH
3flow be 1.1 × 10
4mL/min ~ 1.3 × 10
4under the process conditions of mL/min, growth thickness is the GaN resilient coating of 20nm ~ 30nm; Then be warming up to 1030 DEG C ~ 1100 DEG C, and keep 180s ~ 210s, make described GaN resilient coating recrystallization;
In described step S202, temperature is 1000 DEG C ~ 1250 DEG C, and the flow of described TMGa is 180mL/min ~ 210mL/min, described NH
3flow be 2.1 × 10
4mL/min ~ 2.4 × 10
4mL/min; Growth thickness is 2 μm ~ 2.5 μm;
In described step S203, temperature is 1000 DEG C ~ 1250 DEG C, and the flow of described TMGa is 200mL/min ~ 250mL/min, described NH
3flow be 2.5 × 10
4mL/min ~ 3 × 10
4mL/min, described SiH
4flow be 14mL/min ~ 18mL/min; Growth thickness is 2 μm ~ 2.5 μm;
In described step S2041, temperature is 730 DEG C ~ 800 DEG C, and the flow of described TMGa is 10mL/min ~ 15mL/min, and the flow of described TMIn is 650mL/min ~ 750mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min;
In described step S2042, temperature is 730 DEG C ~ 800 DEG C, and the flow of described TMGa is 10mL/min ~ 15mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min;
In described step S205, temperature is 800 DEG C ~ 850 DEG C, and the flow of described TMGa is 40mL/min ~ 60mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min; Described Cp
2the flow of Mg is 600mL/min ~ 700mL/min; Growth thickness is 50nm ~ 60nm;
In described step S206, temperature is 900 DEG C ~ 950 DEG C, and chamber pressure is 150mbar ~ 250mbar, and the flow of described TMGa is 30mL/min ~ 45mL/min, and the flow of described TMAl is 50mL/min ~ 80mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min; Described Cp
2the flow of Mg is 700mL/min ~ 800mL/min; Growth thickness is 30nm ~ 40nm;
In described step S2071, temperature is 900 DEG C ~ 950 DEG C, and chamber pressure is 150mbar ~ 250mbar, and the flow of described TMGa is 30mL/min ~ 45mL/min, and the flow of described TMIn is 300mL/min ~ 450mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min, described Cp
2the flow of Mg is 700mL/min ~ 800mL/min;
In described step S2072, temperature is 900 DEG C ~ 950 DEG C, and chamber pressure is 150mbar ~ 250mbar, and the flow of described TMGa is 30mL/min ~ 45mL/min, and the flow of described TMAl is 60mL/min ~ 80mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min, described Cp
2the flow of Mg is 700mL/min ~ 800mL/min;
In described step S8, temperature is 1050 DEG C ~ 1100 DEG C, and the flow of described TMGa is 55mL/min ~ 70mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min, described Cp
2the flow of Mg is 400mL/min ~ 750mL/min, and growth thickness is 200nm ~ 250nm.
The present invention has following beneficial effect:
1, the LED epitaxial structure with P type superlattice of the present invention, arranges the P type superlattice be made up of PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing between P type AlGaN electronic barrier layer and the 2nd P type GaN layer.PInGaN potential well layer in P type superlattice is by generation and fetter a large amount of hole, forms Two-Dimensional Hole high-density state; PAlGaN barrier layer will hinder the escape in hole, improve the extending transversely of hole, can block electrons excessive, increase hole injection efficiency, improve electronics and hole-recombination probability, and then improve the brightness of chip.
2, the preparation method with the LED epitaxial structure of P type superlattice of the present invention, processing step is simple, by growing between P type AlGaN electronic barrier layer and the 2nd P type GaN layer by PInGaN potential well layer and the PAlGaN barrier layer periodically P type superlattice that form of intermeshing.The LED epitaxial structure with P type superlattice of the present invention can be prepared, and be suitable for suitability for industrialized production.
Except object described above, feature and advantage, the present invention also has other object, feature and advantage.Below with reference to figure, the present invention is further detailed explanation.
Accompanying drawing explanation
The accompanying drawing forming a application's part is used to provide a further understanding of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is traditional cross-sectional view comprising common P layer LED epitaxial structure;
Fig. 2 is the cross-sectional view with the LED epitaxial structure of P type superlattice of the preferred embodiment of the present invention 1;
Fig. 3 is that the LED epitaxial structure with P type superlattice of the preferred embodiment of the present invention 1 and traditional being with of common P layer LED epitaxial structure that comprise contrast schematic diagram; Wherein, what Fig. 3 (1) was invention preferred embodiment 1 has being with of the LED epitaxial structure of P type superlattice; Fig. 3 (2) comprises being with of common P layer LED epitaxial structure for traditional.
Fig. 4 is profiles versus's schematic diagram of the hole concentration of the P layer of the LED epitaxial structure of the preferred embodiment of the present invention 1 and the LED epitaxial structure of comparative example 1; Wherein, " ■ " is the distribution schematic diagram of the hole concentration of the P layer of the LED epitaxial structure of traditional comparative example 1; The distribution schematic diagram of the hole concentration of the P layer that " ▲ " is the LED epitaxial structure of the preferred embodiment of the present invention 1.
Fig. 5 is the brightness contrast schematic diagram that the epitaxial wafer of the preferred embodiment of the present invention 1 and the epitaxial wafer of comparative example 1 are prepared into the LED chip of 10mil*23mil size respectively; Wherein, the epitaxial wafer that " ▲ " is comparative example 1 is prepared into the brightness schematic diagram of the LED chip of 10mil*23mil size; "-" is the brightness schematic diagram that the epitaxial wafer of the preferred embodiment of the present invention 1 is prepared into the LED chip of 10mil*23mil size;
Fig. 6 is the brightness contrast schematic diagram that the epitaxial wafer of the preferred embodiment of the present invention 1 and the epitaxial wafer of comparative example 1 are prepared into the LED chip of 45mil*45mil size respectively; Wherein, the epitaxial wafer that " ◆ " is comparative example 1 is prepared into the brightness schematic diagram of the LED chip of 45mil*45mil size; "-" is the brightness schematic diagram that the epitaxial wafer of the preferred embodiment of the present invention 1 is prepared into the LED chip of 45mil*45mil size;
Fig. 7 is the brightness contrast schematic diagram that the epitaxial wafer of the preferred embodiment of the present invention 2 and the epitaxial wafer of comparative example 2 are prepared into the LED chip of 10mil*23mil size respectively; Wherein, the epitaxial wafer that " ▲ " is comparative example 2 is prepared into the brightness schematic diagram of the LED chip of 10mil*23mil size; "-" is the brightness schematic diagram that the epitaxial wafer of the preferred embodiment of the present invention 2 is prepared into the LED chip of 10mil*23mil size; And
Fig. 8 is the brightness contrast schematic diagram that the epitaxial wafer of the preferred embodiment of the present invention 2 and the epitaxial wafer of comparative example 2 are prepared into the LED chip of 45mil*45mil size respectively; Wherein ， “ ▃ ◆ ▃ " be prepared into the brightness schematic diagram of the LED chip of 45mil*45mil size for the epitaxial wafer of comparative example 2; “ ▂ ▂ " be prepared into the brightness schematic diagram of the LED chip of 45mil*45mil size for the epitaxial wafer of the preferred embodiment of the present invention 1.
Marginal data:
1, substrate; 2, GaN resilient coating; 3, layer of undoped gan; 4, n-type GaN layer; 5, multiple quantum well light emitting layer; 6, a P type GaN layer; 7, P type AlGaN electronic barrier layer; 8, the 2nd P type GaN layer; 9, P type superlattice; 91, PInGaN potential well layer; 92, PAlGaN barrier layer.
Embodiment
Below in conjunction with accompanying drawing, embodiments of the invention are described in detail, but the multitude of different ways that the present invention can be defined by the claims and cover is implemented.
The invention provides a kind of LED epitaxial structure with P type superlattice, by arranging PInGaN potential well layer 91 and PAlGaN barrier layer 92 periodically P type superlattice 9 structure that forms of intermeshing between P type AlGaN electronic barrier layer 7 and the 2nd P type GaN layer 8 (HTP), PInGaN potential well layer 91 in P type superlattice 9 is by generation and fetter a large amount of hole, forms Two-Dimensional Hole high-density state; PAlGaN barrier layer 92 will hinder the escape in hole, improve the extending transversely of hole, can block electrons excessive, increase hole injection efficiency, improve electronics and hole-recombination probability, and then reach the object of the brightness improving chip.
In literary composition, potential well refers to that the area of space that potential energy is all lower than neighbouring potential energy, potential barrier refer to the area of space that potential energy is all higher than neighbouring potential energy.Potential well in superlattice herein and be converted to quantum level between potential barrier.As shown in Figure 3, vertical transition is converted between potential well and potential barrier.
As shown in Figure 2, the LED epitaxial structure with P type superlattice of the present invention, comprise substrate 1, substrate 1 is disposed with from the bottom to top GaN resilient coating 2, layer of undoped gan 3, n-type GaN layer 4, multiple quantum well light emitting layer 5, a P type GaN layer 6, P type AlGaN electronic barrier layer 7, by PInGaN potential well layer 91 and PAlGaN barrier layer 92 periodically P type superlattice the 9, the 2nd P type GaN layer 8 that forms of intermeshing.During practical application, P type superlattice 9 are made up of the PInGaN potential well layer 91 in 2 ~ 4 cycles and PAlGaN barrier layer 92 intermeshing, and effect is better.The PInGaN potential well layer 91 of period 1 (from the bottom to top for along number) is overlying on PAlGaN electronic barrier layer, namely in the P type superlattice 9 single cycle, be PInGaN potential well layer 91 under, PAlGaN barrier layer 92 is in upper structure.Preferably, one P type GaN layer 6 is the P type GaN layer (LTP generated under 800 DEG C ~ 850 DEG C temperature conditions, low temperature P type GaN), the 2nd P type GaN layer 8 is the P type GaN layer (HTP, high temperature P type GaN) generated under 1050 DEG C ~ 1100 DEG C temperature conditions.
PInGaN energy bandwidth is narrower, and PAlGaN energy broader bandwidth, because the difference that can be with, PInGaN and PAlGaN structure will produce quantum well structure, and thickness preferably controls in the control ability of 3-5nm to hole stronger, more weak to the binding energy force rate of electronics.In composition graphs 3 shown in (2), narrow can with the valence band of PInGaN can be with closer to Mg, the activation energy that Mg needs is lower, the Mg of identical doping content more easily discharges hole, have the quantum well structure of depth stop to possess the ability of bound hole, widely the PAlGaN of band can be unfavorable for the activation of Mg on the contrary, it is few that the Mg of identical doping content discharges number of cavities, resistance is higher, and hole mobility is low.PInGaN well layer hole concentration is high, and mobility is higher, and horizontal and vertical conduction is strengthened, because the width of PInGaN well layer longitudinal direction is much less than horizontal width, longitudinal conduction is strengthened becoming not obvious, and mainly ability extending transversely is strengthened, macroscopically can homogenizing conduction current.The contrary wide PAlGaN that can be with will be unfavorable for the conduction in hole, hinder the escape in PInGaN well layer hole, and in composition graphs 3 (2), the PAlGaN of quality fine paper, by stopping the electronics of N Es-region propagations, prevents electronics excessive to P layer; The effect that this structure plays is summed up as bound hole, improve hole extending transversely, hinder the escape in hole, block electrons excessive; You need to add is that traditional LED epitaxial structure only comprises block electrons excessive, and be PAlGaN component, hole concentration low (in detail see Fig. 4) injection efficiency is poor.Structure of the present invention addresses this problem emphatically, macroscopically be presented as that the electron concentration of luminescent layer remains unchanged, hole concentration is because the reinforcement of injecting and the increase of quantity, and the electronics of luminescent layer and the combined efficiency in hole improve, improve chip internal quantum efficiency, thus the brightness of LED gets a promotion.
During practical application, the thickness of each layer of LED epitaxial structure is rationally arranged, also by effect that the electronic blocking that affects in LED epitaxial structure and hole inject.When the thickness of each layer is preferably arranged in following scope, effect is better: the thickness of GaN resilient coating 2 is 20nm ~ 30nm; The thickness of layer of undoped gan 3 is 2 μm ~ 2.5 μm; The thickness of n-type GaN layer 4 is 2 μm ~ 2.5 μm; The thickness of multiple quantum well light emitting layer 5 is 200nm ~ 260nm, and preferably, multiple quantum well light emitting layer 5 is superposed alternately by the InGaN potential well layer in 15 ~ 16 cycles and GaN barrier layer and forms; In multiple quantum well light emitting layer 5: the thickness of the InGaN potential well layer in single cycle is 2.5nm ~ 3nm; The thickness of the GaN barrier layer in single cycle is 12nm ~ 13nm.The thickness of the one P type GaN layer 6 is 50nm ~ 60nm; The thickness of P type GaN layer is 200nm ~ 250nm.More importantly, the thickness of P type AlGaN electronic barrier layer is set to 30nm ~ 40nm; The thickness of P type superlattice 9 is 12nm ~ 40nm.In P type superlattice 9, the thickness of the PInGaN potential well layer 91 in single cycle is 3nm ~ 5nm; The thickness of the PAlGaN barrier layer 92 in single cycle is 3nm ~ 5nm.P type AlGaN electronic blocking is placed on the lower floor of superlattice, the electronics of being come by the N layer under it can be stopped, then, superlattice thereon layer solve hole injection problem, so both can prevent electronics from leaking, and can retain the effect of conventional P type AlGaN block electrons, hole concentration can be improved again, and then raising hole injection efficiency, improve electronics and hole-recombination probability, and then improve the brightness of chip.
Present invention also offers a kind of preparation method with the LED epitaxial structure of P type superlattice, by growing the P type superlattice 9 be made up of PInGaN potential well layer 91 and PAlGaN barrier layer 92 periodicity intermeshing between P type AlGaN electronic barrier layer 7 and the 2nd P type GaN layer 8, the LED epitaxial structure with P type superlattice of the present invention can be obtained.
Below by specific embodiment, this preparation method of analytic explanation.
Trimethyl gallium (TMGa) used in following examples, trimethyl aluminium (TMAl), trimethyl indium (TMIn), two luxuriant U.S. (Cp
2mg), silane (SiH
4), ammonia (NH3) and unclassified stores be common commercially available.Preparation equipment used in following examples is MOCVD device, also be common commercial equipment, and in following examples, use MOCVD device to be only citing needs, and the equipment that non-limiting preparation method of the present invention is used, other equipment that may be used for each semiconductor layer preparing the method are all applicable to preparation method of the present invention.
The preparation method of the LED epitaxial structure of following examples comprises the following steps:
S1: select Sapphire Substrate 1 (during practical application, also can select SiC substrate or Si substrate); Sapphire Substrate 1 is placed in H
2under atmosphere, be heated to 1100 DEG C and keep 400s, to remove the H on substrate 1 surface
2o and O
2.Cool to 500 DEG C again, and pass into NH
3substrate 1 is carried out to the nitrogen treatment of 200s.
S2: be Ga source with TMGa, being Al source with TMAl, is In source with TMIn, with NH
3for N source, carry out following steps successively on substrate 1:
S201: under temperature is 530 DEG C ~ 570 DEG C conditions, the flow of TMGa is 55mL/min ~ 75mL/min, NH
3flow be 1.1 × 10
4mL/min ~ 1.3 × 10
4under the process conditions of mL/min, growth thickness is the GaN resilient coating 2 of 20nm ~ 30nm; Then be warming up to 1030 DEG C ~ 1100 DEG C, and keep 180s ~ 210s, make GaN resilient coating 2 recrystallization.
S202: temperature is 1000 DEG C ~ 1250 DEG C, the flow of TMGa is 180mL/min ~ 210mL/min, NH
3flow be 2.1 × 10
4mL/min ~ 2.4 × 10
4mL/min; Growth thickness is the layer of undoped gan 3 of 2 μm ~ 2.5 μm.
S203: temperature is 1000 DEG C ~ 1250 DEG C, the flow of TMGa is 200mL/min ~ 250mL/min, NH
3flow be 2.5 × 10
4mL/min ~ 3 × 10
4mL/min, SiH
4flow be 14mL/min ~ 18mL/min; Growth thickness is the n-type GaN layer 4 of 2 μm ~ 2.5 μm.
S204: growth multiple quantum well light emitting layer 5, preferred step is:
Carry out the following operation in 13 ~ 15 cycles:
The flow of S2041: temperature is 730 DEG C ~ 800 DEG C, TMGa is the flow of 10mL/min ~ 15mL/min, TMIn is 650mL/min ~ 750mL/min, NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min, growth thickness is the InGaN potential well layer of 2.5nm ~ 3nm.
S2042: temperature is 730 DEG C ~ 800 DEG C, the flow of TMGa is 10mL/min ~ 15mL/min, NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min; Growth thickness is the GaN barrier layer of 12nm ~ 13nm.
S205: temperature is 800 DEG C ~ 850 DEG C, the flow of TMGa is 40mL/min ~ 60mL/min, NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min; Cp
2the flow of Mg is 600mL/min ~ 700mL/min; Growth thickness is a P type GaN layer 6 of 50nm ~ 60nm.
S206: temperature is 900 DEG C ~ 950 DEG C, the flow of chamber pressure to be the flow of 150mbar ~ 250mbar, TMGa be 30mL/min ~ 45mL/min, TMAl is 50mL/min ~ 80mL/min, NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min; Cp
2the flow of Mg is 700mL/min ~ 800mL/min; Continue duration 120s ~ 200s, growth thickness is the P type AlGaN electronic barrier layer 7 (being called for short PAlGaN in embodiment) of 30nm ~ 40nm.
S207: grow the P type superlattice 9 be made up of PInGaN potential well layer 91 and PAlGaN barrier layer 92 periodicity intermeshing.Preferred employing following steps:
Carry out the following operation in 2 ~ 4 cycles:
S2071: temperature is 900 DEG C ~ 950 DEG C, the flow of chamber pressure to be the flow of 150mbar ~ 250mbar, TMGa be 30mL/min ~ 45mL/min, TMIn is 300mL/min ~ 450mL/min, NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min, Cp
2the flow of Mg is 700mL/min ~ 800mL/min; Continue duration 10s ~ 20s, growth thickness is the PInGaN potential well layer 91 of 3nm ~ 5nm.
S2072: temperature is 900 DEG C ~ 950 DEG C, the flow of chamber pressure to be the flow of 150mbar ~ 250mbar, TMGa be 30mL/min ~ 45mL/min, TMAl is 60mL/min ~ 80mL/min, NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min, Cp
2the flow of Mg is 700mL/min ~ 800mL/min; Continue duration 10s ~ 20s, growth thickness is the PAlGaN barrier layer 92 of 3nm ~ 5nm.
S208: temperature is 1050 DEG C ~ 1100 DEG C, the flow of TMGa is 55mL/min ~ 70mL/min, NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min, Cp
2the flow of Mg is 400mL/min ~ 750mL/min, and growth thickness is the 2nd P type GaN layer 8 of 200nm ~ 250nm.
S3: the N product that above-mentioned steps obtains being placed in 650 DEG C ~ 700 DEG C
2anneal under atmosphere 15min ~ 20min, obtained LED epitaxial structure of the present invention.
The preparation method of the LED epitaxial structure of following comparative example, comprises above-mentioned step S1, step S201 to step S206, step S208 and step S3, but does not comprise step S207.Further, in comparative example, the thickness range of the P type AlGaN electronic barrier layer 7 (being called for short PAlGaN in comparative example) prepared in step S206 is 50nm ~ 60nm.
Embodiment 1 and comparative example 1:
The step S206 of embodiment 1 and the technological parameter of step S207, and the technological parameter of the step S206 of comparative example 1 is as shown in table 1.And in embodiment 1 thickness of PAlGaN (P type AlGaN electronic barrier layer 7) of growth be 30nm, P type superlattice 9 by the thickness in 2 cycles to be the PInGaN potential well layer 91 of 5nm and thickness be 5nm PAlGaN barrier layer 92 periodically intermeshing form.In comparative example 1, the thickness of the PAlGaN (P type AlGaN electronic barrier layer 7) of growth is 50nm.
The step S206 of table 1 embodiment 1 and step S207, and the technological parameter of the step S206 of comparative example 1
In table 1, each source gas is all pass into simultaneously, does not pass into without when representing growth.
Embodiment 1 and comparative example 1 are obtained epitaxial wafer carries out C-V test respectively, obtains the P layer hole concentration distribution map of epitaxial wafer as shown in Figure 4.2 kinds of epitaxial wafers are made respectively the chip of 10mil*23mil, 45mil*45mil size in same chip technology, the electrical parameter of detection chip under identical testing environment, test condition: 10mil*23mil chip is measured under 20mA, 45mil*45mil measures under 350mA, obtains the test result as shown in Fig. 5 (10mil*23mil size), Fig. 6 (45mil*45mil size).
Can be obtained by Fig. 4, Fig. 5, Fig. 6 analysis:
1, ECV test result (Fig. 4) draws, when etching depth h=0.2 μm, in the epitaxial wafer of embodiment 1, the position at PAlGaN (P type AlGaN electronic barrier layer 7) and P type superlattice 9 place, hole concentration value reaches maximum, raising 4 ~ 5 times on PAlGaN (P type AlGaN electronic barrier layer 7) hole concentration value basis, place in the epitaxial wafer of comparative example 1.In the epitaxial wafer of simultaneously embodiment 1, the hole concentration at HTP and LTP place is also subject to aforementioned affect and increases.
2, chip electric parameter detecting result (Fig. 5, Fig. 6) draws, the LED chip brightness of 10mil*23mil size: the chip brightness lifting 5 ~ 8% that the chip that embodiment 1 obtains is obtained compared with comparative example 1; The LED chip brightness of 45mil*45mil size: the chip lifting 8 ~ 10% that the chip that embodiment 1 obtains is obtained compared with comparative example 1.
Embodiment 2 and comparative example 2:
The step S206 of embodiment 2 and the technological parameter of step S207, and the technological parameter of the step S206 of comparative example 2 is as shown in table 2.And in embodiment 2 thickness of PAlGaN (P type AlGaN electronic barrier layer 7) of growth be 32nm, P type superlattice 9 by the thickness in 3 cycles to be the PInGaN potential well layer 91 of 3nm and thickness be 3nm PAlGaN barrier layer 92 periodically intermeshing form.In comparative example 2, the thickness of the PAlGaN (P type AlGaN electronic barrier layer 7) of growth is 50nm.
The step S206 of table 2 embodiment 2 and step S207, and the technological parameter of the step S206 of comparative example 2
In table 2: each source gas is all pass into simultaneously, do not pass into without when representing growth.
By embodiment 2 and comparative example 2 so obtained that epitaxial wafer to make the chip of 10mil*23mil, 45mil*45mil size respectively in same chip technology, the electrical parameter of detection chip under identical testing environment, test condition: 10mil*23mil chip is measured under 20mA, 45mil*45mil measures under 350mA, obtains the test result as shown in Fig. 7 (10mil*23mil size), Fig. 8 (45mil*45mil size).
Can be obtained by Fig. 7, Fig. 8 analysis:
1, chip electric parameter detecting result (Fig. 7, Fig. 8) draws, the LED chip brightness of 10mil*23mil size: the chip brightness lifting 5 ~ 8% that the chip that embodiment 2 obtains is obtained compared with comparative example 2; The LED chip brightness of 45mil*45mil size: the chip lifting 8 ~ 10% that the chip that embodiment 2 obtains is obtained compared with comparative example 2.
Embodiment 3:
The step S206 of embodiment 3 and the technological parameter of step S207 as shown in table 3.And in embodiment 3 thickness of PAlGaN (P type AlGaN electronic barrier layer 7) of growth be 36nm, P type superlattice 9 by the thickness in 2 cycles to be the PInGaN potential well layer 91 of 4nm and thickness be 4nm PAlGaN barrier layer 92 periodically intermeshing form.
The step S206 of table 3 embodiment 3 and the technological parameter of step S207
In table 3: each source gas is all pass into simultaneously, do not pass into without when representing growth.
Embodiment 4:
The step S206 of embodiment 4 and the technological parameter of step S207 as shown in table 4.And in embodiment 4 thickness of PAlGaN (P type AlGaN electronic barrier layer 7) of growth be 40nm, P type superlattice 9 by the thickness in 4 cycles to be the PInGaN potential well layer 91 of 5nm and thickness be 5nm PAlGaN barrier layer 92 periodically intermeshing form.
The step S206 of table 4 embodiment 4 and the technological parameter of step S207
In table 4: each source gas is all pass into simultaneously, do not pass into without when representing growth.
In above embodiment 1 ~ embodiment 4, comparative example 1, comparative example 2, NM step S1, step S201 are to the growth thickness numerical value of the technological parameter in step S205, step S208 and step S3 and each layer, can in aforesaid number range, adopt existing technological means to adjust arbitrarily according to actual needs, not affect whole structure of the present invention.
Being contrasted with the test result of comparative example 1 and comparative example 2 respectively from embodiment 1, embodiment 2, the LED epitaxial structure with P type superlattice 9 of the present invention, by improving hole concentration, and then improving the brightness 5 ~ 10% of chip.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. one kind has the LED epitaxial structure of P type superlattice, comprise substrate, described substrate is disposed with from the bottom to top GaN resilient coating, layer of undoped gan, n-type GaN layer, multiple quantum well light emitting layer, a P type GaN layer, P type AlGaN electronic barrier layer, the 2nd P type GaN layer, it is characterized in that
The P type superlattice be made up of PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing are provided with between described P type AlGaN electronic barrier layer and described 2nd P type GaN layer;
Described P type superlattice are made up of the PInGaN potential well layer in 2 ~ 4 cycles and PAlGaN barrier layer intermeshing; And the described PInGaN potential well layer of period 1 is overlying on described PAlGaN electronic barrier layer;
The thickness of described P type superlattice is 12nm ~ 40nm;
In described P type superlattice, the thickness of the described PInGaN potential well layer in single cycle is 3nm ~ 5nm; The thickness of the described PAlGaN barrier layer in single cycle is 3nm ~ 5nm;
The thickness of described GaN resilient coating is 20nm ~ 30nm;
The thickness of described layer of undoped gan is 2 μm ~ 2.5 μm;
The thickness of described n-type GaN layer is 2 μm ~ 2.5 μm;
The thickness of described multiple quantum well light emitting layer is 200nm ~ 260nm;
The thickness of a described P type GaN layer is 50nm ~ 60nm;
The thickness of described P type AlGaN electronic barrier layer is 30nm ~ 40nm;
The thickness of described 2nd P type GaN layer is 200nm ~ 250nm;
Described multiple quantum well light emitting layer is superposed alternately by the InGaN potential well layer in 15 ~ 16 cycles and GaN barrier layer and forms;
In described multiple quantum well light emitting layer: the thickness of the described InGaN potential well layer in single cycle is 2.5nm ~ 3nm; The thickness of the described GaN barrier layer in single cycle is 12nm ~ 13nm;
A described P type GaN layer is the P type GaN layer generated under 800 DEG C ~ 850 DEG C temperature conditions; Described 2nd P type GaN layer is the P type GaN layer generated under 1050 DEG C ~ 1100 DEG C temperature conditions.
2. LED epitaxial structure according to claim 1, is characterized in that, described multiple quantum well light emitting layer is superposed alternately by the InGaN potential well layer in 15 ~ 16 cycles and GaN barrier layer and forms;
In described multiple quantum well light emitting layer: the thickness of the described InGaN potential well layer in single cycle is 2.5nm ~ 3nm; The thickness of the described GaN barrier layer in single cycle is 12nm ~ 13nm.
3. LED epitaxial structure according to claim 2, is characterized in that, a described P type GaN layer is the P type GaN layer generated under 800 DEG C ~ 850 DEG C temperature conditions; Described 2nd P type GaN layer is the P type GaN layer generated under 1050 DEG C ~ 1100 DEG C temperature conditions.
4. there is a preparation method for the LED epitaxial structure of P type superlattice, it is characterized in that, comprise the following steps:
S1: select substrate;
S2: be Ga source with TMGa, being Al source with TMAl, is In source with TMIn, with NH
3for N source, carry out following steps successively over the substrate:
S201: growing GaN resilient coating;
S202: growth layer of undoped gan;
S203: growing n-type GaN layer;
S204: growth multiple quantum well light emitting layer;
S205: growth the one P type GaN layer;
S206: growing P-type AlGaN electronic barrier layer;
It is characterized in that, in described step S2, after completing described S206, further comprising the steps of:
S207: grow the P type superlattice be made up of PInGaN potential well layer and PAlGaN barrier layer periodicity intermeshing;
S208: growth the 2nd P type GaN layer;
Described step S204 comprises the following steps:
Carry out the following operation in 13 ~ 15 cycles:
S2041: growth thickness is the InGaN potential well layer of 2.5nm ~ 3nm;
S2042: growth thickness is the GaN barrier layer of 12nm ~ 13nm;
Described step S207 comprises the following steps:
Carry out the following operation in 2 ~ 4 cycles:
S2071: growth thickness is the PInGaN potential well layer of 3nm ~ 5nm;
S2072: growth thickness is the PAlGaN barrier layer of 3nm ~ 5nm;
The technological parameter of each step of described preparation method is as follows:
In described step S201, under temperature is 530 DEG C ~ 570 DEG C conditions, the flow of described TMGa is 55mL/min ~ 75mL/min, described NH
3flow be 1.1 × 10
4mL/min ~ 1.3 × 10
4under the process conditions of mL/min, growth thickness is the GaN resilient coating of 20nm ~ 30nm; Then be warming up to 1030 DEG C ~ 1100 DEG C, and keep 180s ~ 210s, make described GaN resilient coating recrystallization;
In described step S202, temperature is 1000 DEG C ~ 1250 DEG C, and the flow of described TMGa is 180mL/min ~ 210mL/min, described NH
3flow be 2.1 × 10
4mL/min ~ 2.4 × 10
4mL/min; Growth thickness is 2 μm ~ 2.5 μm;
In described step S203, temperature is 1000 DEG C ~ 1250 DEG C, and the flow of described TMGa is 200mL/min ~ 250mL/min, described NH
3flow be 2.5 × 10
4mL/min ~ 3 × 10
4mL/min, SiH
4flow be 14mL/min ~ 18mL/min; Growth thickness is 2 μm ~ 2.5 μm;
In step S2041, temperature is 730 DEG C ~ 800 DEG C, and the flow of described TMGa is 10mL/min ~ 15mL/min, and the flow of described TMIn is 650mL/min ~ 750mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min;
In step S2042, temperature is 730 DEG C ~ 800 DEG C, and the flow of described TMGa is 10mL/min ~ 15mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min;
In described step S205, temperature is 800 DEG C ~ 850 DEG C, and the flow of described TMGa is 40mL/min ~ 60mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min; Cp
2the flow of Mg is 600mL/min ~ 700mL/min; Growth thickness is 50nm ~ 60nm;
In described step S206, temperature is 900 DEG C ~ 950 DEG C, and chamber pressure is 150mbar ~ 250mbar, and the flow of described TMGa is 30mL/min ~ 45mL/min, and the flow of described TMAl is 50mL/min ~ 80mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min; Cp
2the flow of Mg is 700mL/min ~ 800mL/min; Growth thickness is 30nm ~ 40nm;
In described step S2071, temperature is 900 DEG C ~ 950 DEG C, and chamber pressure is 150mbar ~ 250mbar, and the flow of described TMGa is 30mL/min ~ 45mL/min, and the flow of described TMIn is 300mL/min ~ 450mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min, Cp
2the flow of Mg is 700mL/min ~ 800mL/min;
In described step S2072, temperature is 900 DEG C ~ 950 DEG C, and chamber pressure is 150mbar ~ 250mbar, and the flow of described TMGa is 30mL/min ~ 45mL/min, and the flow of described TMAl is 60mL/min ~ 80mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min, Cp
2the flow of Mg is 700mL/min ~ 800mL/min;
In described step S208, temperature is 1050 DEG C ~ 1100 DEG C, and the flow of described TMGa is 55mL/min ~ 70mL/min, described NH
3flow be 3 × 10
4mL/min ~ 3.3 × 10
4mL/min, Cp
2the flow of Mg is 400mL/min ~ 750mL/min, and growth thickness is 200nm ~ 250nm.
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| CN103367581A (en) * | 2013-07-26 | 2013-10-23 | 东南大学 | Light emitting diode with electronic barrier layer structure |
| CN104716237B (en) * | 2013-12-17 | 2017-08-04 | 比亚迪股份有限公司 | A kind of GaN base LED and preparation method thereof |
| CN103824917B (en) * | 2014-02-25 | 2017-01-18 | 圆融光电科技有限公司 | LED manufacturing method, LED and chip |
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| CN103972335A (en) * | 2014-05-26 | 2014-08-06 | 湘能华磊光电股份有限公司 | Light-emitting diode (LED) epitaxial layer structure and LED chip with same |
| CN103996769B (en) * | 2014-06-06 | 2017-07-07 | 湘能华磊光电股份有限公司 | LED epitaxial layer structures, growing method and the LED chip with the structure |
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| CN104064643B (en) * | 2014-06-24 | 2017-01-11 | 湘能华磊光电股份有限公司 | P-type epitaxial layer of LED, manufacturing method thereof and LED epitaxial wafer comprising thereof |
| CN105304779A (en) * | 2014-07-31 | 2016-02-03 | 惠州比亚迪实业有限公司 | GaN-based LED structure and formation method thereof |
| CN104134730B (en) * | 2014-08-19 | 2017-03-08 | 湘能华磊光电股份有限公司 | The epitaxial wafer of Mg doping electronic barrier layer, growing method and LED structure |
| CN104900776A (en) * | 2015-06-29 | 2015-09-09 | 聚灿光电科技股份有限公司 | Light emitting diode (LED) epitaxial structure and preparation method therefor |
| CN106486573A (en) * | 2015-08-28 | 2017-03-08 | 南通同方半导体有限公司 | A kind of LED epitaxial structure of high hole injection efficiency |
| CN105206717B (en) * | 2015-09-18 | 2018-10-23 | 华灿光电股份有限公司 | GaN base light emitting epitaxial wafer and preparation method thereof |
| CN105355735B (en) * | 2015-11-03 | 2017-08-29 | 湘能华磊光电股份有限公司 | A kind of epitaxial growth method of reduction LED contact resistances |
| CN105870266B (en) * | 2016-04-27 | 2018-09-18 | 湘能华磊光电股份有限公司 | The growing method of electron barrier layer structure and LED epitaxial structure containing this structure |
| CN106206880B (en) * | 2016-08-31 | 2018-08-31 | 中联西北工程设计研究院有限公司 | A method of preparing InGaN/AlGaN MQW purple LEDs |
| CN108666398A (en) * | 2017-03-28 | 2018-10-16 | 山东浪潮华光光电子股份有限公司 | A kind of LED epitaxial structure and its growing method |
| CN107799633A (en) * | 2017-09-19 | 2018-03-13 | 华灿光电（浙江）有限公司 | Light emitting diode epitaxial wafer and manufacturing method thereof |
| CN109346574B (en) * | 2018-09-03 | 2020-02-21 | 淮安澳洋顺昌光电技术有限公司 | Epitaxial wafer for improving brightness of gallium nitride-based LED and growth method |
| CN109830579B (en) * | 2018-12-28 | 2020-09-15 | 南京邮电大学 | Suspended green light LED monolithic integrated device and preparation method thereof |
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