CN103633214B - InGaN/GaN superlattice buffer layer structure, preparation method of InGaN/GaN superlattice buffer layer structure, and LED chip comprising InGaN/GaN superlattice buffer layer structure - Google Patents
InGaN/GaN superlattice buffer layer structure, preparation method of InGaN/GaN superlattice buffer layer structure, and LED chip comprising InGaN/GaN superlattice buffer layer structure Download PDFInfo
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Abstract
The invention provides an InGaN/GaN superlattice buffer layer structure, a preparation method of the InGaN/GaN superlattice buffer layer structure, and an LED chip comprising the InGaN/GaN superlattice buffer layer structure. The InGaN/GaN superlattice buffer layer structure comprises a shallow quantum well layer, an MQW layer and a superlattice buffer layer disposed between the shallow quantum well layer and the MQW layer. The superlattice buffer layer comprises a plurality of buffer layer units stacked in order. Each buffer layer unit comprises an InGaN layer and a plurality of doped layers. Each doped layer comprises a uGaN layer and an nGaN layer which are stacked in order. Each doped layer is arranged on the corresponding InGaN layer. The InGaN/GaN superlattice buffer layer structure has the advantages that the quality of active region crystal of the LED chip can be improved, active region lattice mismatch and thermal stress mismatch are reduced, electron leakage is reduced effectively, carriers and holes can be recombined more efficiently, and luminous efficiency of devices is improved.
Description
Technical field
The present invention relates to MQW especially, relate to a kind of InGaN/GaN super-lattice buffer layer and preparation method thereof.The present invention
Another aspect additionally provide a kind of LED chip containing this structure.
Background technology
Existing LED chip mostly is direct growth MQW (MQW) layer on shallow quantum well layer, and mqw layer includes successively
Stacked well layer and barrier layer, but owing to LED chip has started at Grown multilamellar from substrate, all can during every layer growth
Producing stress with preceding layer, the shallow quantum well layer stress causing growth is relatively big, if directly growing mqw layer on shallow quantum well layer,
Thermal stress mismatch and the crystal mass that can form MQW active area reduce, and increase the V-type of elongation growth on mqw layer and lack
Fall into quantity, add electronics and reveal, be unfavorable for electric current uniform expansion in mqw layer, increase current crowding phenomenon, these
Unfavorable factor finally have impact on the radiation recombination in effective electron and hole, thus reduces the luminous efficiency of LED chip.
Summary of the invention
Present invention aim at providing a kind of InGaN/GaN super-lattice buffer layer, preparation method and the LED chip containing this structure,
To solve that LED chip luminous efficiency in prior art is low, in LED chip, mqw layer stress is excessive, and in mqw layer, crystal lacks
Fall into many technical problems.
For achieving the above object, according to an aspect of the invention, it is provided a kind of InGaN/GaN superlattice buffer layer structure,
Including shallow quantum well layer and mqw layer, including the super-lattice buffer layer being arranged between shallow quantum well layer and mqw layer；Super brilliant
Lattice cushion includes multiple cushion unit being sequentially stacked, and wherein, each cushion unit includes: InGaN layer and multiple
Doped layer；Doped layer includes uGaN layer and the nGaN layer being sequentially stacked, and is arranged in InGaN layer.
Further, cushion unit is 6～20；Doped layer is 2～5.
Further, InGaN layer thickness is 0.5～3nm；The thickness of uGaN layer and nGaN layer is than for 1:1～3.
Further, the thickness of uGaN layer is 0.5～2nm, and the thickness of nGaN layer is 0.5～2nm.
Additionally provide the preparation method of a kind of above-mentioned InGaN/GaN superlattice buffer layer structure according to a further aspect in the invention, its
It is characterised by, comprises the following steps:
S1: grow InGaN layer on shallow quantum well layer；
S2: grow multi-doped layers in InGaN layer；
S3: grow InGaN layer on doped layer；
Repeatedly S2～S3 step obtains multiple cushion unit, grows mqw layer on cushion unit.
Further, the growth temperature of InGaN layer is higher than the growth temperature 20 of the well layer in mqw layer～80 DEG C, and doped layer grows
Temperature is identical with the growth temperature of barrier layer in mqw layer.
Further, InGaN layer growth temperature is higher than the growth temperature 30 of the well layer in mqw layer～60 DEG C.
Additionally provide a kind of LED chip according to a further aspect in the invention, including substrate and the N-type being sequentially formed on substrate
GaN layer, shallow quantum well layer, mqw layer, p-type GaN layer, be further provided with between shallow quantum well layer and mqw layer
The super-lattice buffer layer stated.
Further, a GaN cushion, the uGaN layer being sequentially stacked between substrate and N-type GaN layer is also included
With the 2nd uGaN layer；Also include being sequentially stacked the electronic barrier layer between N-type GaN layer and shallow quantum well layer and n-type doping
GaN layer.
Further, the first doped p-type GaN layer being sequentially stacked between mqw layer and p-type GaN layer is also included；Also wrap
Include the second doped p-type GaN layer and p-type contact layer being sequentially formed in p-type GaN layer.
The method have the advantages that
The InGaN/GaN superlattice buffer layer structure that the present invention provides can improve the LED chip active area crystal matter with this structure
Amount, reduces active area lattice mismatch and thermal stress mismatch, effectively reduces electronics and reveals, increases the combined efficiency of carrier and hole,
Improve the luminous efficiency of device.
In addition to objects, features and advantages described above, the present invention also has other objects, features and advantages.Below
Will be with reference to figure, the present invention is further detailed explanation.
Accompanying drawing explanation
The accompanying drawing of the part constituting the application is used for providing a further understanding of the present invention, the illustrative examples of the present invention and
Its explanation is used for explaining the present invention, is not intended that inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the structural representation of the preferred embodiment of the present invention；
Fig. 2 is the structural representation of the present invention preferably another embodiment；
Fig. 3 is the structural representation of the present invention preferably another embodiment；And
Fig. 4 is brightness (the LOP)-core particles number curve chart of the preferred embodiment of the present invention and comparative example.
Marginal data:
1, substrate；2, a GaN cushion；3, a uGaN layer；4, the 2nd uGaN layer；5, N-type GaN layer；
6, electronic barrier layer；7, n-type doping GaN layer；8, shallow quantum well layer；9, InGaN layer；10, uGaN layer；11、nGaN
Layer；12, mqw layer；13, the first doped p-type GaN layer；14, p-type GaN layer；15, the second doped p-type GaN layer；
16, p-type contact layer；110, super-lattice buffer layer.
Detailed description of the invention
Below in conjunction with accompanying drawing, embodiments of the invention are described in detail, but the present invention can be defined by the claims and cover
Multitude of different ways implement.
The InGaN/GaN superlattice buffer layer structure that the present invention provides, by setting between shallow quantum well layer 8 and mqw layer 12
Put super-lattice buffer layer 110, be effectively improved active area crystal mass, reduce active area lattice mismatch and thermal stress mismatch, effectively subtract
Few electronics is revealed, and increases the combined efficiency of carrier and hole, improves the luminous efficiency of device.
InGaN/GaN superlattice buffer layer structure includes shallow quantum well layer 8, super-lattice buffer layer 110 and mqw layer 12, super
Buffer layer lattice 110 includes multiple cushion unit being sequentially stacked；Each cushion unit includes InGaN layer 9 and is grown on
Multiple doped layers being sequentially stacked on InGaN layer 9 top, doped layer includes uGaN layer 10 He being formed in InGaN layer 9
The nGaN layer 11 being formed on uGaN layer 10.
Herein multiple refer at least 2.The super-lattice buffer layer 110 that the present invention provides is made up of multiple cushion unit,
Each cushion unit includes InGaN layer 9 and the multiple doped layers being sequentially stacked being formed on this InGaN layer 9 end face, should
Doped layer includes the uGaN layer 10 being formed in InGaN layer 9 and the nGaN layer 11 being formed on uGaN layer 10.Use
There is the most aggregated before the super-lattice buffer layer 110 of this structure can buffer growth mqw layer 12 being formed on shallow quantum well layer 8
Stress.Arrange super-lattice buffer layer 110 for 12 times at mqw layer can the skew that occur due to electronics and hole be reduced simultaneously,
Hole and electronics and recombination rate are provided, thus reduce piezoelectricity and spontaneous polarization, improve luminous efficiency.Superlattices are set simultaneously
The V-type groove defect that shallow quantum well layer 8 is formed when adulterating In can also be weakened by cushion 110.
It is preferably provided with 6～20 cushion unit.Cushion unit growth cycle is very few, it is impossible to play on the shallow quantum well layer 8 of elimination
Stress, cover V-type defect, improve the effect of current expansion.If it is long to spend the production cycle at most, it is unfavorable for industrial applicability.
Being preferably provided with 2～5 doped layers, uGaN/nGaN repeated growth obtains superlattice structure, and this superlattice structure can make entrance
The continuous current of device is evenly distributed at device, reduces and excessively concentrates the resistance heat caused due to electric current, thus will enter device
Electric current is farthest converted to luminous energy, thus improves the extension of electric current, reduces electric current current crowding in the devices, finally real
Now improve the purpose of brightness (LOP).
The thickness of InGaN layer 9 is 0.5～3nm, is avoided that the doping In bad effect to crystal in this range, makes obtained
Crystal properties is optimum.InGaN layer 9 thickness is too small, then cannot play the effect of super-lattice buffer layer 110.UGaN layer 10
With the thickness of nGaN layer 11 than for 1:1～3.Uniform electric current can be formed in super-lattice buffer layer 110 in the growth of this ratio
Extension layer, thus the extension effect that the realization of optimum is to entrance device current, the gathering reducing electric current to greatest extent improves luminescence
Efficiency.The thickness of monolayer uGaN layer 10 and monolayer nGaN layer 11 is respectively 0.5～2nm.Both can guarantee that super-lattice buffer layer 110
Play and eliminate stress, reduce the effect of defect, make obtained device reach high-high brightness.
Another aspect of the present invention additionally provides the growing method of above-mentioned super-lattice buffer layer 110.Comprise the following steps:
S1: grow InGaN layer 9 on shallow quantum well layer 8；
S2: grow multi-doped layers in InGaN layer 9；
S3: grow InGaN layer 9 on doped layer；
Repeatedly S2～S3 step obtains multiple cushion unit, grows mqw layer 12 on cushion unit.By this step
Growth can obtain the LED chip with aforementioned superlattice structure.In S1 step, shallow quantum well layer 8 is grown on conventional LED chips
On the equivalent layer of structure, can be but be not limited in N-type GaN layer.
The growth temperature of InGaN layer 9 is preferably 30～60 DEG C higher than the growth temperature 20 of described mqw layer 12～80 DEG C.Now
Crystal defect on the boundary layer of obtained super-lattice buffer layer 110 both sides is few, and crystal unit arrangement is neat, and space is few, and quality is preferable,
Defect is few.Stress and the defect thereon that can be assembled by shallow quantum well layer 8 separate with mqw layer 12, are affected and are preferably minimized.
InGaN layer 9 and mqw layer 12 excessive temperature differentials in super-lattice buffer layer 110 simultaneously, can increase super-lattice buffer layer 110 with
Mqw layer 12 connects the deformational stress on interface, affects the performance of device.
uGaN layer 10 is adulterated Si, and concentration can set according to a conventional method, and preferred concentration is 1 × 1017～1.01 × 1018atom/cm3。
Another aspect of the present invention additionally provides the LED chip with this InGaN/GaN superlattice buffer layer structure, sees Fig. 1,
This chip includes the substrate 1 being sequentially stacked, the N-type GaN layer 5 being formed on substrate 1 end face, is formed at N-type GaN layer 5
Shallow quantum well layer 8 on end face, mqw layer 12 and the p-type GaN layer 14 being formed on mqw layer 12 end face, superlattices
Cushion 110 is formed between shallow quantum well layer 8 and mqw layer 12.Arrange by this structure and the super of present invention offer can be provided
The effect of buffer layer lattice.
Further, see Fig. 2, have the LED chip of this InGaN/GaN superlattice buffer layer structure can include substrate 1,
The uGaN layer be formed at the GaN cushion 2 on substrate 1 end face, being formed on GaN cushion 2 end face
3, N-type GaN be formed at the 2nd uGaN layer 4 on uGaN layer 3 end face, being formed on the 2nd uGaN layer 4 end face
Layer 5, the electronic barrier layer 6 that is formed on N-type GaN layer 5 end face, the n-type doping that is formed on electronic barrier layer 6 end face
GaN layer 7, the shallow quantum well layer 8 being formed on n-type doping GaN layer 7 end face, be formed on shallow quantum well layer 8 end face super
Buffer layer lattice 110, the mqw layer 12 being formed on super-lattice buffer layer 110 end face and be formed on mqw layer 12 end face
P-type GaN layer 14.
Further, see Fig. 3, have the LED chip of this InGaN/GaN superlattice buffer layer structure can include substrate 1,
The uGaN layer be formed at the GaN cushion 2 on substrate 1 end face, being formed on GaN cushion 2 end face
3, N-type GaN be formed at the 2nd uGaN layer 4 on uGaN layer 3 end face, being formed on the 2nd uGaN layer 4 end face
Layer 5, the electronic barrier layer 6 that is formed on N-type GaN layer 5 end face, the n-type doping that is formed on electronic barrier layer 6 end face
GaN layer 7, the shallow quantum well layer 8 being formed on n-type doping GaN layer 7 end face, be formed on shallow quantum well layer 8 end face super
Buffer layer lattice 110, the mqw layer 12 being formed on super-lattice buffer layer 110 end face and be formed on mqw layer 12 end face
The first doped p-type GaN layer 13, the p-type GaN layer 14 being formed on the first doped p-type GaN layer 13 end face, formed
The second doped p-type GaN layer 15 on p-type GaN layer 14 end face and being formed on the second doped p-type GaN layer 15 end face
P-type contact layer 16.
Embodiment
In following example, material used and instrument are commercially available, and wherein instrument is that AixtronCriusIIMOCVD (is purchased from
AixtronCrius company).
Embodiment 1
Structure sees Fig. 3.
1, Sapphire Substrate 1 is positioned in MOCVD reative cell, at 900～1100 DEG C, uses H2、NH3High Deng gas
Temperature processes 4～10 minutes Sapphire Substrate 1；
2, treating Chu Liwan, reative cell is cooled to 500～550 DEG C, is passed through TMGa and NH3, pressure is 300～900mbar,
In Sapphire Substrate 1, growth thickness is 20～50nm thick low temperature the oneth GaN cushion 2 (Nucleation)；
3, grow a GaN cushion 2, then rise temperature to 950～1050 DEG C, high annealing 60～300s, on substrate 1
Form GaN nucleus；
4, high annealing is complete, and temperature is adjusted to 960～1020 DEG C, is passed through TMGa and NH3, Stress control 300～900mbar,
On a GaN cushion 2, growth thickness is high temperature undoped the oneth uGaN layer 3 of 0.8～1.2um；
5,1020～1080 DEG C it are warming up to again, pressure 300～900mbar, growth thickness 2～3um on a uGaN layer 3
High temperature undoped the 2nd uGaN layer 4；
6, after the 2nd uGaN layer 4 growth terminates, then homoiothermic is to 1020～1080 DEG C, is passed through TMGa and NH3, SiH4,
On 2nd uGaN layer 4 growth thickness be 2～3um mix Si N-type GaN layer 5；
7, after N-type GaN layer 5 growth terminates, growing one layer of N-shaped current extending (n-AlGaN), temperature is adjusted to 1020-1080 DEG C,
Being passed through TMGa and NH3, TMAl, TMGa, Stress control is at 100mbar-400mbar, and growth 5-30nm is thick, as electricity
Sub-barrier layer 6；
8, after electronic barrier layer 6 growth terminates, one layer 300～500nm low-mix n-GaN of regrowth is as n-type doping GaN layer
7；
9, after the growth of low-mix n-GaN n-type doping GaN layer 7 terminates, 2～5 shallow quantum well layers of InGaN/GaN 8 are grown,
Pressure is 300～400mbar, and In is mixed in 800 DEG C of growths of low temperaturexGa(1-x)N/GaN layer, InxGa(1-x)N thickness is 1～10nm, GaN
Thickness is 20～50nm；
10, after the growth of shallow quantum well layer 8 terminates, super-lattice buffer layer 110 is grown.Use and grow higher than mqw layer 12 of having chance with
The temperature conditions growth InGaN layer 9 that temperature is 20 DEG C, thickness is 0.5nm；Use the temperature conditions growth doping of mqw layer 12
Layer, doped layer includes uGaN layer 10 and nGaN layer 11.Doped layer is repeated growth 2 cycle in InGaN layer 9, as super
One growth cycle of buffer layer lattice 110, super-lattice buffer layer 110 growth cycle number is 6；
Doped layer uses the growth pattern of uGaN/nGaN, and uGaN layer 10 is undoped GaN, and nGaN layer 11 is doping N
Type GaN.NGaN layer 11 adulterates Si, and doping content is 1 × 1017～1.01 × 1018atom/cm3；
UGaN layer 10 and nGaN layer 11 thickness are 0.5～2nm than for 1:1～3, uGaN layer 10 and nGaN layer 11 thickness in monolayer；
11, after super-lattice buffer layer 110 growth terminates, cyclical growth is had chance with mqw layer 12；Pressure is
300～400mbar, 750 DEG C of growths 2～3nmInxGa(1-x)The well layer of N, grows 11～13nmGaN barrier layer at 850 DEG C.InxGa(1-x)
N/GaN periodicity is 9～15；
12, after having the growth of edge layer MWQ12, regrowth the first doped p-type GaN layer 13；Temperature is 740～800 DEG C,
It is passed through TMGa, NH3And Cp2Mg, pressure is 200～400mbar, and growth thickness is 20～30nm；
13, after the first doped p-type GaN layer 13 growth, one layer of p-type AlGaN of regrowth is as p-type GaN layer 14；
Temperature is 780～850 DEG C, is passed through TMGa, NH3、Cp2Mg and TMAl, pressure is 200～400mbar, and growth thickness is about
30～40nm；
14, after p-type GaN layer 14 growth, one layer of p-GaN of regrowth is as the second doped p-type GaN layer 15；Temperature
It is 910～950 DEG C, is passed through TMGa, NH3And Cp2Mg, growth pressure is 200～400mbar, and growth gross thickness is about
100～200nm；
15, after the second doped p-type GaN layer 15 growth, one layer of contact layer (contact) of regrowth is as p-type contact layer
16；Temperature is adjusted to 650～680 DEG C, is passed through TMGa, NH3、Cp2Mg and TMIn, growth pressure is 300～500mbar,
The p-type contact layer 16 of growth 5～10nm；
16, after p-type contact layer 16 growth, 700～750 DEG C are reduced the temperature to, in a nitrogen atmosphere, the persistent period 20～30
Minute, activate PGaN.
Embodiment 2
Structure sees Fig. 3.
1, Sapphire Substrate 1 is positioned in MOCVD reative cell, at 900～1100 DEG C, uses H2、NH3High Deng gas
Temperature processes 4～10 minutes Sapphire Substrate 1；
2, treating Chu Liwan, reative cell is cooled to 500～550 DEG C, is passed through TMGa and NH3, pressure is 300～900mbar,
In Sapphire Substrate 1, growth thickness is 20～50nm thick low temperature the oneth GaN cushion 2 (Nucleation)；
3, grow a GaN cushion 2, then rise temperature to 950～1050 DEG C, high annealing 60～300s, on substrate 1
Form GaN nucleus；
4, high annealing is complete, and temperature is adjusted to 960～1020 DEG C, is passed through TMGa and NH3, Stress control 300～900mbar,
On a GaN cushion 2, growth thickness is high temperature undoped the oneth uGaN layer 3 of 0.8～1.2um；
5,1020～1080 DEG C it are warming up to again, pressure 300～900mbar, growth thickness 2～3um in the second buffer gan layer 3
High temperature undoped the 2nd uGaN layer 4；
6, after the 2nd uGaN layer 4 growth terminates, then homoiothermic is to 1020～1080 DEG C, is passed through TMGa and NH3, SiH4,
On 2nd uGaN layer 4 growth thickness be 2～3um mix Si N-type GaN layer 5；
7, after N-type GaN layer 5 growth terminates, growing one layer of N-shaped current extending (n-AlGaN), temperature is adjusted to 1020-1080 DEG C,
Being passed through TMGa and NH3, TMAl, TMGa, Stress control is at 100mbar-400mbar, and growth 5-30nm is thick, as electricity
Sub-barrier layer 6；
8, after electronic barrier layer 6 growth terminates, one layer 300～500nm low-mix n-GaN of regrowth is as n-type doping GaN layer
7；
9, after the growth of low-mix n-GaNN type doped gan layer 7 terminates, 2～5 shallow quantum well layers of InGaN/GaN 8 are grown,
Pressure is 300～400mbar, and In is mixed in 800 DEG C of growths of low temperaturexGa(1-x)N/GaN layer, NxGa(1-x)N thickness is 1～10nm, GaN
Thickness is 20～50nm；
10, after the growth of shallow quantum well layer 8 terminates, super-lattice buffer layer 110 is grown.Use and grow higher than mqw layer 12 of having chance with
The temperature conditions growth InGaN layer 9 that temperature is 80 DEG C, thickness is 3nm；Use the temperature conditions growth doped layer of mqw layer 12,
Doped layer includes uGaN layer 10 and nGaN layer 11.Doped layer is repeated growth 5 cycle in InGaN layer 9, as superlattices
One growth cycle of cushion 110, super-lattice buffer layer 110 growth cycle number is 20；
Doped layer uses the growth pattern of uGaN/nGaN, and uGaN layer 10 is undoped GaN, and nGaN layer 11 is doping N
Type GaN.NGaN layer 11 adulterates Si, and doping content is 1 × 1017～1.01 × 1018atom/cm3；
UGaN layer 10 and nGaN layer 11 thickness are 0.5～2nm than for 1:1～3, uGaN layer 10 and nGaN layer 11 thickness in monolayer；
11, after super-lattice buffer layer 110 growth terminates, cyclical growth has edge layer MQW12；Pressure is 300～400mbar, 750 DEG C
Growth 2～3nmInxGa(1-x)The well layer of N, grows 11～13nmGaN barrier layer at 850 DEG C.InxGa(1-x)N/GaN periodicity is
9～15；
12, after having the growth of edge layer MWQ12, regrowth the first doped p-type GaN layer 13；Temperature is 740～800 DEG C,
It is passed through TMGa, NH3And Cp2Mg, pressure is 200～400mbar, and growth thickness is 20～30nm；
13, after the first doped p-type GaN layer 13 growth, one layer of p-type AlGaN of regrowth is as p-type GaN layer 14；
Temperature is 780～850 DEG C, is passed through TMGa, NH3、Cp2Mg and TMAl, pressure is 200～400mbar, and growth thickness is about
30～40nm；
14, after p-type GaN layer 14 growth, one layer of p-GaN of regrowth is as the second doped p-type GaN layer 15；Temperature
It is 910～950 DEG C, is passed through TMGa, NH3And Cp2Mg, growth pressure is 200～400mbar, and growth gross thickness is about
100～200nm；
15, after the second doped p-type GaN layer 15 growth, one layer of contact layer (contact) of regrowth is as p-type contact layer
16；Temperature is adjusted to 650～680 DEG C, is passed through TMGa, NH3、Cp2Mg and TMIn, growth pressure is 300～500mbar,
The p-type contact layer 16 of growth 5～10nm；
16, after p-type contact layer 16 growth, 700～750 DEG C are reduced the temperature to, in a nitrogen atmosphere, the persistent period 20～30
Minute, activate PGaN.
Embodiment 3
Structure sees Fig. 3.
1, Sapphire Substrate 1 is positioned in MOCVD reative cell, at 900～1100 DEG C, uses H2、NH3High Deng gas
Temperature processes 4～10 minutes Sapphire Substrate 1；
2, treating Chu Liwan, reative cell is cooled to 500～550 DEG C, is passed through TMGa and NH3, pressure is 300～900mbar,
In Sapphire Substrate 1, growth thickness is 20～50nm thick low temperature the oneth GaN cushion 2 (Nucleation)；
3, grow a GaN cushion 2, then rise temperature to 950～1050 DEG C, high annealing 60～300s, on substrate 1
Form GaN nucleus；
4, high annealing is complete, and temperature is adjusted to 960～1020 DEG C, is passed through TMGa and NH3, Stress control 300～900mbar,
On a GaN cushion 2, growth thickness is high temperature undoped second buffer gan layer 3 of 0.8～1.2um；
5,1020～1080 DEG C it are warming up to again, pressure 300～900mbar, growth thickness 2～3um in the second buffer gan layer 3
High temperature undoped the 2nd uGaN layer 4；
6, after the 2nd uGaN layer 4 growth terminates, then homoiothermic is to 1020～1080 DEG C, is passed through TMGa and NH3, SiH4,
On 2nd uGaN layer 4 growth thickness be 2～3um mix Si N-type GaN layer 5；
7, after N-type GaN layer 5 growth terminates, growing one layer of N-shaped current extending (n-AlGaN), temperature is adjusted to 1020-1080 DEG C,
Being passed through TMGa and NH3, TMAl, TMGa, Stress control is at 100mbar-400mbar, and growth 5-30nm is thick, as electricity
Sub-barrier layer 6；
8, after electronic barrier layer 6 growth terminates, one layer 300～500nm low-mix n-GaN of regrowth is as n-type doping GaN layer
7；
9, after the growth of low-mix n-GaNN type doped gan layer 7 terminates, 2～5 shallow quantum well layers of InGaN/GaN 8 are grown,
Pressure is 300～400mbar, and In is mixed in 800 DEG C of growths of low temperaturexGa(1-x)N/GaN layer, InxGa(1-x)N thickness is 1～10nm, GaN
Thickness is 20～50nm；
10, after the growth of shallow quantum well layer 8 terminates, super-lattice buffer layer 110 is grown.Use and grow higher than mqw layer 12 of having chance with
The temperature conditions growth InGaN layer 9 that temperature is 30 DEG C, thickness is 2nm；Use the temperature conditions growth doped layer of mqw layer 12,
Doped layer includes uGaN layer 10 and nGaN layer 11.Doped layer is repeated growth 3 cycle in InGaN layer 9, as superlattices
One growth cycle of cushion 110, super-lattice buffer layer 110 growth cycle number is 10；
Doped layer uses the growth pattern of uGaN/nGaN, and uGaN layer 10 is undoped GaN, and nGaN layer 11 is doping N
Type GaN.NGaN layer 11 adulterates Si, and doping content is 1 × 1017～1.01 × 1018atom/cm3；
UGaN layer 10 and nGaN layer 11 thickness are 0.5～2nm than for 1:1～3, uGaN layer 10 and nGaN layer 11 thickness in monolayer；
11, after super-lattice buffer layer 110 growth terminates, cyclical growth has edge layer MQW12；Pressure is 300～400mbar, 750 DEG C
Growth 2～3nmInxGa(1-x)The well layer of N, grows 11～13nmGaN barrier layer at 850 DEG C.InxGa(1-x)N/GaN periodicity is
9～15；
12, after having the growth of edge layer MWQ12, regrowth the first doped p-type GaN layer 13；Temperature is 740～800 DEG C,
It is passed through TMGa, NH3And Cp2Mg, pressure is 200～400mbar, and growth thickness is 20～30nm；
13, after the first doped p-type GaN layer 13 growth, one layer of p-type AlGaN of regrowth is as p-type GaN layer 14；
Temperature is 780～850C, is passed through TMGa, NH3、Cp2Mg and TMAl, pressure is 200～400mbar, and growth thickness is about
30～40nm；
14, after p-type GaN layer 14 growth, one layer of p-GaN of regrowth is as the second doped p-type GaN layer 15；Temperature
It is 910～950 DEG C, is passed through TMGa, NH3And Cp2Mg, growth pressure is 200～400mbar, and growth gross thickness is about
100～200nm；
15, after the second doped p-type GaN layer 15 growth, one layer of contact layer (contact) of regrowth is as p-type contact layer
16；Temperature is adjusted to 650～680 DEG C, is passed through TMGa, NH3、Cp2Mg and TMIn, growth pressure is 300～500mbar,
The p-type contact layer 16 of growth 5～10nm；
16, after p-type contact layer 16 growth, 700～750 DEG C are reduced the temperature to, in a nitrogen atmosphere, the persistent period 20～30
Minute, activate PGaN.
Embodiment 4
Structure sees Fig. 3.
1, Sapphire Substrate 1 is positioned in MOCVD reative cell, at 900～1100 DEG C, uses H2、NH3High Deng gas
Temperature processes 4～10 minutes Sapphire Substrate 1；
2, treating Chu Liwan, reative cell is cooled to 500～550 DEG C, is passed through TMGa and NH3, pressure is 300～900mbar,
In Sapphire Substrate 1, growth thickness is 20～50nm thick low temperature the oneth GaN cushion 2 (Nucleation)；
3, grow a GaN cushion 2, then rise temperature to 950～1050 DEG C, high annealing 60～300s, on substrate 1
Form GaN nucleus；
4, high annealing is complete, and temperature is adjusted to 960～1020 DEG C, is passed through TMGa and NH3, Stress control 300～900mbar,
On a GaN cushion 2, growth thickness is high temperature undoped the oneth uGaN layer 3 of 0.8～1.2um；
5,1020～1080 DEG C it are warming up to again, pressure 300～900mbar, growth thickness 2～3um in the second buffer gan layer 3
High temperature undoped the 2nd uGaN layer 4；
6, after the 2nd uGaN layer 4 growth terminates, then homoiothermic is to 1020～1080 DEG C, is passed through TMGa and NH3, SiH4,
On 2nd uGaN layer 4 growth thickness be 2～3um mix Si N-type GaN layer 5；
7, after N-type GaN layer 5 growth terminates, growing one layer of N-shaped current extending (n-AlGaN), temperature is adjusted to 1020-1080 DEG C,
Being passed through TMGa and NH3, TMAl, TMGa, Stress control is at 100mbar-400mbar, and growth 5-30nm is thick, as electricity
Sub-barrier layer 6；
8, after electronic barrier layer 6 growth terminates, one layer 300～500nm low-mix n-GaN of regrowth is as n-type doping GaN layer
7；
9, after the growth of low-mix n-GaN n-type doping GaN layer 7 terminates, 2～5 shallow quantum well layers of InGaN/GaN 8 are grown,
Pressure is 300～400mbar, and In is mixed in 800 DEG C of growths of low temperaturexGa(1-x)N/GaN layer, InxGa(1-x)N thickness is 1～10nm, GaN
Thickness is 20～50nm；
10, after the growth of shallow quantum well layer 8 terminates, super-lattice buffer layer 110 is grown.Use and grow higher than mqw layer 12 of having chance with
The temperature conditions growth InGaN layer 9 of temperature 60 C, thickness is 2.7nm；Use the temperature conditions growth doping of mqw layer 12
Layer, doped layer includes uGaN layer 10 and nGaN layer 11.Doped layer is repeated growth 4 cycle in InGaN layer 9, as super
One growth cycle of buffer layer lattice 110, super-lattice buffer layer 110 growth cycle number is 15；
Doped layer uses the growth pattern of uGaN/nGaN, and uGaN layer 10 is undoped GaN, and nGaN layer 11 is doping N
Type GaN.NGaN layer 11 adulterates Si, and doping content is 1 × 1017～1.01 × 1018atom/cm3；
UGaN layer 10 and nGaN layer 11 thickness are 0.5～2nm than for 1:1～3, uGaN layer 10 and nGaN layer 11 thickness in monolayer；
11, after super-lattice buffer layer 110 growth terminates, cyclical growth is had chance with mqw layer 12；Pressure is
300～400mbar, 750 DEG C of growths 2～3nmInxGa(1-x)The well layer of N, grows 11～13nmGaN barrier layer at 850 DEG C.InxGa(1-x)
N/GaN periodicity is 9～15；
12, after having the growth of edge layer MWQ12, regrowth the first doped p-type GaN layer 13；Temperature is 740～800 DEG C,
It is passed through TMGa, NH3And Cp2Mg, pressure is 200～400mbar, and growth thickness is 20～30nm；
13, after the first doped p-type GaN layer 13 growth, one layer of p-type AlGaN of regrowth is as p-type GaN layer 14；
Temperature is 780～850 DEG C, is passed through TMGa, NH3、Cp2Mg and TMAl, pressure is 200～400mbar, and growth thickness is about
30～40nm；
14, after p-type GaN layer 14 growth, one layer of p-GaN of regrowth is as the second doped p-type GaN layer 15；Temperature
It is 910～950 DEG C, is passed through TMGa, NH3And Cp2Mg, growth pressure is 200～400mbar, and growth gross thickness is about
100～200nm；
15, after the second doped p-type GaN layer 15 growth, one layer of contact layer (contact) of regrowth is as p-type contact layer
16；Temperature is adjusted to 650～680 DEG C, is passed through TMGa, NH3、Cp2Mg and TMIn, growth pressure is 300～500mbar,
The p-type contact layer 16 of growth 5～10nm；
16, after p-type contact layer 16 growth, 700～750 DEG C are reduced the temperature to, in a nitrogen atmosphere, the persistent period 20～30
Minute, activate PGaN.
Embodiment 5
Structure sees Fig. 3.
1, Sapphire Substrate 1 is positioned in MOCVD reative cell, at 900～1100 DEG C, uses H2、NH3High Deng gas
Temperature processes 4～10 minutes Sapphire Substrate 1；
2, treating Chu Liwan, reative cell is cooled to 500～550 DEG C, is passed through TMGa and NH3, pressure is 300～900mbar,
In Sapphire Substrate 1, growth thickness is 20～50nm thick low temperature the oneth GaN cushion 2 (Nucleation)；
3, grow a GaN cushion 2, then rise temperature to 950～1050 DEG C, high annealing 60～300s, on substrate 1
Form GaN nucleus；
4, high annealing is complete, and temperature is adjusted to 960～1020 DEG C, is passed through TMGa and NH3, Stress control 300～900mbar,
On a GaN cushion 2, growth thickness is high temperature undoped the oneth uGaN layer 3 of 0.8～1.2um；
5,1020～1080 DEG C it are warming up to again, pressure 300～900mbar, growth thickness 2～3um on a uGaN layer 3
High temperature undoped the 2nd uGaN layer 4；
6, after the 2nd uGaN layer 4 growth terminates, then homoiothermic is to 1020～1080 DEG C, is passed through TMGa and NH3, SiH4,
On 2nd uGaN layer 4 growth thickness be 2～3um mix Si N-type GaN layer 5；
7, after N-type GaN layer 5 growth terminates, growing one layer of N-shaped current extending (n-AlGaN), temperature is adjusted to 1020-1080 DEG C,
Being passed through TMGa and NH3, TMAl, TMGa, Stress control is at 100mbar-400mbar, and growth 5-30nm is thick, as electricity
Sub-barrier layer 6；
8, after electronic barrier layer 6 growth terminates, one layer 300～500nm low-mix n-GaN of regrowth is as n-type doping GaN layer
7；
9, after the growth of low-mix n-GaNN type doped gan layer 7 terminates, 2～5 shallow quantum well layers of InGaN/GaN 8 are grown,
Pressure is 300～400mbar, and In is mixed in 800 DEG C of growths of low temperaturexGa(1-x)N/GaN layer, InxGa(1-x)N thickness is 1～10nm, GaN
Thickness is 20～50nm；
10, after the growth of shallow quantum well layer 8 terminates, super-lattice buffer layer 110 is grown.Use and grow higher than mqw layer 12 of having chance with
The temperature conditions growth InGaN layer 9 that temperature is 40 DEG C, thickness is 1.5nm；Use the temperature conditions growth doping of mqw layer 12
Layer, doped layer includes uGaN layer 10 and nGaN layer 11.Doped layer is repeated growth 4 cycle in InGaN layer 9, as super
One growth cycle of buffer layer lattice 110, super-lattice buffer layer 110 growth cycle number is 17；
Doped layer uses the growth pattern of uGaN/nGaN, and uGaN layer 10 is undoped GaN, and nGaN layer 11 is doping N
Type GaN.NGaN layer 11 adulterates Si, and doping content is 1 × 1017～1.01 × 1018atom/cm3；
UGaN layer 10 and nGaN layer 11 thickness are 0.5～2nm than for 1:1～3, uGaN layer 10 and nGaN layer 11 thickness in monolayer；
11, after super-lattice buffer layer 110 growth terminates, cyclical growth is had chance with mqw layer 12；Pressure is
300～400mbar, 750 DEG C of growths 2～3nmInxGa(1-x)The well layer of N, grows 11～13nmGaN barrier layer at 850 DEG C.InxGa(1-x)
N/GaN periodicity is 9～15；
12, after MWQ layer 12 of having chance with growth, regrowth the first doped p-type GaN layer 13；Temperature is 740～800 DEG C,
It is passed through TMGa, NH3And Cp2Mg, pressure is 200～400mbar, and growth thickness is 20～30nm；
13, after the first doped p-type GaN layer 13 growth, one layer of p-type AlGaN of regrowth is as p-type GaN layer 14；
Temperature is 780～850 DEG C, is passed through TMGa, NH3、Cp2Mg and TMAl, pressure is 200～400mbar, and growth thickness is about
30～40nm；
14, after p-type GaN layer 14 growth, one layer of p-GaN of regrowth is as the second doped p-type GaN layer 15；Temperature
It is 910～950 DEG C, is passed through TMGa, NH3And Cp2Mg, growth pressure is 200～400mbar, and growth gross thickness is about
100～200nm；
15, after the second doped p-type GaN layer 15 growth, one layer of contact layer (contact) of regrowth is as p-type contact layer
16；Temperature is adjusted to 650～680 DEG C, is passed through TMGa, NH3、Cp2Mg and TMIn, growth pressure is 300～500mbar,
The p-type contact layer 16 of growth 5～10nm；
16, after p-type contact layer 16 growth, 700～750 DEG C are reduced the temperature to, in a nitrogen atmosphere, the persistent period 20～30
Minute, activate PGaN.
Comparative example 1～5
The most corresponding embodiment 1～5 of comparative example 1～5, differs only in comparative example 1～5 and is not provided with super-lattice buffer layer 110.
Using gained epitaxial wafer in embodiment 1～5 according to a conventional method as LED core particle, multiple LED core particle are measured according to a conventional method
The brightness of each LED core particle, draws as abscissa using core particles number as vertical coordinate obtain Fig. 4 with brightness (LOP), obtain
Curve 1.Gained epitaxial wafer in comparative example 1～5 is prepared LED core particle by with the identical method of embodiment 1～5, and uses phase Tongfang
Method measures brightness, is drawn in Fig. 4 and obtains curve 2.From fig. 4, it can be seen that the LED core particle that the present invention provides is than institute in comparative example
Obtain LED core particle brightness and improve about 5%.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for those skilled in the art
For, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any amendment of being made, etc.
With replacement, improvement etc., should be included within the scope of the present invention.
Claims (10)
1. an InGaN/GaN superlattice buffer layer structure, including shallow quantum well layer (8) and mqw layer (12), its feature exists
In, including the super-lattice buffer layer (110) being arranged between described shallow quantum well layer (8) and mqw layer (12)；Institute
State super-lattice buffer layer (110) and include multiple cushion unit being sequentially stacked, wherein, each described cushion unit bag
Include:
InGaN layer (9) and
Multiple doped layers；Described doped layer includes uGaN layer (10) and the nGaN layer (11) being sequentially stacked, and arranges
In described InGaN layer (9)；Described doped layer is 2～5.
InGaN/GaN superlattice buffer layer structure the most according to claim 1, it is characterised in that described cushion unit is
6～20.
InGaN/GaN superlattice buffer layer structure the most according to claim 2, it is characterised in that described InGaN layer (9)
Thickness is 0.5～3nm；The thickness of described uGaN layer (10) and described nGaN layer (11) ratio is for 1:1～3.
InGaN/GaN superlattice buffer layer structure the most according to claim 3, the thickness of described uGaN layer (10) is
0.5～2nm, the thickness of described nGaN layer (11) is 0.5～2nm.
5. the preparation method of InGaN/GaN superlattice buffer layer structure according to any one of a Claims 1 to 4, it is characterised in that
Comprise the following steps:
S1: described shallow quantum well layer (8) the described InGaN layer of upper growth (9)；
S2: grow multi-doped layers in described InGaN layer (9)；
S3: grow described InGaN layer (9) on described doped layer；
Repeatedly S2～S3 step obtains multiple cushion unit, grows described mqw layer on described cushion unit
(12)。
Preparation method the most according to claim 5, it is characterised in that the growth temperature of described InGaN layer (9) is higher than described
The growth temperature 20 of the well layer in mqw layer (12)～80 DEG C, described doped layer growth temperature and described mqw layer (12)
The growth temperature of middle barrier layer is identical.
Preparation method the most according to claim 6, it is characterised in that described InGaN layer (9) growth temperature is higher than described
The growth temperature 30 of the well layer in mqw layer (12)～60 DEG C.
8. a LED chip, the N-type GaN layer (5) including substrate (1) and being sequentially formed on described substrate (1), shallow
Quantum well layer (8), mqw layer (12), p-type GaN layer (14), it is characterised in that described shallow quantum well layer (8)
And between mqw layer (12), it is further provided with the super-lattice buffer layer (110) according to any one of Claims 1-4.
LED chip the most according to claim 8, it is characterised in that also include being sequentially stacked in described substrate (1) and described
A GaN cushion (2), a uGaN layer (3) and the 2nd uGaN layer (4) between N-type GaN layer (5)；
Also include the electronic barrier layer (6) being sequentially stacked between described N-type GaN layer (5) and described shallow quantum well layer (8)
With n-type doping GaN layer (7).
LED chip the most according to claim 9, it is characterised in that also include being sequentially stacked in described mqw layer (12)
And the first doped p-type GaN layer (13) between described p-type GaN layer (14)；Also include being sequentially formed in described P
The second doped p-type GaN layer (15) in type GaN layer (14) and p-type contact layer (16).
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