CN103001477A - 将双极性结型晶体管用于缓冲电路的方法和缓冲电路 - Google Patents

将双极性结型晶体管用于缓冲电路的方法和缓冲电路 Download PDF

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Publication number
CN103001477A
CN103001477A CN201210338784XA CN201210338784A CN103001477A CN 103001477 A CN103001477 A CN 103001477A CN 201210338784X A CN201210338784X A CN 201210338784XA CN 201210338784 A CN201210338784 A CN 201210338784A CN 103001477 A CN103001477 A CN 103001477A
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buffer circuit
terminal
capacitor
bipolar junction
type transistor
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CN201210338784XA
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CN103001477B (zh
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林国藩
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FSP Technology Inc
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FSP Technology Inc
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Abstract

本发明公开了一种将一双极性结型晶体管用于一缓冲电路的方法和缓冲电路。该缓冲电路包含有：一电容器，该电容器具有一第一端子与一第二端子，其中该电容器的该第一端子是电气连接至该缓冲电路的一第一端子；以及一双极性结型晶体管，其中该双极性结型晶体管的发射极与集电极中的一者是电气连接至该电容器的该第二端子，且其发射极与集电极中的另一者是电气连接至该缓冲电路的一第二端子。该缓冲电路可并联于一主动组件或一负载以保护负载所连接的电路，尤其可吸收主动组件在高频切换时所产生的突波或噪声以做能量回收，而可达到降低突波电压、提高效率的功效。

Description

将双极性结型晶体管用于缓冲电路的方法和缓冲电路
技术领域
本发明是有关于电力／电子组件的保护电路，尤指一种缓冲电路（Snubber Circuit）以及将双极性结型晶体管（Bipolar Junction Transistor，BJT）用于缓冲电路的方法。
背景技术
近年来由于电子电路的技术不断地发展，各种电力／电子组件的保护电路被广泛地实施于诸多应用中。因此，这些保护电路的设计遂成为相当热门的议题。传统的保护电路当中，有某些缓冲电路，其构造简单、易于实施，故被广泛地应用于电力／电子电路。然而，这些传统的缓冲电路还是有不足之处。例如：传统的缓冲电路的能量损耗很高，且其效率通常很差。又例如：传统的缓冲电路无法确保最高突波电压值的限制，也就是说，突波电压值可能超过整体电路所能承受的范围，故采用传统的缓冲电路易造成半导体组件的损坏。因此，需要一种新颖的方法来提升缓冲电路的电路保护的效能。
发明内容
因此本发明的一目的在于提供一种缓冲电路（Snubber Circuit）以及将双极性结型晶体管（Bipolar Junction Transistor，BJT）用于缓冲电路的方法，以解决上述问题。
本发明的一目的在于提供一种缓冲电路以及将双极性结型晶体管用于缓冲电路的方法，以保护负载所连接的电路，且降低突波电压、改善效率。
本发明的较佳实施例中提供一种缓冲电路，该缓冲电路包含有：一电容器，该电容器具有一第一端子与一第二端子，其中该电容器的该第一端子是电气连接至该缓冲电路的一第一端子；以及一双极性结型晶体管（BipolarJunction Transistor,BJT），其中该双极性结型晶体管的发射极（Emitter）与集电极（Collector）中的一者是电气连接至该电容器的该第二端子，且该双极性结型晶体管的发射极与集电极中的另一者是电气连接至该缓冲电路的一第二端子。尤其是，该双极性结型晶体管的基极（Base）与发射极是被导通。
本发明的较佳实施例中提供一种缓冲电路，该缓冲电路包含有：一第一电容器，该第一电容器具有一第一端子与一第二端子，其中该第一电容器的该第一端子是电气连接至该缓冲电路的一第一端子；一电阻器，该电阻器具有一第一端子与一第二端子，其中该电阻器的该第一端子是电气连接至该第一电容器的该第二端子；以及一双极性结型晶体管，其中该双极性结型晶体管的发射极与集电极中的一者是电气连接至该电阻器的该第二端子，且该双极性结型晶体管的发射极与集电极中的另一者是电气连接至该缓冲电路的一第二端子。尤其是，该双极性结型晶体管的基极与发射极是被导通。
本发明于提供上述缓冲电路的同时，亦对应地提供一种将一双极性结型晶体管用于一缓冲电路的方法，该方法包含有下列步骤：将该双极性结型晶体管的基极与发射极导通；以及基于该双极性结型晶体管的基极与集电极之间的至少一接面特性，利用该双极性结型晶体管作为一快速二极管，以供设置于该缓冲电路。尤其是，利用该双极性结型晶体管作为该快速二极管以供设置于该缓冲电路的步骤包含：将该双极性结型晶体管的发射极与集电极中的一者电气连接至一电容器的一端子；将该电容器的另一端子电气连接至该缓冲电路的一第一端子；以及将该双极性结型晶体管的发射极与集电极中的另一者电气连接至该缓冲电路的一第二端子。
本发明的好处之一是，本发明的缓冲电路的构造简单且易于实施，同时能避免相关技术的问题。另外，本发明的缓冲电路可并联于一主动组件或一负载以保护负载所连接的电路，例如可设置于交换式电源供应器中以保护变压器一次侧连接的交换组件或二次侧连接的输出整流电路，尤其可吸收主动组件在高频切换时所产生的突波或噪声以做能量回收，而可降低突波电压、提高效率。
附图说明
图1为依据本发明一第一实施例的一种缓冲电路（Snubber Circuit）的示意图，其中该缓冲电路是为电容器-双极性结型晶体管（Bipolar Junction Transistor,BJT）缓冲电路，故可简称为CB缓冲器。
图2至图5绘示图1所示的缓冲电路于不同的实施例中所涉及的实施细节，其中图2至图5的实施例分别对应于类型TYPE1、TYPE2、TYPE3、TYPE4。
图6至图9为依据本发明一第二实施例的一种缓冲电路的不同类型的示意图，其中图6至图9所示的一系列的缓冲电路是为电阻器（Resistor）-电容器（Capacitor）-双极性结型晶体管（BJT）缓冲电路，故可简称为RCB缓冲器。
图10绘示图1所示的缓冲电路于一实施例中所涉及的某些实验的架构。
图11绘示图10右半部所示的缓冲电路于一实施例中的实施细节。
图12绘示图10右半部所示的缓冲电路于另一实施例中的实施细节。
图13绘示上述实施例的缓冲电路于一实施例中所涉及的交换式电源供应器。
图14绘示图2所示的缓冲电路于一实施例中针对图13所示的交换式电源供应器中的隔离功率变压器的一次侧的设置方案，其中该设置方案对应于类型TYPE1。
图15绘示图3所示的缓冲电路于另一实施例中针对图13所示的交换式电源供应器中的隔离功率变压器的二次侧的设置方案，其中该设置方案对应于类型TYPE2。
图16绘示本发明的缓冲电路诸如上述的CB缓冲器与RCB缓冲器于某些实施例中对突波电压的影响。
其中，附图标记说明如下：
100、                        缓冲电路
100A、100B、100C、100D、
200A、200B、200C、200D、
300A、300B、300C、400
120、C1、C2、C6、C7、            电容器
C8、C9、C10、C11、C12
130、Q1、Q2、Q7、Q8、            双极性结型晶体管
Q9、Q10、Q11、Q12
A、B                             缓冲电路的端子
D11                              二极管
G                                接地端子
L1                               电感器
QA、QB、QC                       金属氧化物半导体场效应晶体管
R1、R2、R3、R4、R5、R6           电阻器
T1                               隔离功率变压器
Vin                              输入电压
Vout                             输出电压
具体实施方式
图1为依据本发明一第一实施例的一种缓冲电路（Snubber Circuit）100的示意图，其中缓冲电路100是为电容器（Capacitor）-双极性结型晶体管（Bipolar Junction Transistor,BJT）缓冲电路，故可简称为CB缓冲器。于本实施例中，缓冲电路100包含一电容器120以及一双极性结型晶体管130。尤其是，电容器120具有一第一端子与一第二端子，其中电容器120的该第一端子是电气连接至缓冲电路100的一第一端子A，而双极性结型晶体管130的发射极（Emitter）与集电极（Collector）中的一者是电气连接至电容器120的该第二端子，并且双极性结型晶体管130的发射极与集电极中的另一者是电气连接至缓冲电路100的一第二端子B。实作上，双极性结型晶体管130的基极（Base）与发射极是被导通。
依据本实施例，一种将一双极性结型晶体管诸如双极性结型晶体管130用于一缓冲电路诸如缓冲电路100的方法包含有下列步骤：将该双极性结型晶体管的基极与发射极导通；以及基于该双极性结型晶体管的基极与集电极之间的至少一接面特性，利用该双极性结型晶体管作为一快速二极管，以供设置于该缓冲电路。其中利用该双极性结型晶体管作为该快速二极管以供设置于该缓冲电路的步骤包含：将该双极性结型晶体管诸如双极性结型晶体管130的发射极与集电极中的一者电气连接至一电容器诸如电容器120的一端子（于本实施例中尤其是电容器120的该第二端子）；将该电容器诸如电容器120的另一端子（于本实施例中尤其是电容器120的该第一端子）电气连接至该缓冲电路诸如缓冲电路100的第一端子A；以及将该双极性结型晶体管诸如双极性结型晶体管130的发射极与集电极中的另一者电气连接至该缓冲电路诸如缓冲电路100的第二端子B。尤其是，该至少一接面特性包含导通快的特性、恢复时间（Storage Time）慢的特性、变换缓和的特性、以及基极-集电极接面电容Cbc小的特性，其中上述利用该双极性结型晶体管作为该快速二极管的步骤另包含：利用该导通快的特性将漏感能量快速地转移至该缓冲电路当中的该电容器中，再利用该恢复时间慢的特性使该电容器中的能量反推回源头；以及利用该变换缓和的特性以及该基极-集电极接面电容Cbc小的特性缩小共振幅度。
图2至图5绘示图1所示的缓冲电路100于不同的实施例中所涉及的实施细节，其中图2至图5的实施例分别对应于类型TYPE1、TYPE2、TYPE3、TYPE4。为了便于理解且便于说明，图2至图5所示的缓冲电路可分别称为缓冲电路100A、100B、100C、100D。
如图2所示，缓冲电路100A包含电容器C1以及双极性结型晶体管Q1，其中双极性结型晶体管Q1的基极与发射极是被导通并电气连接至该缓冲电路100A的第二端子B，而该双极性结型晶体管Q1的集电极是电气连接至该电容器C1的一端子（其对应于图1所示实施例中的电容器120的该第二端子），且该电容器C1的另一端子（其对应于图1所示实施例中的电容器120的该第一端子）是电气连接至该缓冲电路100A的第一端子A。
如图3所示，缓冲电路100B包含电容器C6以及双极性结型晶体管Q7，其中双极性结型晶体管Q7的基极与发射极是被导通并电气连接至该电容器C6的一端子（其对应于图1所示实施例中的电容器120的该第二端子），而该双极性结型晶体管Q7的集电极是电气连接至该缓冲电路100B的第二端子B，且该电容器C6的另一端子（其对应于图1所示实施例中的电容器120的该第一端子）是电气连接至该缓冲电路100B的第一端子A。
如图4所示，缓冲电路100C包含电容器C2以及双极性结型晶体管Q2，其中双极性结型晶体管Q2的基极与发射极是被导通并电气连接至该缓冲电路100C的第二端子B，而该双极性结型晶体管Q2的集电极是电气连接至该电容器C2的一端子（其对应于图1所示实施例中的电容器120的该第二端子），且该电容器C2的另一端子（其对应于图1所示实施例中的电容器120的该第一端子）是电气连接至该缓冲电路100C的第一端子A。
如图5所示，缓冲电路100D包含电容器C7以及双极性结型晶体管Q8，其中双极性结型晶体管Q8的基极与发射极是被导通并电气连接至该电容器C7的一端子（其对应于图1所示实施例中的电容器120的该第二端子），而该双极性结型晶体管Q8的集电极是电气连接至该缓冲电路100D的第二端子B，且该电容器C7的另一端子（其对应于图1所示实施例中的电容器120的该第一端子）是电气连接至该缓冲电路100D的第一端子A。
依据某些实施例诸如上述各个实施例及其变化例，缓冲电路100可动态地调整端子A对端子B的电压Vab。基于上述的至少一接面特性，缓冲电路100可利用双极性结型晶体管130作为一快速二极管。尤其是，缓冲电路100可利用该导通快的特性将漏感能量快速地转移至该缓冲电路当中的一电容器中、然后利用该恢复时间慢的特性使该电容器中的能量反推回源头，并且利用该变换缓和的特性以及该基极-集电极接面电容Cbc小的特性缩小共振幅度。
图6至图9为依据本发明一第二实施例的一种缓冲电路的不同类型的示意图，其中图6至图9所示的一系列的缓冲电路是为电阻器（Resistor）-电容器（Capacitor）-双极性结型晶体管（BJT）缓冲电路，故可简称为RCB缓冲器。相较于该第一实施例，该第二实施例的缓冲电路中设置有至少一电阻。尤其是，该第二实施例的缓冲电路包含一第一电容器诸如电容器120、一电阻器以及一双极性结型晶体管诸如双极性结型晶体管130，其中该第一电容器具有一第一端子与一第二端子，该第一电容器的该第一端子是电气连接至该缓冲电路的一第一端子诸如第一端子A，而该电阻器具有一第一端子与一第二端子，其中该电阻器的第一端子是电气连接至该第一电容器的第二端子，该双极性结型晶体管的发射极与集电极中的一者是电气连接至该电阻器的该第二端子，且该双极性结型晶体管的发射极与集电极中的另一者是电气连接至该缓冲电路的一第二端子诸如第二端子B；实作上，双极性结型晶体管130的基极与发射极是被导通。
如图6所示，缓冲电路200A包含电容器C8、电阻器R2以及双极性结型晶体管Q9，其中双极性结型晶体管Q9的基极与发射极是被导通并电气连接至该缓冲电路200A的第二端子B，该双极性结型晶体管Q9的集电极是电气连接至该电阻器R2的该第二端子，而该电阻器R2的第一端子是电气连接至该电容器C8的第二端子，且该电容器C8的第一端子是电气连接至该缓冲电路200A的第一端子A。
如图7所示，缓冲电路200B包含电容器C9、电阻器R3以及双极性结型晶体管Q10，其中双极性结型晶体管Q10的基极与发射极是被导通并电气连接至该电阻器R3的该第二端子，双极性结型晶体管Q10的集电极是电气连接至缓冲电路200B的第二端子B，而该电阻器R3的该第一端子是电气连接至该电容器C9的第二端子，且该电容器C9的第一端子是电气连接至该缓冲电路200B的第一端子A。
如图8所示，缓冲电路200C包含电容器C10、电阻器R4以及双极性结型晶体管Q11，其中双极性结型晶体管Q11的基极与发射极是被导通并电气连接至该缓冲电路200C的第二端子B，该双极性结型晶体管Q11的集电极是电气连接至该电阻器R4的该第二端子，而该电阻器R4的第一端子是电气连接至该电容器C10的第二端子，且该电容器C10的第一端子是电气连接至该缓冲电路200C的第一端子A。
如图9所示，缓冲电路200D包含电容器C11、电阻器R5以及双极性结型晶体管Q12，其中双极性结型晶体管Q12的基极与发射极是被导通并电气连接至该电阻器R5的该第二端子，双极性结型晶体管Q12的集电极是电气连接至缓冲电路200D的第二端子B，而该电阻器R5的该第一端子是电气连接至该电容器C11的第二端子，且该电容器C11的第一端子是电气连接至该缓冲电路200D的第一端子A。
其中上述第一实施例及第二实施例的缓冲电路100A~100D、200A~200D是可并联于一主动组件或一负载，该主动组件是为一金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)、一二极管(Diode)、一双极性结型晶体管(BJT)、一绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,IGBT)、一静电感应晶体管(StaticInduction Transistor,SIT)、一闸流体或其组成的电路，而该负载是为一电感、一电阻、一电容或其组成的电路。
图10绘示图6所示的缓冲电路200A于一实施例中所涉及的某些实验的架构，其中图10右半部所示架构为本实施例的缓冲电路300A，而图10左半部中的缓冲电路400则为采用二极管(Diode)的现有架构(其可称为传统RCD缓冲电路)且可供对照的用。为了便于理解，图10中绘示了缓冲电路300A、400并接于电感器L1，电感器L1在本实施例中是为一负载，其中该负载亦可为一电阻、一电容或其组成的电路。依据本实施例，该缓冲电路300A相较于上述的RCB缓冲器诸如图6的缓冲电路200A更包含电容器C12，其中该电容器C12是并联于该电容器C1的第一端子与该电阻器R1的第二端子，而电容器C1的电容值大于电容器C12的电容值，使电容器C12可用来阻挡微小的电气噪声。尤其是，于本实施例中，双极性结型晶体管Q1是可为制造商Fairchild Semiconductor生产的型号KSP44，而二极管D11是可为制造商Fairchild Semiconductor、ON Semiconductor或Diodes Incorporated生产的型号1N4007，且电阻器R1、R6的电阻值可分别为10奥姆（Ohm）与100千奥姆，并且电容器C12、C1的电容值可分别为2.2奈法拉（Nano-Farad）与10奈法拉，其中该型号为KSP44的双极性结型晶体管Q1，其规格如下:集电极-发射极最大电压(VCEO)为400V，发射极-基极最大电压(VEBO)为6V，集电极电流(IC)为300mA。这只是为了说明的目的而已，并非对本发明的限制。
依据本实施例的某些变化例，诸如图11至图12所示的实施例，电容器C12可从图10右半部所示的缓冲电路300A架构中移除，亦即该缓冲电路300B可在电容器C12不存在的状况下正常运作。例如：在图11所示的实施例中，电阻器R1的电阻值可为0奥姆至∞奥姆，较佳者为100奥姆至200奥姆，亦可小于100奥姆。又例如：在图12所示的实施例中，上述的电阻器R1的电阻值为零时，R1等同于自图11所示的架构中移除，亦即缓冲电路300C可在电阻器R1与电容器C12不存在的状况下正常运作，其中本实施例的缓冲电路300C是等同于图2所示的CB缓冲器架构。
基于图10所示的实施例，表1至表6列出该些实验的测试结果，可供证实图10右半部所示的缓冲电路300A（其测试结果为表2、表4、表6）相较于图10左半部中采用二极管的缓冲电路400（其测试结果为表1、表3、表5）的优势。于表1至表6中的每一者当中，参数Input_Voltage与Load_分别代表输入电压与负载，其中表1至表2是为输入电压Input_Voltage=90Vac的测试结果（Vac的下标「ac」代表交流电），表3至表4是为输入电压Input_Voltage=100Vac的测试结果，而表5至表6是为输入电压Input_Voltage=115Vac的测试结果。另外，参数Percent_of_Rated_Load代表指定负载的百分比（Percent of Rated Load），其中不同的百分比诸如「1%」、「2%」、...「100%」。此外，后续的参数Output_Current、Output_Voltage、Efficiency_、与Average_Efficiency_分别代表输出电流、输出电压、效率、与平均效率，其中该平均效率是为指定负载的百分比25%、50%、75%与100%的平均效率。
表1
Figure BDA00002133925000101
表2
Figure BDA00002133925000102
表3
Figure BDA00002133925000103
表4
Figure BDA00002133925000104
表5
Figure BDA00002133925000111
表6
Figure BDA00002133925000112
基于表1至表6列出的测试结果，该些实验可证实图10右半部所示的缓冲电路300A（其测试结果为表2、表4、表6）的整体效能优于图10左半部中采用二极管的缓冲电路400（其测试结果为表1、表3、表5）的整体效能。尤其是，缓冲电路电性连接一轻负载的状况下，其中本发明的轻负载是为指定负载的百分比（Percent of Rated Load）小(等)于20%，亦即负载占全负载的20%以下，例如:指定负载的百分比为1%~20%；由表1至表6可知，本实施例的缓冲电路300A的效率远超过图10左半部中采用二极管的缓冲电路400的效率，例如:参阅表1与表2，同样在指定负载的百分比为1%时，表2(缓冲电路300A)相较于表1(缓冲电路400)可增加10.75%(57.84%→68.59%)的效率，又例如:参阅表1与表2，同样在指定负载的百分比为20%时，表2(缓冲电路300A)相较于表1(缓冲电路400)亦可增加1.23%(88.22%→89.45%)的效率。
藉此，本实施例的缓冲电路300A相较于传统的RCD缓冲电路(缓冲电路400)可在轻负载时达到提高效率的功效，因此本发明的缓冲电路特别适用于空载或轻负载的情况，而可设置在小功率的转接器(Adapter)或小功率的电源供应器(Power Supply)上，其中本实施例的缓冲电路300A除在轻负载时效率有明显的增加外，由表1至表6的Average_Efficiency_可得知在重负载时(25%~100%)的平均效率是小幅增加0.3%~0.6%。因此，使用本发明缓冲电路的电源供应器相较于使用RCD缓冲电路的电源供应器，具有较高的转换效率，尤其在轻载的情况下更为明显。
图13绘示上述实施例的缓冲电路于一实施例中所涉及的交换式电源供应器，其中该交换式电源供应器包含一输入整流与滤波电路、一交换组件、一隔离功率变压器T1、一输出整流电路、以及一输出滤波电路，且另包含多个缓冲电路100A~100D、200A~200D、300A~300C中的至少一部分。于图13中，左下角的符号AC代表交流（Alternating Current,AC）输入，而右下角的符号DC代表直流（Direct Current,DC）输出。
图14绘示图2所示的缓冲电路100A于一实施例中针对图13所示的交换式电源供应器中的隔离功率变压器T1的一次侧的设置方案，其中该设置方案对应于类型TYPE1。于图14中，符号G代表接地端子，而符号Vin与Vout分别代表输入电压与输出电压。
依据本实施例，缓冲电路100A可设置于交换式电源供应器的隔离功率变压器T1的一次侧。尤其是，当缓冲电路100A使用于隔离功率变压器T1的一次侧时，缓冲电路100A可和隔离功率变压器T1的一次侧并联，且可和该交换式电源供应器中的至少一交换组件(诸如图13所示的交换组件)串联。另外，该交换组件可为一开关管。例如：于本实施例中，该开关管为一金属氧化物半导体场效应晶体管（MOSFET）QA。这只是为了说明的目的而已，并非对本发明的限制。依据本实施例的某些变化例，该开关管可为一个二极管、一双极性结型晶体管(BJT)、一绝缘栅双极晶体管(IGBT)、一静电感应晶体管(SIT)、一闸流体或其组成的电路（其于该些变化例中可取代金属氧化物半导体场效应晶体管QA）。例如：基于该二极管的电压-电流特性，该二极管可随着其跨压自动地开启或关闭，故可视为自动开关管，其中该二极管的两端子的设置方向可依不同的设计而决定。
于本实施例中，缓冲电路100A的第一端子A电气连接至隔离功率变压器T1的一次侧的一端子，而缓冲电路100A的另一端B则电气连接至隔离功率变压器T1的一次侧的另一端子以及该交换组件诸如上述的开关管（例如：金属氧化物半导体场效应晶体管QA），藉此，在高频切换时由该开关管产生的漏感能量可被缓冲电路100A所吸收以进行能量回收运作。尤其是，缓冲电路100A可利用上述至少一接面特性进行上述的能量回收运作。例如：缓冲电路100A可利用该导通快的特性将漏感能量快速的转移至电容器120中，并利用该恢复时间慢的特性使电容器120中的能量反推回源头。请注意，在进行上述能量回收运作时，缓冲电路100A可利用该变换缓和的特性以及该基极-集电极接面电容Cbc小的特性缩小共振幅度；如此，缓冲电路100A可降低突波电压(如图16所示)，而可有效保护组件。
图15绘示图3所示的缓冲电路100B于另一实施例中针对图13所示的交换式电源供应器中的隔离功率变压器T1的二次侧的设置方案，其中该设置方案对应于类型TYPE2。相仿地，于图15中，符号G代表接地端子，而符号Vin与Vout分别代表输入电压与输出电压。
依据本实施例，缓冲电路100B亦可设置于隔离功率变压器T1的二次侧。尤其是，当缓冲电路100B（对应于类型TYPE2）使用于隔离功率变压器T1的二次侧时，缓冲电路100B可和图13所示的输出整流电路的一开关管并联，藉此，在高频切换时由该开关管产生的能量可被缓冲电路100B所吸收，以利用上述至少一接面特性进行能量回收运作。例如：在该开关管是为金属氧化物半导体场效应晶体管QB的状况下，缓冲电路100B可和金属氧化物半导体场效应晶体管QB并联，以保护金属氧化物半导体场效应晶体管QB免受突波电压的破坏。又例如：在该开关管是为金属氧化物半导体场效应晶体管QC的状况下，缓冲电路100B可和金属氧化物半导体场效应晶体管QC并联，以保护金属氧化物半导体场效应晶体管QC免受突波电压的破坏。这只是为了说明的目的而已，并非对本发明的限制。依据本实施例的某些变化例，该开关管可为一个二极管（其于该些变化例中可取代金属氧化物半导体场效应晶体管QB或QC）。例如：基于该二极管的电压-电流特性，该二极管可随着其跨压自动地开启或关闭，故可视为自动开关管，其中该二极管的两端子的设置方向可依不同的设计而决定。
图16绘示本发明的缓冲电路诸如上述的CB缓冲器与RCB缓冲器于某些实施例中对突波电压的影响。基于上列实施例诸如图13至图15所示者，缓冲电路100可降低突波电压，例如将图16左半部所示的波形的突波电压降低为图16右半部所示者。
本发明的好处之一是，本发明的缓冲电路的构造简单且易于实施，同时能避免相关技术的问题。另外，本发明的缓冲电路可并联于一主动组件或一负载以保护负载所连接的电路，例如设置于交换式电源供应器中以保护变压器一次侧连接的交换组件或二次侧连接的输出整流电路，尤其可吸收主动组件在高频切换时所产生的突波或噪声以做能量回收，由上述可知，本发明的缓冲电路可有效保护组件，且使用本发明缓冲电路的电源供应器相较于使用传统缓冲电路的电源供应器具有较高的转换效率，尤其是在轻载时更为明显。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (11)

1.一种缓冲电路，该缓冲电路的特征在于包含有：
一电容器，该电容器具有一第一端子与一第二端子，其中该电容器的该第一端子是电气连接至该缓冲电路的一第一端子；以及
一双极性结型晶体管，其中该双极性结型晶体管的发射极与集电极中的
一者是电气连接至该电容器的该第二端子，且该双极性结型晶体管的发射极与集电极中的另一者是电气连接至该缓冲电路的一第二端子。
2.如权利要求1所述的缓冲电路，其特征在于，基于该双极性结型晶体管的基极与集电极之间的至少一接面特性，该缓冲电路利用该双极性结型晶体管作为一快速二极管。
3.如权利要求2所述的缓冲电路，其特征在于，该至少一接面特性包含导通快的特性、恢复时间慢的特性、变换缓和的特性以及基极-集电极接面电容小的特性，而该缓冲电路利用该导通快的特性将漏感能量快速地转移至该电容器中，且利用该恢复时间慢的特性使该电容器中的能量反推回源头，以及该缓冲电路利用该变换缓和的特性、该基极-集电极接面电容小的特性缩小共振幅度。
4.一种缓冲电路，该缓冲电路的特征在于包含有：
一第一电容器，该第一电容器具有一第一端子与一第二端子，其中该第一电容器的该第一端子是电气连接至该缓冲电路的一第一端子；
一电阻器，该电阻器具有一第一端子与一第二端子，其中该电阻器的该第一端子是电气连接至该第一电容器的该第二端子；以及
一双极性结型晶体管，其中该双极性结型晶体管的发射极与集电极中的
一者是电气连接至该电阻器的该第二端子，且该双极性结型晶体管的发射极与集电极中的另一者是电气连接至该缓冲电路的一第二端子。
5.如权利要求4所述的缓冲电路，其特征在于，该缓冲电路更包含一第二电容器，该第二电容器是并联于该第一电容器的该第一端子与该电阻器的该第二端子。
6.如权利要求1、4或5所述的缓冲电路，其特征在于，该双极性结型晶体管的基极与发射极是被导通。
7.如权利要求1、4或5所述的缓冲电路，其特征在于，该缓冲电路是并联于一主动组件或一负载，该主动组件是为一金属氧化物半导体场效应晶体管、一二极管、一双极性结型晶体管、一绝缘栅双极晶体管、一静电感应晶体管、一闸流体或其组成的电路，而该负载是为一电感、一电阻、一电容或其组成的电路。
8.如权利要求7所述的缓冲电路，其特征在于，当该缓冲电路使用于一变压器的一次侧时，该缓冲电路是并联于该变压器的一次侧且串联于至少一开关管。
9.如权利要求7所述的缓冲电路，其特征在于，当该缓冲电路使用于一变压器的二次侧时，该缓冲电路是并联于一输出整流电路的一开关管。
10.如权利要求1、4或5所述的缓冲电路，其特征在于，该缓冲电路是电性连接一轻负载，而使该缓冲电路相较于传统缓冲电路在轻负载时可提高效率，其中该轻负载是为负载占全负载的20%以下。
11.一种将一双极性结型晶体管用于一缓冲电路的方法，该方法的特征在于包含有下列步骤：
将该双极性结型晶体管的基极与发射极导通；以及
基于该双极性结型晶体管的基极与集电极之间的至少一接面特性，利用该双极性结型晶体管作为一快速二极管，以供设置于该缓冲电路，
其中利用该双极性结型晶体管作为该快速二极管以供设置于该缓冲电路的步骤包含：
将该双极性结型晶体管的发射极与集电极中的一者电气连接至一电容器的一端子；
将该电容器的另一端子电气连接至该缓冲电路的一第一端子；以及
将该双极性结型晶体管的发射极与集电极中的另一者电气连接至该缓冲电路的一第二端子。
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US8941962B2 (en) 2015-01-27
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