CN103001478A - 将双极性结型晶体管用于缓冲电路的方法和缓冲电路 - Google Patents

将双极性结型晶体管用于缓冲电路的方法和缓冲电路 Download PDF

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Publication number
CN103001478A
CN103001478A CN2012103400878A CN201210340087A CN103001478A CN 103001478 A CN103001478 A CN 103001478A CN 2012103400878 A CN2012103400878 A CN 2012103400878A CN 201210340087 A CN201210340087 A CN 201210340087A CN 103001478 A CN103001478 A CN 103001478A
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buffer circuit
characteristic
capacitor
junction
bipolar junction
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CN103001478B (zh
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林国藩
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FSP Technology Inc
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FSP Technology Inc
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Abstract

本发明公开了一种将一双极性结型晶体管用于一缓冲电路的方法和缓冲电路。该缓冲电路包括有：至少一阻抗组件、一电容器、以及一双极性结型晶体管。该缓冲电路是用于保护电力／电子组件、降低高频干扰及突波电压、以及改善效率。尤其是，该缓冲电路中的该至少一阻抗组件可为至少一齐纳二极管；针对保护电力／电子组件、降低高频干扰及突波电压、以及改善效率，该缓冲电路在采用齐纳二极管的情况下的效能较在采用别种阻抗组件的情况下的效能更佳。

Description

将双极性结型晶体管用于缓冲电路的方法和缓冲电路
技术领域
本发明是有关于电力／电子组件的保护电路，尤指一种缓冲电路以及将双极性结型晶体管用于缓冲电路的方法。
背景技术
近年来由于电子电路的技术不断地发展，各种电力／电子组件的保护电路被广泛地实施于诸多应用中。因此，这些保护电路的设计遂成为相当热门的议题。传统的保护电路当中，有某些缓冲电路，其构造简单、易于实施，故被广泛地应用于电力／电子电路。然而，这些传统的缓冲电路(例如一RCD缓冲电路)还是有不足之处。例如：传统的缓冲电路的能量损耗很高，且其效率通常很差。又例如：传统的缓冲电路无法确保最高突波电压值的限制，也就是说，突波电压值可能超过整体电路所能承受的范围，故采用传统的缓冲电路易造成半导体组件的损坏。因此，需要一种新颖的方法来提升缓冲电路的电路保护的效能。
发明内容
因此本发明之一目的在于提供一种缓冲电路（Snubber Circuit）以及将双极性结型晶体管（Bipolar Junction Transistor,BJT）用于缓冲电路的方法，以解决上述问题。
本发明的一目的在于提供一种缓冲电路以及将双极性结型晶体管用于缓冲电路的方法，以保护电力／电子组件、降低高频干扰及突波电压、及／或改善效率。
本发明的较佳实施例中提供一种缓冲电路，该缓冲电路包括有：至少一阻抗组件、一电容器、以及一双极性结型晶体管。尤其是，该缓冲电路中的该至少一阻抗组件是为至少一齐纳二极管（Zener Diode），其中该缓冲电路在采用齐纳二极管的情况下的效能较在采用别种阻抗组件的情况下的效能更佳。
本发明于提供上述缓冲电路的同时，亦对应地提供一种将一双极性结型晶体管用于一缓冲电路的方法，该方法包括有下列步骤：将该双极性结型晶体管的基极（Base）与发射极（Emitter）导通；以及基于该双极性结型晶体管的基极与集电极（Collector）之间的至少一接面特性，利用该双极性结型晶体管作为一快速二极管，以供设置于该缓冲电路。尤其是，该至少一接面特性包括导通快的特性以及恢复时间（Storage Time）慢的特性，而且利用该双极性结型晶体管作为该快速二极管的步骤另包括：利用该导通快的特性将漏感能量快速地转移至该缓冲电路当中的一电容器中，再利用该恢复时间慢的特性使该电容器中的能量反推回源头。
本发明的好处之一是，本发明的缓冲电路的构造简单且易于实施，同时能避免相关技术的问题。另外，本发明的缓冲电路以及将双极性结型晶体管用于缓冲电路的方法可提供极佳的效率，又能确保最高突波电压值，使各种电力／电子组件诸如保护半导体组件获得最佳的保护。
附图说明
图1为依据本发明一第一实施例的一种缓冲电路（Snubber Circuit）的示意图，其中该缓冲电路是为阻抗组件（例如：齐纳二极管（Zener Diode））-电容器-双极性结型晶体管（Bipolar Junction Transistor,BJT）缓冲电路，故可简称为ZCB缓冲器。
图2至图9绘示图1所示的缓冲电路于不同的实施例中所涉及的实施细节，其中图2至图9的实施例分别对应于类型TA、TB、TC、TD、TE、TF、TG、与TH。
图10为图1所示的缓冲电路于某些实施例中所涉及的电压，其中该缓冲电路可动态地调整该电压。
图11至图14绘示图10所示的电压于不同的实施例中对时间的曲线，其中图11至图14所示的实施例分别对应于状况CS1、CS2、CS3、与CS4。
图15绘示图6所示的缓冲电路于一实施例中在状况CS1的运作。
图16绘示图6所示的缓冲电路于图15所示实施例中的相关曲线。
图17绘示图4所示的缓冲电路于一实施例中在状况CS2的运作。
图18绘示图4所示的缓冲电路于图17所示实施例中的相关曲线。
图19至图22为依据本发明一第二实施例的一种缓冲电路的不同类型TYPE1、TYPE2、TYPE3、TYPE4的示意图，其中图19至图22所示的一系列的缓冲电路是为电容器-双极性结型晶体管（BJT）缓冲电路，故可简称为CB缓冲器。图23绘示上述实施例的缓冲电路诸如ZCB缓冲器与CB缓冲器于一实施例中所涉及的交换式电源供应器。
图24绘示图2所示的缓冲电路于一实施例中针对图23所示的交换式电源供应器中的隔离功率变压器的一次侧的设置方案，其中该设置方案对应于类型TA。
图25绘示图3所示的缓冲电路于另一实施例中针对图23所示的交换式电源供应器中的隔离功率变压器的二次侧的设置方案，其中该设置方案对应于类型TB。
其中，附图标记说明如下：
100、                缓冲电路
100A、100B、100C、100D、
100E、100F、100G、100H、
200A、200B、200C、200D
110                  阻抗组件
120、                电容器
C1、C2、C3、C4、
C5、C6、C7、C8
130、                     双极性结型晶体管
Q1、Q2、Q3、Q4、
Q5、Q6、Q7、Q8
A、B                      端子
D1、D2、D3、D4、D5、      齐纳二极管
D6、D7、D8、D9、D10、
D11、D12
G                         接地端子
I_C3、I_D4、I_Q3、        电流
I_D2、I_Q2
QA、QB、QC                金属氧化物半导体场效应晶体管
T1                        隔离功率变压器
t                         时间
Vab                       端子A对端子B的电压
V_(d3+d4)、V_D2           电压
Vin                       输入电压
Vout                      输出电压
具体实施方式
图1为依据本发明一第一实施例的一种缓冲电路（Snubber Circuit）100的示意图，其中缓冲电路100是为阻抗组件（例如：齐纳二极管（Zener Diode））-电容器（Capacitor）-双极性结型晶体管（Bipolar Junction Transistor,BJT）缓冲电路，故可简称为ZCB缓冲器。于本实施例中，缓冲电路100包括至少一阻抗组件110（例如：至少一齐纳二极管）、一电容器120、以及一双极性结型晶体管130。
依据本实施例，一种将双极性结型晶体管130用于一缓冲电路诸如缓冲电路100的方法包括有下列步骤：将该双极性结型晶体管的基极（Base）与发射极（Emitter）导通；以及基于该双极性结型晶体管的基极与集电极（Collector）之间的至少一接面特性，利用该双极性结型晶体管作为一快速二极管，以供设置于该缓冲电路。尤其是，该至少一接面特性包括导通快的特性、恢复时间（Storage Time）慢的特性、变换缓和的特性、以及基极-集电极接面电容Cbc小的特性，其中上述利用该双极性结型晶体管作为该快速二极管的步骤另包括：利用该导通快的特性将漏感能量快速地转移至该缓冲电路当中的一电容器中，再利用该恢复时间慢的特性使该电容器中的能量反推回源头，然后利用该变换缓和的特性以及该基极-集电极接面电容Cbc小的特性缩小共振幅度。实作上，阻抗组件110可用来确保最高突波电压值的限制并且用来消耗剩余的能量。
依据某些实施例，诸如该第一实施例的某些变化例，上述的至少一阻抗组件110是为至少一齐纳二极管，其中缓冲电路100在采用齐纳二极管的情况下的效能较在采用别种阻抗组件的情况下的效能更佳。实作上，该些实施例中的齐纳二极管可用来确保最高突波电压值的限制并且用来消耗剩余的能量。
图2至图9绘示图1所示的缓冲电路100于不同的实施例中所涉及的实施细节，其中图2至图9的实施例分别对应于类型TA、TB、TC、TD、TE、TF、TG、与TH。为了便于理解且便于说明，图2至图9所示的缓冲电路可分别称为缓冲电路100A、100B、100C、100D、100E、100F、100G、与100H。
如图2所示，缓冲电路100A包括齐纳二极管D1、电容器C1、以及双极性结型晶体管Q1，其中双极性结型晶体管Q1的基极与发射极是被导通而电气连接至缓冲电路100A的第二端子B，而该电容器C1的两端是并联于该齐纳二极管D1的两端，且该双极性结型晶体管Q1的集电极是串联至该齐纳二极管D1的阴极，而该齐纳二极管D1的阳极是电气连接至缓冲电路100A的第一端子A。
如图3所示，缓冲电路100B包括齐纳二极管D11、电容器C6、以及双极性结型晶体管Q7，其中双极性结型晶体管Q7的基极与发射极是被导通而串联至该齐纳二极管D11的阳极，而该电容器C6的两端是并联于该齐纳二极管D11的两端，且该双极性结型晶体管Q7的集电极是电气连接至缓冲电路100B的第二端子B，而该齐纳二极管D11的阴极是电气连接至缓冲电路100B的第一端子A。
如图4所示，缓冲电路100C包括齐纳二极管D2、电容器C2、以及双极性结型晶体管Q2，其中双极性结型晶体管Q2的基极与发射极是被导通而电气连接至缓冲电路100C的第二端子B，而该电容器C2的两端是并联于该齐纳二极管D2的两端，且该双极性结型晶体管Q2的集电极是串联至该齐纳二极管D2的阳极，而该齐纳二极管D1的阴极是电气连接至缓冲电路100C的第一端子A。
如图5所示，缓冲电路100D包括齐纳二极管D12、电容器C7、以及双极性结型晶体管Q8，其中双极性结型晶体管Q8的基极与发射极是被导通而串联至该齐纳二极管D12的阴极，而该电容器C7的两端是并联于该齐纳二极管D12的两端，且该双极性结型晶体管Q8的集电极是电气连接至缓冲电路100D的第二端子B，而该齐纳二极管D12的阳极是电气连接至缓冲电路100D的第一端子A。
如图6所示，缓冲电路100E包括齐纳二极管D3与D4、电容器C3、以及双极性结型晶体管Q3，其中双极性结型晶体管Q3的基极与发射极是被导通而电气连接至缓冲电路100E的第二端子B，而该双极性结型晶体管Q3的集电极是电气连接至该电容器C3的一端子，且该电容器C3的另一端子是电气连接至缓冲电路100E的第一端子A，而齐纳二极管D3的阳极是串联至齐纳二极管D4的阴极，且齐纳二极管D3与D4串联所形成的模块分别通过该齐纳二极管D3的阴极与该齐纳二极管D4的阳极并联于该双极性结型晶体管Q3的发射极与集电极。
如图7所示，缓冲电路100F包括齐纳二极管D9与D10、电容器C8、以及双极性结型晶体管Q6，其中双极性结型晶体管Q6的基极与发射极是被导通而电气连接至该电容器C8的一端子，而该双极性结型晶体管Q6的集电极是电气连接至缓冲电路100F的第二端子B，且该电容器C8的另一端子是电气连接至缓冲电路100F的第一端子A，而齐纳二极管D10的阳极是串联至齐纳二极管D9的阴极，且齐纳二极管D10与D9串联所形成的模块分别通过该齐纳二极管D10的阴极与该齐纳二极管D9的阳极并联于该双极性结型晶体管Q6的发射极与集电极。
如图8所示，缓冲电路100G包括齐纳二极管D5与D6、电容器C4、以及双极性结型晶体管Q4，其中双极性结型晶体管Q4的基极与发射极是被导通而电气连接至缓冲电路100G的第二端子B，而该双极性结型晶体管Q4的集电极是电气连接至该电容器C4的一端子，且该电容器C4的另一端子是电气连接至缓冲电路100G的第一端子A，而齐纳二极管D5的阳极是串联至齐纳二极管D6的阴极，且齐纳二极管D5与D6串联所形成的模块分别通过该齐纳二极管D5的阴极与该齐纳二极管D6的阳极并联于该双极性结型晶体管Q4的集电极与发射极。
如图9所示，缓冲电路100H包括齐纳二极管D7与D8、电容器C5、以及双极性结型晶体管Q5，其中双极性结型晶体管Q5的基极与发射极是被导通而电气连接至该电容器C5的一端子，而该双极性结型晶体管Q5的集电极是电气连接至缓冲电路100H的第二端子B，且该电容器C5的另一端子是电气连接至缓冲电路100H的第一端子A，而齐纳二极管D8的阳极是串联至齐纳二极管D7的阴极，且齐纳二极管D8与D7串联所形成的模块分别通过该齐纳二极管D8的阴极与该齐纳二极管D7的阳极并联于该双极性结型晶体管Q5的集电极与发射极。
图10为图1所示的缓冲电路100于某些实施例诸如上述各个实施例中所涉及的电压Vab，即端子A对端子B的电压，其中缓冲电路100可动态地调整电压Vab。基于上述的至少一接面特性，缓冲电路100可利用双极性结型晶体管130作为一快速二极管。尤其是，缓冲电路100可利用该导通快的特性将漏感能量快速地转移至该缓冲电路当中的一电容器中、利用该恢复时间慢的特性使该电容器中的能量反推回源头、并且利用该变换缓和的特性以及该基极-集电极接面电容Cbc小的特性缩小共振幅度，其中上述的阻抗组件110诸如齐纳二极管D1、D2、D3与D4、D5与D6、D7与D8、D9与D10、D11、以及D12可用来确保最高突波电压值的限制并且用来消耗剩余的能量。
图11至图14绘示图10所示的电压Vab于不同的实施例中对时间t的曲线，其中图11至图14所示的实施例分别对应于状况CS1、CS2、CS3、与CS4。
依据图11所示的实施例，状况CS1代表电压Vab可大于或等于零并且突波可发生于电压Vab大于零的状况，其中缓冲电路100E与100H适用于状况CS1。
依据图12所示的实施例，状况CS2代表电压Vab可于正、负值之间切换并且突波可发生于电压Vab大于零（尤其是突波紧随着电压Vab的上升缘之后）的状况，其中缓冲电路100B与100C适用于状况CS2。
依据图13所示的实施例，状况CS3代表电压Vab可小于或等于零并且突波可发生于电压Vab小于零的状况，其中缓冲电路100F与100G适用于状况CS3。
依据图14所示的实施例，状况CS4代表电压Vab可于正、负值之间切换并且突波可发生于电压Vab小于零（尤其是突波紧随着电压Vab的下降缘之后）的状况，其中缓冲电路100A与100D适用于状况CS4。
图15绘示图6所示的缓冲电路100E于一实施例中在状况CS1的运作，而图16则绘示图6所示的缓冲电路100E于图15所示实施例中的相关曲线，其中符号I_C3、I_D4、与I_Q3分别代表通过电容器C3的电流、通过齐纳二极管D4的电流、与通过双极性结型晶体管Q3的电流。于本实施例中，缓冲电路100E可确保最高突波电压值的限制。尤其是，缓冲电路100E可确保突波电压值的最大值不超过V_(d3+d4)（即齐纳二极管D3的崩溃电压V_D3与齐纳二极管D4的崩溃电压V_D4的和）。
图17绘示图4所示的缓冲电路100C于一实施例中在状况CS2的运作，而图18则绘示图4所示的缓冲电路100C于图17所示实施例中的相关曲线，其中符号I_D2与I_Q2分别代表通过齐纳二极管D2的电流与通过双极性结型晶体管Q2的电流。于本实施例中，缓冲电路100C可确保最高突波电压值的限制。尤其是，缓冲电路100C可确保突波电压值的最大值不超过V_D2（即齐纳二极管D2的崩溃电压）。
图19至图22为依据本发明一第二实施例的一种缓冲电路200的不同类型TYPE1、TYPE2、TYPE3、TYPE4的示意图，其中缓冲电路200是为电容器（Capacitor）-双极性结型晶体管（BJT）缓冲电路，故可简称为CB缓冲器。于该第二实施例中，缓冲电路200包括一电容器120、以及一双极性结型晶体管130（尤其是，在此不需要设置上述的阻抗组件110），而缓冲电路200于不同类型TYPE1、TYPE2、TYPE3、TYPE4所涉及的实施细节是分别绘示于图19至图22。为了便于理解且便于说明，图19至图22所示的一系列的缓冲电路可分别称为缓冲电路200A、200B、200C、200D。
如图19所示，齐纳二极管D1是从图2所示的缓冲电路架构100A中移除，缓冲电路200A包括电容器C1以及双极性结型晶体管Q1，其中双极性结型晶体管Q1的基极与发射极是被导通并电气连接至该缓冲电路200A的第二端子B，而该双极性结型晶体管Q1的集电极是电气连接至该电容器C1的一端子，且该电容器C1的另一端子是电气连接至该缓冲电路200A的第一端子A。
如图20所示，齐纳二极管D11是从图3所示的缓冲电路架构100B中移除，缓冲电路200B包括电容器C6以及双极性结型晶体管Q7，其中双极性结型晶体管Q7的基极与发射极是被导通并电气连接至该电容器C6的一端子，而该双极性结型晶体管Q7的集电极是电气连接至该缓冲电路200B的第二端子B，且该电容器C6的另一端子是电气连接至该缓冲电路200B的第一端子A。
如图21所示，齐纳二极管D2是从图4所示的缓冲电路架构100C中移除，缓冲电路200C包括电容器C2以及双极性结型晶体管Q2，其中双极性结型晶体管Q2的基极与发射极是被导通并电气连接至该缓冲电路200C的第二端子B，而该双极性结型晶体管Q2的集电极是电气连接至该电容器C2的一端子，且该电容器C2的另一端子是电气连接至该缓冲电路200C的第一端子A。
如图22所示，齐纳二极管D12是从图5所示的缓冲电路架构100D中移除，缓冲电路200D包括电容器C7以及双极性结型晶体管Q8，其中双极性结型晶体管Q8的基极与发射极是被导通并电气连接至该电容器C7的一端子，而该双极性结型晶体管Q8的集电极是电气连接至该缓冲电路200D的第二端子B，且该电容器C7的另一端子是电气连接至该缓冲电路200D的第一端子A。
其中上述第一实施例及第二实施例的缓冲电路100A~100H、200A~200D是可并联于一主动组件或一负载，该主动组件是为一金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)、一二极管(Diode)、一双极性结型晶体管(BJT)、一绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,IGBT)、一静电感应晶体管(StaticInduction Transistor,SIT)、一闸流体或其组成的电路，而该负载是为一电感、一电阻、一电容或其组成的电路。
图23绘示上述实施例的缓冲电路诸如ZCB缓冲器与CB缓冲器于一实施例中所涉及的交换式电源供应器，其中该交换式电源供应器包括一输入整流与滤波电路、一交换组件、一隔离功率变压器T1、一输出整流电路、以及一输出滤波电路，且另包括多个缓冲电路100A~100H、200A~200D中的至少一部分。于图23中，左下角的符号AC代表交流（Alternating Current,AC）输入，而右下角的符号DC代表直流（Direct Current,DC）输出。
图24绘示图2所示的缓冲电路100A于一实施例中针对图23所示的交换式电源供应器中的隔离功率变压器T1的一次侧的设置方案，其中该设置方案对应于类型TA。于图24中，符号G代表接地端子，而符号Vin与Vout分别代表输入电压与输出电压。为了便于理解，图24中是以对应于类型TA的缓冲电路100A作为缓冲电路100的例子来说明。这只是为了说明的目的而已，并非对本发明的限制。该设置方案亦可予以变化，其中，是可根据设置方案的不同而采用分别对应于其它类型TB、TC、TD、TE、TF、TG、TH、TYPE1、TYPE2、TYPE3、与TYPE4的缓冲电路。例如：在采用对应于类型TG的缓冲电路100G的状况下，图24中的端子A与B之间的架构可代换为图8所示者。又例如：在采用对应于类型TYPE1的缓冲电路200A的状况下，图24中的端子A与B之间的架构可代换为图19所示者。
依据本实施例，缓冲电路100A可设置于交换式电源供应器的隔离功率变压器T1的一次侧。尤其是，缓冲电路100A可和隔离功率变压器T1的一次侧并联，且可和该交换式电源供应器中的至少一交换组件(诸如图23所示的交换组件)串联。另外，该交换组件可为一开关管。例如：于本实施例中，该开关管可为一金属氧化物半导体场效应晶体管（MOSFET）QA。这只是为了说明的目的而已，并非对本发明的限制。依据本实施例的某些变化例，该开关管可为一个二极管（其于该些变化例中可取代金属氧化物半导体场效应晶体管QA）。例如：基于该二极管的电压-电流特性，该二极管可随着其跨压自动地开启或关闭，故可视为自动开关管，其中该二极管的两端子的设置方向可依不同的设计而决定。依据本实施例的某些变化例，该开关管可为一双极性结型晶体管(BJT)、一绝缘栅双极晶体管(IGBT)、一静电感应晶体管(SIT)、一闸流体或其组成的电路（其于该些变化例中可取代金属氧化物半导体场效应晶体管QA）。
于本实施例中，缓冲电路100A的第一端子A电气连接至隔离功率变压器T1的一次侧的一端子，而缓冲电路100A的另一端B则电气连接至隔离功率变压器T1的一次侧的另一端子以及该交换组件诸如上述的开关管（例如：金属氧化物半导体场效应晶体管QA），藉此，在高频切换时由该开关管产生的能量可被缓冲电路100A所吸收以进行能量回收运作。尤其是，缓冲电路100A可利用上述至少一接面特性进行上述的能量回收运作。例如：缓冲电路100A可利用该导通快的特性将漏感能量快速的转移至电容器120中，并利用该恢复时间慢的特性使电容器120中的能量反推回源头。请注意，在进行上述能量回收运作时，缓冲电路100A可利用该变换缓和的特性以及该基极-集电极接面电容Cbc小的特性缩小共振幅度；如此，缓冲电路100A可降低突波电压，并可提供极佳的效率。
图25绘示图3所示的缓冲电路100B于另一实施例中针对图23所示的交换式电源供应器中的隔离功率变压器T1的二次侧的设置方案，其中该设置方案对应于类型TB。相仿地，于图25中，符号G代表接地端子，而符号Vin与Vout分别代表输入电压与输出电压。为了便于理解，图25中是以对应于类型TB的缓冲电路100B作为缓冲电路100的例子来说明。这只是为了说明的目的而已，并非对本发明的限制。该设置方案亦可予以变化，其中，是可根据设置方案的不同而采用分别对应于其它类型TA、TC、TD、TE、TF、TG、TH、TYPE1、TYPE2、TYPE3、与TYPE4的缓冲电路。例如：在采用对应于类型TH的缓冲电路100H的状况下，图25中的端子A与B之间的架构可代换为图9所示者。又例如：在采用对应于类型TYPE2的缓冲电路200B的状况下，图25中的端子A与B之间的架构可代换为图20所示者。
依据本实施例，缓冲电路100B亦可设置于隔离功率变压器T1的二次侧。尤其是，当缓冲电路100B（对应于类型TB）使用于隔离功率变压器T1的二次侧时，缓冲电路100B可和图23所示的输出整流电路的一开关管并联，藉此，在高频切换时由该开关管产生的能量可被缓冲电路100B所吸收，以利用上述至少一接面特性进行能量回收运作。例如：在该开关管是为金属氧化物半导体场效应晶体管QB的状况下，缓冲电路100B可和金属氧化物半导体场效应晶体管QB并联，以保护金属氧化物半导体场效应晶体管QB免受突波电压的破坏，并可提供极佳的效率。又例如：在该开关管是为金属氧化物半导体场效应晶体管QC的状况下，缓冲电路100B可和金属氧化物半导体场效应晶体管QC并联，以保护金属氧化物半导体场效应晶体管QC免受突波电压的破坏，并可提供极佳的效率。这只是为了说明的目的而已，并非对本发明的限制。依据本实施例的某些变化例，该开关管可为一个二极管（其于该些变化例中可取代金属氧化物半导体场效应晶体管QB或QC）。例如：基于该二极管的电压-电流特性，该二极管可随着其跨压自动地开启或关闭，故可视为自动开关管，其中该二极管的两端子的设置方向可依不同的设计而决定。依据本实施例的某些变化例，该开关管可为一双极性结型晶体管(BJT)、一绝缘栅双极晶体管(IGBT)、一静电感应晶体管(SIT)、一闸流体或其组成的电路（其于该些变化例中可取代金属氧化物半导体场效应晶体管QB或QC）。
本发明的好处之一是，本发明的缓冲电路的构造简单且易于实施，同时能避免相关技术的问题。另外，本发明的缓冲电路可并联于一主动组件或一负载以保护负载所连接的电路，例如设置于交换式电源供应器中以保护变压器一次侧连接的交换组件或二次侧连接的输出整流电路，尤其可吸收主动组件在高频切换时所产生的突波或噪声以做能量回收，而可提供极佳的效率，又能确保最高突波电压值，使各种电力／电子组件诸如保护半导体组件获得最佳的保护。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (17)

1.一种缓冲电路，该缓冲电路的特征在于包括有：
至少一阻抗组件；
一电容器，该电容器具有一第一端子与一第二端子，其中该电容器的该第一端子是电气连接至该缓冲电路的一第一端子；以及
一双极性结型晶体管，其中该双极性结型晶体管的发射极与集电极中的一者是电气连接至该电容器的该第二端子，且该双极性结型晶体管
的发射极与集电极中的另一者是电气连接至该缓冲电路的一第二端子；
其中该至少一阻抗组件和该电容器并联、或和该双极性结型晶体管的发射极与集电极并联。
2.如权利要求1所述的缓冲电路，其特征在于，该至少一阻抗组件是为至少一齐纳二极管。
3.如权利要求1所述的缓冲电路，其特征在于，该双极性结型晶体管的基极与发射极是被导通。
4.如权利要求1所述的缓冲电路，其特征在于，基于该双极性结型晶体管的基极与集电极之间的至少一接面特性，该缓冲电路利用该双极性结型晶体管作为一快速二极管。
5.如权利要求4所述的缓冲电路，其特征在于，该至少一接面特性包括导通快的特性以及恢复时间慢的特性，而该缓冲电路利用该导通快的特性将漏感能量快速地转移至该电容器中，且利用该恢复时间慢的特性使该电容器中的能量反推回源头。
6.如权利要求5所述的缓冲电路，其特征在于，该至少一接面特性另包括变换缓和的特性以及基极-集电极接面电容小的特性，而该缓冲电路利用该变换缓和的特性、该基极-集电极接面电容小的特性缩小共振幅度。
7.如权利要求6所述的缓冲电路，其特征在于，该阻抗组件是用来确保最高突波电压值的限制并且用来消耗剩余的能量。
8.如权利要求6所述的缓冲电路，其特征在于，该至少一阻抗组件是为至少一齐纳二极管；以及该至少一齐纳二极管是用来确保最高突波电压值的限制并且用来消耗剩余的能量。
9.一种将一双极性结型晶体管用于一缓冲电路的方法，该方法的特征在于包括有下列步骤：
将该双极性结型晶体管的基极与发射极导通；以及
基于该双极性结型晶体管的基极与集电极之间的至少一接面特性，利用该双极性结型晶体管作为一快速二极管，以供设置于该缓冲电路。
10.如权利要求9所述的方法，其特征在于，该至少一接面特性包括导通快的特性、恢复时间慢的特性、变换缓和的特性以及基极-集电极接面电容小的特性；以及利用该双极性结型晶体管作为该快速二极管的步骤另包括：
利用该导通快的特性将漏感能量快速地转移至该缓冲电路当中的一电容器中，再利用该恢复时间慢的特性使该电容器中的能量反推回源头；以及
利用该变换缓和的特性以及该基极-集电极接面电容小的特性缩小共振幅度。
11.如权利要求10所述的方法，其特征在于，另包括：
利用至少一阻抗组件来确保最高突波电压值的限制并且用来消耗剩余的能量。
12.如权利要求10所述的方法，其特征在于，另包括：
利用至少一齐纳二极管来确保最高突波电压值的限制并且用来消耗剩余的能量。
13.一种缓冲电路，该缓冲电路的特征在于包括有：
一电容器，该电容器具有一第一端子与一第二端子，其中该电容器的该第一端子是电气连接至该缓冲电路的一第一端子；以及
一双极性结型晶体管，其中该双极性结型晶体管的发射极与集电极中的一者是电气连接至该电容器的该第二端子，且该双极性结型晶体管的发射极与集电极中的另一者是电气连接至该缓冲电路的一第二端子。
14.如权利要求13所述的缓冲电路，其特征在于，该双极性结型晶体管的基极与发射极是被导通。
15.如权利要求1或13所述的缓冲电路，其特征在于，该缓冲电路是并联于一主动组件或一负载，该主动组件是为一金属氧化物半导体场效应晶体管、一二极管、一双极性结型晶体管、一绝缘栅双极晶体管、一静电感应晶体管、一闸流体或其组成的电路，而该负载是为一电感、一电阻、一电容或其组成的电路。
16.如权利要求15所述的缓冲电路，其特征在于，当该缓冲电路使用于一变压器的一次侧时，该缓冲电路是并联于变压器的一次侧且串联于至少一开关管。
17.如权利要求15所述的缓冲电路，其特征在于，当该缓冲电路使用于一变压器的二次侧时，该缓冲电路是并联于一输出整流电路的一开关管。
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