CN102832191B - 功率模块封装和具有该功率模块封装的系统模块 - Google Patents

功率模块封装和具有该功率模块封装的系统模块 Download PDF

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CN102832191B
CN102832191B CN201210191200.0A CN201210191200A CN102832191B CN 102832191 B CN102832191 B CN 102832191B CN 201210191200 A CN201210191200 A CN 201210191200A CN 102832191 B CN102832191 B CN 102832191B
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substrate
power module
module package
semiconductor chip
lead frame
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CN102832191A (zh
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金洸洙
李荣基
崔硕文
朴成根
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Abstract

此处公开了一种功率模块封装,该功率模块封装包括:第一衬底,该第一衬底具有安装在该第一衬底上的第一半导体芯片;以及第二衬底,该第二衬底具有安装在该第二衬底上的第二半导体芯片,所述第二衬底与所述第一衬底连接,以使得沿所述第二衬底的厚度方向的侧表面设置在所述第一衬底的上表面上。

Description

功率模块封装和具有该功率模块封装的系统模块
相关申请的交叉引用
本申请要求以申请日为2011年6月17日,名称为“Power Module Packageand System Module Having The Same(功率模块封装和具有该功率模块封装的系统模块)”的韩国专利申请No.10-2011-0058920为优先权,该申请的全部内容在此作为参考结合于本申请。
技术领域
本发明涉及功率模块封装和具有该功率模块封装的系统模块。
背景技术
由于全世界能源消耗的增加,人们已经开始对如何有效地利用有限的能源表现出了极大的兴趣。因此,采用智能功率模块(IPM)以高效地转换能量的转换器在现有家用电器和工业设备中得到了加速应用。随着功率模块的广泛应用,市场要求所需产品具有高集成度和小型化。因此,功率设备和控制设备中设置在同一模块中的一体化功率模块应运而生。
通常,一体化功率模块分为功率设备(例如绝缘栅双极型晶体管(IGBT)和二极管)和控制设备(用于控制功率设备的运转)一起结合在引线框上然后成型的结构,引线框结合在陶瓷衬底上然后功率设备和控制设备结合在引线框上的结构,以及功率设备和控制设备结合在直接覆铜(direct bondingcopper,DBC)衬底上的结构。
但是,如上所述,由于根据现有技术的一体式功率模块具有设置在一个模块中的功率设备和控制设备,功率设备和控制设备不会彼此隔热。因此,与功率设备相比,很可能在易受热和电损坏的控制设备中引起操作失败。另外,当在控制设备中发生操作失败时,由于只有控制设备不能维修和更换,需要整体替换模块,这会引起维护成本的增加。
发明内容
本发明致力于提供一种功率模块封装和具有该功率模块封装的系统模块,该功率模块封装具有只有控制设备能够选择性地更换的结构,该控制设备与功率设备相比易受热和电损坏。
本发明还致力于提供一种具有三维结构的功率模块封装,在三维结构中功率设备和控制设备彼此隔热。
根据本发明的一种优选实施方式,提供一种功率模块封装,该功率模块封装包括:第一衬底,该第一衬底具有安装在该第一衬底上的第一半导体芯片;以及第二衬底,该第二衬底具有安装在该第二衬底上的第二半导体芯片,所述第二衬底与所述第一衬底连接,以使得沿所述第二衬底的厚度方向的侧表面设置在所述第一衬底的上表面上。
所述功率模块封装还可以包括连接单元,该连接单元电连接于所述第一半导体芯片并且形成在所述第一衬底上,所述连接单元具有用于与所述第二衬底连接的至少一个连接槽。
与所述连接槽对应的连接销可以形成在沿所述第二衬底的长度方向的一端上。
此处,彼此面对的第一固定凸起可以形成在所述连接单元的内侧的上部上,并且与所述第一固定凸起对应的第一固定槽可以形成在沿所述第二衬底的长度方向的一端的上部和下部。
所述功率模块封装还可以包括密封树脂,该密封树脂具有插入槽,该插入槽用于露出穿过该插入槽的所述连接单元,并且用于包裹所述第一衬底的侧表面和上表面。
此处,彼此面对的第二固定凸起可以形成在所述插入槽的内侧的上部上,并且与所述第二固定凸起对应的第二固定槽可以形成在沿所述第二衬底的长度方向的一端的上部和下部。
所述功率模块封装还可以包括引线框,该引线框具有埋设在所述密封树脂内并且连接于所述第一衬底的一端,以及凸出于所述密封树脂的另一端。
所述第一半导体芯片和所述第二半导体芯片可以分别为功率设备和控制设备。
所述第一衬底可以为具有阳极氧化层的金属衬底,并且所述金属衬底可以由铝制成。
所述第二衬底可以为印刷电路板。
根据本发明的另一种优选实施方式,提供一种系统模块,该系统模块包括:功率模块封装,该功率模块封装包括第一衬底、第二衬底和引线框,所述第一衬底具有安装在该第一衬底上的第一半导体芯片,所述第二衬底具有安装在该第二衬底上的第二半导体芯片,所述第二衬底与所述第一衬底连接,以使得沿所述第二衬底的厚度方向的侧表面设置在所述第一衬底的上表面上,所述引线框具有连接于所述第一衬底的一端以及凸出到外部的另一端;以及主板衬底,该主板衬底与凸出到外部的所述引线框的另一端连接,以允许所述功率模块封装安装在所述主板衬底上,所述主板衬底具有槽,该槽的尺寸与具有所述第二半导体芯片的所述第二衬底相对应。
此处,所述槽的内侧可以安装有固定件,所述固定件通过支撑所述第二衬底的上表面和下表面以固定所述第二衬底。
所述主板衬底可以具有通孔,所述引线框的另一端插入地贯穿所述通孔,并且所述主板衬底可以通过焊接与贯穿所述通孔的所述引线框的另一端结合。
所述第一半导体芯片和所述第二半导体芯片可以分别为功率设备和控制设备。
所述第一衬底可以为具有阳极氧化层的金属衬底,所述第二衬底可以为印刷电路板。
附图说明
本发明的上述和其它目的、特征和优点将通过下面结合附图的详细描述更加清楚地理解,其中:
图1是显示根据本发明的一种优选实施方式的功率模块封装的结构的横截面视图;
图2是显示根据本发明的一种优选实施方式的功率模块封装的第一衬底的结构的横截面视图;
图3是显示根据本发明的一种优选实施方式的功率模块封装的第二衬底的结构的横截面视图;
图4是显示根据本发明的另一种优选实施方式的功率模块封装的结构的横截面视图;以及
图5是显示具有根据本发明的一种优选实施方式的功率模块封装的系统模块的结构的横截面视图。
具体实施方式
本发明的目的、特征和优点将通过下面结合附图对优选实施方式的详细描述而更加清楚地得到理解。贯穿整个附图,相同的参考标记用于表示相同或相似的部件,忽略其多余的描述。此外,在下面的描述中,术语“第一”、“第二”、“一侧”、“另一侧”等用来区分一个部件和另一个部件,但是这些部件的结构不应该被这些术语所限定。此外,在本发明的描述中,当确定公知技术的详细描述可能使本发明的要点模糊时,对它的描述将被省略。
下面,本发明的优选实施方式将结合附图详细描述。
功率模块封装
图1是显示根据本发明的一种优选实施方式的功率模块封装的结构的横截面视图;图2是显示根据本发明的一种优选实施方式的功率模块封装的第一衬底的结构的横截面视图;图3是显示根据本发明的一种优选实施方式的功率模块封装的第二衬底的结构的横截面视图;以及图4是显示根据本发明的另一种优选实施方式的功率模块封装的结构的横截面视图。
结合图1,根据优选实施方式的功率模块封装包括第一衬底110、第二衬底150、密封树脂117和引线框119。
在本优选实施方式中,第一半导体芯片111可以安装在第一衬底110上。
在本优选实施方式中,第一衬底110可以为具有阳极氧化层110a的金属衬底110b,但并不限定于此。作为示例,第一衬底110可以包括印刷电路板(PCB)、陶瓷衬底和直接覆铜(DBC)衬底。
作为金属衬底110b的材料,例如可以使用与具有非常优秀的热传导特性的铝(Al)或铝合金一样能够以相对较低的成本得到的金属材料。由于金属衬底110b具有非常优秀的热传导特性,因此该金属衬底110b能够作为从第一半导体芯片111辐射热量的热辐射元件。因此,不需要单独的热辐射元件。
另外,阳极氧化层110a通过将铝或铝合金制成的金属衬底110b浸入电解溶液(例如硼酸、磷酸、硫酸、铬酸等)中,然后将阳极施加到金属衬底110b上且将阴极施加到电解溶液中而形成。因此,形成的阳极氧化层具有绝缘性和大约10~30W/Km(瓦每开尔文每米)的相对较高的热传导率。
在本优选实施方式中,由于铝或者铝合金被用于金属衬底110b,可以形成铝阳极氧化层(Al2O3)。
由于阳极氧化层110a具有绝缘特性,因此允许电路层形成在第一衬底110上。另外,阳极氧化层110a可以以比一般的绝缘层薄的厚度形成,以能够减小金属衬底110b和第一半导体芯片111之间的距离,因此能够进一步改善模块的热辐射性能并且能够使模块变薄。
同时,在本优选实施方式中,第一布线图(wiring pattern)113形成在第一衬底110上并且通过引线接合法(wire bonding)而连接于第一半导体芯片111。
第一布线图113可以通过传统的方法形成,例如,化学气相沉积法(Chemical Vapor Deposition,CVD)、物理气相沉积(Physical VaporDeposition,PVD)、电镀或者化学镀(electroless plating)。
此外,第一布线图113可以包括导电材料,比如金属(例如,铝、铝合金、铜、铜合金或者它们的组合物、镍、金或者它们的合金),但不局限于此。
在本优选实施方式中,可控硅整流器(SCR)、功率晶体管、绝缘栅双极型晶体管(IGBT)、金属氧化物半导体(MOS)晶体管、功率整流器、功率调节器、变换器、转换器、或者由它们的组合物形成的高功率半导体芯片或二极管均可以被用作第一半导体芯片111。
此处,虽然图2未图示,但是第一半导体芯片111可以通过使用粘结件(未图示)结合在第一布线图113上,该粘结件(未图示)可以导电也可以非导电。
例如,粘结件可以通过电镀形成,或者可以是导电胶或者导电胶带。另外,粘结件可以是焊料、环氧金属、金属胶、环氧基树脂或具有优秀耐热性的粘结带。
例如,已经商品化和公知的耐高温胶带(诸如玻璃带、硅带、聚四氟乙烯带、不锈箔带、陶瓷带等)可以被用作能够作为粘结件的粘结胶带,粘结件可以由上面所述的材料结合形成,但也不特别局限于此。
在本优选实施方式中,如图2所示,安装在第一布线图113上的第一半导体芯片111通过引线115的接合可以电连接于第一布线图113。同时,它们可以通过倒装焊接(flip chip bonding)而不是采用引线115连接。
此处,通过使用引线115连接第一半导体芯片111和第一布线图113的工序可以通过本领域中公知的球焊(ball bonding)、楔焊(wedge bonding)、针脚式焊(stitch bonding)来实现。
在本优选实施方式中,当连接单元120电连接于第一半导体芯片111时,用于连接第一衬底110和第二衬底150的连接单元120可以设置在第一衬底110上。
连接单元120可以结合在形成于第一衬底110上的第一布线图113上。连接单元120可以通过引线115的接合,与第一半导体芯片111和第一布线图113电连接,如第一半导体芯片111,该连接可以通过倒装焊接安装实现。
此处,连接单元120可以具有用于与第二衬底150连接的至少一个连接槽(未图示),并且优选地,与连接槽(未图示)对应的连接销沿与其连接的第二衬底150的长度方向形成在一端上。
连接槽和连接销的形状可以具有例如已经商品化的阴连接器(femaleconnector)和阳连接器(male connector)的形式,或者插座和销的形式,以能够容易地实现连接和断开。
在本优选实施方式中,如图2所示,彼此面对的第一固定凸起120a可以形成在连接单元120的内侧的上部上。
该单元用于防止第二衬底150从连接单元120偏离。优选地,如图3所示,与第一固定凸起120a对应的第一固定槽150a沿第二衬底150的长度方向形成在一端的上部和下部。
即,如图1所示,当第二衬底150安装在连接单元120上时,第一固定凸起120a固定在第一固定槽150a内,从而防止第二衬底150从连接单元120偏离。此处,第一固定凸起120a可以由弹性件制成,以防止第二衬底150在连接时受到损坏。
再者,与上面的描述相反地,第一固定凸起120a和第一固定槽150a可以分别形成在第二衬底150和连接单元120上。
在本优选实施方式中,第二半导体芯片151可以安装在第二衬底150上。此外,第二衬底150可以为印刷电路板(PCB)。
在本优选实施方式中,如图1所示,第二衬底150与第一衬底110连接,使得沿第二衬底150的厚度方向的侧表面设置在第一衬底110的上表面上。
此处,在如图3所示的第二衬底150的横截面中,厚度方向是指A部分,长度方向是指B部分。
此外,侧表面是指除了衬底的上表面和下表面的表面,而部件则传统地安装在上表面和下表面上。
即如图3所示,第二衬底150以直角垂直竖立地穿过第一衬底110,使得沿第二衬底150的厚度方向A的侧表面沿上下方向设置在第一衬底110上。
此处,连接销(未图示)可以沿第二衬底150的长度方向B形成在一端上,使得具有上述连接槽(未图示)的连接单元120能够与连接销(未图示)连接。
此外,在本优选实施方式中,当第二衬底150与第一衬底110连接时,与第一固定凸起120a对应的第一固定槽150a,和与第二固定凸起117a对应的第二固定槽150b分别沿第二衬底150的长度方向B形成在一端的上部和下部上,使得第一固定凸起120a固定在第一固定槽150a中并且第二固定凸起117a固定在第二固定槽150b中,从而防止第二衬底150从第一衬底110偏离。
此处,第一固定凸起120a和第二固定凸起117a可以由弹性件制成,以防止第二衬底150在连接时受到损坏。
此外,与上面相反,上述的固定凸起可以沿第二衬底150的长度方向B形成在一端的上部和下部上,而与该固定凸起对应的上述固定槽可以形成在连接单元120和密封树脂117的插入槽117b的内侧的上部。
此外,第一固定凸起120a和第一固定槽150a,以及第二固定凸起117a和第二固定槽150b可以同时形成,或者可以只形成两者中的一者。
此外,连接于第二半导体芯片151的第二布线图153也可以形成在第二衬底150内。
第二布线图153可以通过与第一布线图113的形成方法相同的方法形成。第二布线图153可以包括导电材料,比如金属(例如,铝、铝合金、铜、铜合金或者它们的组合物、镍、金或者它们的合金),但不局限于此。
此外,第二半导体芯片151可以通过倒装焊接或引线接合法连接于第二布线图153。
在本优选实施方式中,第二半导体芯片151的示例可以包括用于控制上述高功率半导体芯片的低功率半导体芯片,例如,用于控制功率设备的控制设备。
即,第二衬底150和第一衬底110在三维结构中彼此分开制造并且彼此连接,从而防止由高功率半导体芯片产生的热量对低功率半导体芯片的作用影响,其中,与高功率半导体芯片相比易受热/电损坏的低功率半导体芯片安装在第二衬底150上,而高功率半导体芯片则安装在第一衬底110上。
此外,如上所述,第一衬底110和第二衬底150通过使用例如连接器或者插座的连接单元,容易地彼此连接或者彼此分离,从而有利于第二衬底150的更换,在该第二衬底150上安装具有相对经常故障的低功率半导体芯片。
此外,在本优选实施方式中还可以包括包裹第一衬底110的侧表面和上表面的密封树脂117。
密封树脂117是用于保护包括引线115的第一半导体芯片111免受外部环境影响。例如,环氧塑封料(epoxy molding compound,EMC)等类似物可以用作密封树脂150,但是密封树脂的材料不特别局限于此。
在本优选实施方式中,密封树脂117可以具有插入槽117b,第二衬底150插入该插入槽117b内。与第二衬底150连接的连接单元120可以通过插入槽117b露出。如图2所示,第二固定凸起117a可以形成在插入槽117b的内侧的上部。
与第一固定凸起120a相同,第二固定凸起117a也可以用于防止连接的第二衬底150的偏离,与此对应地如图3所示,优选地,第二固定槽150b也沿第二衬底150的长度方向B形成在一端的上部和下部。
此外,如图1所示,根据本实施方式的功率模块封装还可以包括引线框119,该引线框119具有埋设在密封树脂117中并且电连接于第一衬底110的一端以及凸出于密封树脂117的另一端。
此处,引线框119通常可以由具有高导热特性的铜形成,但不局限于此。
具有功率模块封装的系统模块
图5是显示具有根据本发明的一种优选实施方式的功率模块封装的系统模块的结构的横截面视图。
结合图5,根据本优选实施方式的系统模块200可以包括主板衬底210和安装在其上的功率模块封装100。
主板衬底210可以为印刷电路板(PCB),但是不特别限定于此。
此外,例如电容器、寄存器等的无源器件(passive devices)(未图示)以及功率模块封装100可以设置在主板衬底210上。
功率模块封装100可以包括第一衬底110、第二衬底150和引线框119,第一半导体芯片111安装在第一衬底110上,第二半导体芯片151安装在第二衬底150上,引线框119具有连接于第一衬底110的一端和凸出到外部的另一端。
此处,如图5所示,引线框119凸出到外部的另一端可以与主板衬底210结合。
此处,引线框119的另一端凸出到主板衬底210上,并贯穿形成在主板衬底210上的通孔210a,凸出的引线框119的另一端和主板衬底210使用焊料220焊接结合,以使得功率模块封装100能够与主板衬底210结合。
第一衬底110可以为具有阳极氧化层110a的金属衬底110b,但并不限定于此。作为示例,第一衬底110可以包括印刷电路板(PCB)、陶瓷衬底和直接覆铜(DBC)衬底。
作为金属衬底110b的材料,例如可以使用与具有非常优秀的热传导特性的铝(Al)或铝合金一样能够以相对较低的成本得到的金属材料。其中,阳极氧化层110a可以为铝阳极氧化层(Al2O3)。
此外,第二衬底150可以为印刷电路板(PCB)。
在本优选实施方式中,第二衬底150与第一衬底110连接,使得沿第二衬底150的厚度方向的侧表面设置在第一衬底110的上表面上。
此处,在如图3所示的第二衬底150的横截面中,厚度方向是指A部分,长度方向是指B部分。
此外,侧表面是指除了衬底的上表面和下表面的表面,而部件则传统地安装在上表面和下表面上。
即如图3所示,第二衬底150以直角垂直竖立地穿过第一衬底150,使得沿第二衬底150的厚度方向A的侧表面沿上下方向设置在第一衬底110上。
此外,根据本优选实施方式的功率模块封装100还可以包括用于连接第一衬底110和第二衬底150的连接单元120。连接单元120可以包括形成在第一衬底110上的至少一个连接槽(未图示)。此外,与该连接槽(未图示)对应的连接销可以沿与其连接的第二衬底150的长度方向B形成在一端上。
连接槽(未图示)和连接销(未图示)的形状可以具有例如已经商品化的阴连接器和阳连接器的形式,或者插座和销的形式,以能够容易地实现连接和断开,但是不特别地限定于此。
此处,第一半导体芯片111和第二半导体芯片151分别可以为可控硅整流器(silicon controlled rectifer,SCR)、功率晶体管、绝缘栅双极型晶体管(IGBT)、金属氧化物半导体(MOS)晶体管、功率整流器、功率调节器、变换器、转换器、或者由它们的组合物形成的高功率半导体芯片或二极管。
即,第二衬底150和第一衬底110在三维结构中彼此分开制造并且彼此连接,从而防止由高功率半导体芯片产生的热量对低功率半导体芯片的作用影响,其中,与高功率半导体芯片相比易受热/电损坏的低功率半导体芯片安装在第二衬底150上,而高功率半导体芯片则安装在第一衬底110上。
此外,如上所述,第一衬底110和第二衬底150通过使用例如连接器或者插座的连接单元,容易地彼此连接或者彼此分离,从而有利于第二衬底150的更换,在该第二衬底150上安装具有相对经常故障的低功率半导体芯片。
在本优选实施方式中,贯穿于第二衬底150的端部的槽210b可以形成在如上的主板衬底200中,该第二衬底150与第一衬底110连接。
此处,在功率模块封装100安装在主板衬底200上后,槽210b准备用于更换第二衬底150,该第二衬底150安装具有相对经常故障的低功率半导体芯片151。如图5所示,槽210b的宽度h’可以等于或者大于包括第二半导体芯片151的第二衬底150的高度h。即,槽210b具有使第二衬底150能够贯穿槽210b的宽度h’,该第二衬底150上安装有第二半导体芯片151。
此处,如图5所示,固定件230可以安装在槽210b的内侧,以使得该固定件230能够支撑第二衬底150的上表面和下表面,以固定第二衬底150。
即,固定件230沿箭头方向支撑第二衬底150,从而防止连接于第一衬底110的第二衬底150从一边到另一边摇晃,并且保持第一衬底110和第二衬底150的连接状态。
此处,在功率模块封装100和主板衬底200彼此连接后,固定件230可以安装在形成于主板衬底200内的槽210b的内侧。再者,在第二衬底150更换时,首先拆卸固定件230,然后第二衬底150可以更换,此后固定件230可以再次安装。
如上所述,根据本发明,当控制设备损坏时,只有控制设备能够选择性地更换,从而当功率模块损坏时,能够容易修理并且降低修理成本。
另外,根据本发明,产生高热量的功率设备和易受热的控制设备设置在三维结构中,从而使得热量对控制设备的影响最小化,因此能够提高模块的稳定性和模块的寿命。
另外,根据本发明,由于功率设备和控制设备的三维结构,电路设计的自由度能够增加,从而允许各种附加元件的安装。
此外,根据本发明,通过垂直地设置安装控制装置的控制电路板,可以实现模块的小型化。
尽管出于说明的目的已经公开了本发明的实施方式,可以理解的是本发明并不限于此,在不脱离本发明的范围和精神的情况下,本领域技术人员可以做出各种修改、增加和替换。
因此,任何和所有修改、增加或替换也应该理解为落入本发明的保护范围内,并且本发明的具体范围由附属权利要求公开。

Claims (19)

1.一种功率模块封装,该功率模块封装包括:
第一衬底,该第一衬底具有安装在该第一衬底上的第一半导体芯片;
第二衬底,该第二衬底具有安装在该第二衬底上的第二半导体芯片,所述第二衬底与所述第一衬底连接,以使得沿所述第二衬底的厚度方向的侧表面设置在所述第一衬底的上表面上;以及
连接单元,该连接单元电连接于所述第一半导体芯片并且形成在所述第一衬底上,所述连接单元具有至少一个连接槽,所述第二衬底通过插入到所述至少一个连接槽中而与所述第一衬底连接。
2.根据权利要求1所述的功率模块封装,其中,与所述连接槽对应的连接销形成在沿所述第二衬底的长度方向的一端上。
3.根据权利要求1所述的功率模块封装,其中,彼此面对的第一固定凸起形成在所述连接单元的内侧的上部上。
4.根据权利要求3所述的功率模块封装,其中,与所述第一固定凸起对应的第一固定槽形成在沿所述第二衬底的长度方向的一端的上部和下部。
5.根据权利要求1所述的功率模块封装,其中,该功率模块封装还包括密封树脂,该密封树脂具有插入槽,该插入槽用于露出穿过该插入槽的所述连接单元,并且用于包裹所述第一衬底的侧表面和上表面。
6.根据权利要求5所述的功率模块封装,其中,彼此面对的第二固定凸起形成在所述插入槽的内侧的上部上。
7.根据权利要求6所述的功率模块封装,其中,与所述第二固定凸起对应的第二固定槽形成在沿所述第二衬底的长度方向的一端的上部和下部。
8.根据权利要求5所述的功率模块封装,其中,该功率模块封装还包括引线框,该引线框具有埋设在所述密封树脂内并且连接于所述第一衬底的一端,以及凸出于所述密封树脂的另一端。
9.根据权利要求1所述的功率模块封装,其中,所述第一半导体芯片和所述第二半导体芯片分别为功率器件和控制器件。
10.根据权利要求1所述的功率模块封装,其中,所述第一衬底为具有阳极氧化层的金属衬底。
11.根据权利要求10所述的功率模块封装,其中,所述金属衬底由铝制成。
12.根据权利要求1所述的功率模块封装,其中,所述第二衬底为印刷电路板。
13.一种具有功率模块封装的系统模块,该系统模块包括:
所述功率模块封装,该功率模块封装包括第一衬底、第二衬底和引线框,所述第一衬底具有安装在该第一衬底上的第一半导体芯片,所述第二衬底具有安装在该第二衬底上的第二半导体芯片,所述第二衬底与所述第一衬底连接,以使得沿所述第二衬底的厚度方向的侧表面设置在所述第一衬底的上表面上,所述引线框具有连接于所述第一衬底的一端以及凸出到外部的另一端;以及
主板衬底,该主板衬底与凸出到外部的所述引线框的另一端连接,以允许所述功率模块封装安装在所述主板衬底上,所述主板衬底具有槽,该槽的尺寸与具有所述第二半导体芯片的所述第二衬底相对应。
14.根据权利要求13所述的系统模块,其中,所述槽的内侧安装有固定件,所述固定件通过支撑所述第二衬底的上表面和下表面以固定所述第二衬底。
15.根据权利要求13所述的系统模块,其中,所述主板衬底具有通孔,所述引线框的另一端贯穿插入所述通孔。
16.根据权利要求15所述的系统模块,其中,所述主板衬底通过焊接与贯穿所述通孔的所述引线框的另一端结合。
17.根据权利要求13所述的系统模块,其中,所述第一半导体芯片和所述第二半导体芯片分别为功率器件和控制器件。
18.根据权利要求13所述的系统模块,其中,所述第一衬底为具有阳极氧化层的金属衬底。
19.根据权利要求13所述的系统模块,其中,所述第二衬底为印刷电路板。
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Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8018056B2 (en) * 2005-12-21 2011-09-13 International Rectifier Corporation Package for high power density devices
JP5859906B2 (ja) * 2012-04-20 2016-02-16 三菱電機株式会社 半導体装置および半導体装置の製造方法
US20140264808A1 (en) * 2013-03-15 2014-09-18 Andreas Wolter Chip arrangements, chip packages, and a method for manufacturing a chip arrangement
CN104465603A (zh) 2013-09-23 2015-03-25 台达电子企业管理(上海)有限公司 功率模块
KR101983164B1 (ko) * 2013-12-20 2019-08-28 삼성전기주식회사 전력 반도체 패키지 및 그 제조 방법
US10163687B2 (en) * 2015-05-22 2018-12-25 Qualcomm Incorporated System, apparatus, and method for embedding a 3D component with an interconnect structure
CN106340513B (zh) * 2015-07-09 2019-03-15 台达电子工业股份有限公司 一种集成控制电路的功率模块
US9824959B2 (en) * 2016-03-23 2017-11-21 Texas Instruments Incorporated Structure and method for stabilizing leads in wire-bonded semiconductor devices
CN106098650A (zh) * 2016-07-29 2016-11-09 广东美的制冷设备有限公司 一种智能功率模块及其制造方法
CN106024652A (zh) * 2016-07-29 2016-10-12 广东美的制冷设备有限公司 一种智能功率模块及其制造方法
CN106158801A (zh) * 2016-07-29 2016-11-23 广东美的制冷设备有限公司 一种智能功率模块及其制造方法
CN106067450A (zh) * 2016-07-29 2016-11-02 广东美的制冷设备有限公司 一种智能功率模块及其制造方法
CN106098652A (zh) * 2016-08-19 2016-11-09 广东美的制冷设备有限公司 一种智能功率模块及其制造方法
CN106024651A (zh) * 2016-07-29 2016-10-12 广东美的制冷设备有限公司 一种智能功率模块及其制造方法
CN106505057B (zh) * 2016-11-15 2019-04-30 广东美的制冷设备有限公司 智能功率模块及其制造方法
CN106409799B (zh) * 2016-11-15 2019-04-30 广东美的制冷设备有限公司 智能功率模块及其制造方法
CN106601700A (zh) * 2016-12-30 2017-04-26 广东美的制冷设备有限公司 智能功率模块、智能功率模块的制备方法及电力电子设备
CN106601691A (zh) * 2016-12-30 2017-04-26 广东美的制冷设备有限公司 智能功率模块、智能功率模块的制备方法及电力电子设备
CN107301979A (zh) * 2017-06-21 2017-10-27 广东美的制冷设备有限公司 智能功率模块及具有其的空调器
US10366958B2 (en) 2017-12-28 2019-07-30 Texas Instruments Incorporated Wire bonding between isolation capacitors for multichip modules
US11178772B2 (en) * 2018-03-29 2021-11-16 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier connected with a separate tilted component carrier for short electric connection
KR102552077B1 (ko) 2018-04-23 2023-07-06 현대자동차주식회사 적층형 파워 모듈 및 이의 제조 방법
US11521921B2 (en) * 2019-09-04 2022-12-06 Semiconductor Components Industries, Llc Semiconductor device package assemblies and methods of manufacture
US11632860B2 (en) * 2019-10-25 2023-04-18 Infineon Technologies Ag Power electronic assembly and method of producing thereof
CN110783278B (zh) * 2019-11-04 2023-05-12 汉斯自动化科技(江苏)有限公司 功率半导体模块衬底
US20220102258A1 (en) * 2020-09-30 2022-03-31 Stmicroelectronics S.R.L. Semiconductor device and corresponding method of manufacturing semiconductor devices
CN112908971A (zh) * 2021-01-28 2021-06-04 华进半导体封装先导技术研发中心有限公司 一种半导体封装结构及其制造方法、半导体器件
EP4156253A1 (en) * 2021-09-22 2023-03-29 Infineon Technologies Austria AG Resin encapsulated semiconductor package comprising an external recess with exposed electrical contacts and a semiconductor module using the same
CN114094800B (zh) * 2021-10-29 2024-05-17 广东汇芯半导体有限公司 半导体电路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5199895A (en) * 1992-02-04 1993-04-06 Chang Lien Ker Low insertion force, self-locking connecting apparatus for electrically connecting memory modules to a printed circuit board
US5530623A (en) * 1993-11-19 1996-06-25 Ncr Corporation High speed memory packaging scheme
US5648683A (en) * 1993-08-13 1997-07-15 Kabushiki Kaisha Toshiba Semiconductor device in which a first resin-encapsulated package is mounted on a second resin-encapsulated package

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100723454B1 (ko) * 2004-08-21 2007-05-30 페어차일드코리아반도체 주식회사 높은 열 방출 능력을 구비한 전력용 모듈 패키지 및 그제조방법
KR100442847B1 (ko) * 2001-09-17 2004-08-02 페어차일드코리아반도체 주식회사 3차원 구조를 갖는 전력 반도체 모듈 및 그 제조방법
JP2003179203A (ja) 2001-12-11 2003-06-27 Fuji Electric Co Ltd 電力半導体素子モジュール駆動用回路とその構成方法
KR20060068854A (ko) 2004-12-17 2006-06-21 엘지이노텍 주식회사 집적전력모듈 및 그 제조 공정
KR101203466B1 (ko) * 2006-04-20 2012-11-21 페어차일드코리아반도체 주식회사 전력 시스템 모듈 및 그 제조 방법
KR101489325B1 (ko) * 2007-03-12 2015-02-06 페어차일드코리아반도체 주식회사 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법
JP5169764B2 (ja) 2008-11-19 2013-03-27 トヨタ自動車株式会社 電力変換装置
KR101022906B1 (ko) 2009-07-20 2011-03-16 삼성전기주식회사 전력반도체 모듈 및 그 제조방법
CN201601272U (zh) * 2009-10-01 2010-10-06 番禺得意精密电子工业有限公司 记忆卡连接器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5199895A (en) * 1992-02-04 1993-04-06 Chang Lien Ker Low insertion force, self-locking connecting apparatus for electrically connecting memory modules to a printed circuit board
US5648683A (en) * 1993-08-13 1997-07-15 Kabushiki Kaisha Toshiba Semiconductor device in which a first resin-encapsulated package is mounted on a second resin-encapsulated package
US5530623A (en) * 1993-11-19 1996-06-25 Ncr Corporation High speed memory packaging scheme

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