CN102714199A - 用于使用粘合剂粘结的微部件最优化放置的开槽配置 - Google Patents

用于使用粘合剂粘结的微部件最优化放置的开槽配置 Download PDF

Info

Publication number
CN102714199A
CN102714199A CN2010800532639A CN201080053263A CN102714199A CN 102714199 A CN102714199 A CN 102714199A CN 2010800532639 A CN2010800532639 A CN 2010800532639A CN 201080053263 A CN201080053263 A CN 201080053263A CN 102714199 A CN102714199 A CN 102714199A
Authority
CN
China
Prior art keywords
arrangement
substrate
slit
slits
microcomponent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010800532639A
Other languages
English (en)
Other versions
CN102714199B (zh
Inventor
玛丽·纳多
威普库马·帕特尔
普拉卡什·约托斯卡
约翰·芳曼
约翰·马修·芳曼
马克·韦伯斯特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cisco Technology Inc
Original Assignee
Lightwire LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lightwire LLC filed Critical Lightwire LLC
Priority to CN201510046559.2A priority Critical patent/CN104614819B/zh
Publication of CN102714199A publication Critical patent/CN102714199A/zh
Application granted granted Critical
Publication of CN102714199B publication Critical patent/CN102714199B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B7/00—Mountings, adjusting means, or light-tight connections, for optical elements
    • G02B7/02—Mountings, adjusting means, or light-tight connections, for optical elements for lenses
    • G02B7/025—Mountings, adjusting means, or light-tight connections, for optical elements for lenses using glue
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4236—Fixing or mounting methods of the aligned elements
    • G02B6/4239—Adhesive bonding; Encapsulation with polymer material
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B7/00—Mountings, adjusting means, or light-tight connections, for optical elements
    • G02B7/003—Alignment of optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83234—Applying energy for connecting using means for applying energy being within the device, e.g. integrated heater
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/345—Arrangements for heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness

Abstract

一种用来在组件中改善微部件的粘合剂附加的安排利用在用来支持微部件的衬底的顶面中形成的多个并置狭槽。狭槽用来控制一个粘合剂“点”的流动和“形状”以便迅速和精确附加一个微部件到一个衬底的表面。狭槽在衬底的表面中以给予其自身从一个衬底到另一个的可复制精度的方式形成（优选蚀刻）。其它狭槽（“沟道”）可连同粘结狭槽一起形成，从而使得外来粘合剂材料流入这些沟道并且不散布进入不希望的区域。

Description

用于使用粘合剂粘结的微部件最优化放置的开槽配置
相关申请的交叉引用
本申请要求于2009年12月1日提交的美国临时申请No.61/265,459的优先权，并且该申请通过引用结合在此。
技术领域
本发明涉及一种用来在组件中改善微部件的粘合剂附加的安排，并更特别涉及在微部件有待附加到其上的表面内形成的特定开槽配置的利用，从而改善粘合剂附加的质量和微部件关于组件其余部分的定位精度。
发明背景
在许多集成电路微部件安排中，经常需要在各种组装和/或封装操作期间利用环氧树脂（或任何其它合适粘合剂）将一个部件接合到另一部件。当然，并且为本讨论的目的，假设接合涉及将微部件附加到支撑衬底。将微部件附加到衬底的需要在电子集成电路组件、光学系统子组件、光电安排等中是一个普遍工艺步骤。
由于这些微部件的大小继续收缩，因此增加了用改善的对齐精度放置元件的需要。这在光学或光电安排中特别真实，其中一个或多个微部件形成一个光信号路径的部分，该路径要求中间部件对齐从而维持信号路径完整性。例如在一个硅光子组件中，由于部件例如微透镜和光纤附加到一个共用衬底上，例如绝缘体上硅（SOI）衬底，因此它们需要以亚100nm位置精度相互对齐。
尽管在一个衬底上精确放置这些微部件的能力是一个必需的需求，但在组件寿命期内维持这些位置同样重要。一个给定的组件在其寿命期内受到温度、湿度等的变更是非常可能的，其中这些环境变化可降低粘合剂粘结的质量并导致一个部件相对于另一个移位。解决寿命问题的一个方式是在原附加工艺中利用尽可能薄的粘结线（“粘结线”被定义为被粘结的两个表面之间的粘合剂厚度）。已经发现约几十微米等级的粘结线会提高微部件组件的寿命稳定性。然而，该相对薄的粘结线在与有待相对于粘合剂总体积（相对小）而接合的相对大表面积关联的粘合剂流动的基于摩擦约束（即分子流状态）方面存在问题。这种与少量粘合剂材料相关联的摩擦问题然后也限制可执行的微部件后放置调整量，消除了在许多光学或光电系统中执行主动或半主动对齐的可能性。现有技术中存在用来解决涉及使用环氧树脂或其它粘合剂接合部件的各种问题的安排。于2009年5月7日向Z.Zhu等人颁发的美国专利公开2009/0115039涉及控制用于半导体器件附加的环氧树脂的粘结线厚度。然而，Zhu等人的安排涉及创造相对“厚”的粘结线（与在本环境中期望的“薄”粘结线相反）并围绕一个粘结区的周界使用边界墙从而用作一个堤坝以防止环氧树脂流入不希望的区域。
在本领域中存在涉及防止环氧树脂流入不希望的区域而形成‘毛细管停止’沟槽等的许多其它参考文献。在2003年2月25日向D.W. Sherrer等人颁发的美国专利6,526,204是该技术的示范，其中在“离开”一条光信号路径/光纤支持凹槽的方向上形成了一条沟槽。因此，环氧树脂的任何溢出量将被引导出信号路径并进入毛细管停止沟槽。
然而，这些沟槽在其中具有需要紧密靠近放置的多个部件的情况下具有受限制使用。即，具有其中一个或多个毛细管停止沟槽的内含物在安排中需要过多有价值表面积的许多系统安排。
因此仍需要一种安排以便更好地控制用来将接合微部件接合到衬底的一种粘合剂的应用和控制。
发明概述
本发明解决现有技术中的需要，其涉及一种用来在组件中改善微部件的粘合剂附加的安排，并更特别涉及在微部件有待附加到其上的表面内形成的特定开槽配置的利用，从而改善粘合剂附加的质量和微部件关于组件其余部分的定位精度。
根据本发明，多个并置狭槽用来控制一个粘合剂“点”的流动和“形状”以便精确将微部件附加到衬底的表面上。狭槽在衬底的表面中以给予其自身从一个衬底到另一个的可复制精度的方式形成（优选蚀刻）。额外的狭槽（在下文中称为“沟道”）可连同粘结狭槽一起形成，从而使得外来粘合剂材料将流入这些沟道并且不散布进入不希望的区域。在一个优选实施方案中，沟道被形成为比狭槽更远延伸进入衬底，以便确保溢出粘合剂的全部被容纳。
能够以任何期望的配置（即矩形、圆形等）形成多个狭槽以便定义粘合剂材料的“形状”。在本发明的一个实施方案中，形状被定义为模拟被附加到衬底的微部件的表面拓扑，从而使得微部件将使其自身在粘合剂上自然“定心”，并在衬底上期望位置提供自对齐。
本发明的一方面是形成多个狭槽的单独狭槽的数目和狭槽深度允许形成期望的薄粘合线。另外，沟道的内含物允许在向外方向上（即作为压力的结果）或在向内方向上（即作为表面张力的结果）以可预测和可复制方式控制并约束在有待接合的表面下方的粘合剂流动。
在本发明的一个实施方案中，一个或多个加热器元件（例如电阻带）可嵌入一个或多个狭槽内，从而允许粘合剂材料的局部加热，按需要改变其粘度和/或提供粘合剂的固化。事实上，通过各种元件的加热的选择性控制，多个微部件可附加到一个共用衬底，其中一种热敏粘结材料用来将分离的附加操作排序。即，通过控制加热器元件的“开启”和“关闭”，数个分离微部件可安置在一个共用衬底上，其中每个微部件的粘合通过在每个部件的局部面积中控制粘合剂的温度以一个优选顺序执行。
本发明的一个优点是在支持衬底包括一种材料（例如硅）时，在CMOS器件制造中普遍的一种标准蚀刻工艺可用来形成狭槽。一种常规蚀刻工艺的利用允许狭槽图案从一个衬底到下个衬底的可复制性，因此改善了组件的可制造性。
根据本发明的粘合槽群的使用发现了在纯电气集成电路粘合操作、光学组件或光电安排中的使用。粘合剂材料自身包括如在本领域中为此使用的任何合适环氧树脂或可流动粘合剂。
本发明的其它和进一步实施方案和方面将在以下讨论的过程期间并参考附图变得明显。
附图简述
现在参考附图，其中相似数字在若干图中表示相似部件：
图1是根据本发明的利用多个狭槽形成粘合剂点的一个光学系统的一部分的等距视图；
图2是图1的安排的概略形式的顶视图，其中一个微部件被安置为有待附加到光学衬底上；
图3是图2的安排的侧视图；
图4和图5分别是图2和图3的视图的替代实施方案，展示了用来容纳溢出粘合剂的沟道的内含物；
图6是本发明的一个替代实施方案的等距视图，在此情况下使用了以具体配置形成的多个狭槽来模拟被附加到衬底上的一个微部件的表面积，该配置允许微部件在分布到狭槽上的一个粘合剂点上自定心；
图7是本发明的仍另一实施方案的顶视图，在此情况下将多个加热器元件与狭槽合并，其中粘合剂的局部加热在控制粘合剂的固化中是有用的；以及
图8是本发明的仍另一实施方案的等距视图，利用了与围绕狭槽的一个外围防护沟道结合的多个狭槽。
详细说明
图1是适合使用本发明的开槽附加安排的绝缘体上硅（SOI）光电组件10的一部分的等距视图。组件10包括在衬底14中形成并用来支持微部件例如透镜（未示出）的蚀刻腔12。根据本发明，多个狭槽16在衬底14的顶面18中形成。在一个实施方案中，介电层15可跨越衬底14的表面和使用标准CMOS光刻技术蚀刻进入介电层15的狭槽16来布置。尽管上面讨论的焦点利用光学组件作为实例，但应当理解的是使用狭槽群提供微部件到衬底的附加在电气集成电路系统、光学系统或光电系统中是有用的。
在图1中所示的特定安排中，多个狭槽16包括布置在空腔12的一侧的第一多个狭槽16-1和布置在空腔12相反侧的第二多个狭槽16-2。一个粘合剂“点”20（例如规定体积的环氧树脂或其它合适的可流动的粘合剂材料）示作分布到狭槽16-2上。根据本发明，由于表面张力性质，预定长度和深度（以及槽间间隔）的多个狭槽的利用允许液体粘合剂的量自然取得狭槽的形状。
图2是图1的安排的框图形式的顶视图，其中，一个微部件40被布置为装入空腔12并跨越在衬底14的顶面18中形成（具体而言，穿过布置在衬底14上的介电层15）的狭槽16-1和16-2。在图2中示出了与狭槽16关联的长度l和槽间间隔s。尽管在该具体实例中每个狭槽都被形成为包括近似相同的长度并被蚀刻为近似相同的深度，但应当理解的是在其最一般实施方案中，狭槽可包括不同的长度、深度和间隔，只要它们用来容纳粘合剂材料的流动到适合附加一个特定微部件的一个区域。粘合剂20（例如环氧树脂）示作沿狭槽16并在其中布置的成形材料。在该实例中，微部件40包括布置在一个透镜支架44内的一个光学透镜42，其中透镜自身被放置为位于空腔12内，并且支架44跨越空腔并通过使用沿狭槽16-1和16-2布置的粘合剂20接合到衬底14。
在图3中具体展示了所创造的狭槽16的深度d。再次，在该实例中，由于硅衬底14可用作用于狭槽16的工艺的一个蚀刻停止物，因此每个狭槽都被蚀刻为相同深度d，并被定义为介电层15的厚度。在其最一般形式中，狭槽可被形成为各种形状。事实上，如以下将要讨论的，沟道可与狭槽关联并可更深蚀刻进入衬底。同样在该图中示出了一条单独粘结线的厚度t。根据本发明，用来形成给定数个狭槽的单独狭槽的数目、其长度l和间隔s以及单独狭槽的深度d可被设计为增加粘合剂体积对粘结表面积的比率，同时在粘结区域中维持一条非常薄（即约几十微米或更小的等级）的粘结线。狭槽的大小、形状和数目也可被最优化从而解决各种制造/工艺问题，例如一个具体组件的周期、产量和成本需求。使用根据本发明的狭槽的一个优点是在将微部件（例如透镜支架44）压入在粘合剂点20上的位置时，狭槽16的存在将允许粘合剂保持并以一种受引导的方式散布。
在本发明的另一实施方案中，一个或多个沟道可连同多个狭槽一起形成，其中沟道用来捕捉溢出粘合剂并防止粘合剂材料流入不希望的区域。图4和图5分别是图2和图3的安排的顶视图和侧视图，其中一条溢出沟道17连同狭槽16一起形成。在该具体实施方案中，溢出沟道17被形成为延伸一个更大深度D进入衬底14。这仅被考虑为一个设计选择，并且溢出沟道的深度可以可替代地大约与狭槽自身相同。如同狭槽16，沟道17可使用在CMOS加工中众所周知的一种蚀刻工艺（例如深RIE蚀刻、等离子蚀刻等）或任何其它合适工艺形成。参考图4和5，沟道17关于狭槽16安置，从而使得任何溢出粘合剂20将自然地排入沟道17并且不以其它方式跨衬底14的表面18散布进入不希望的区域。
如上面提到，本发明的一个显著方面是使用可在支持衬底的表面中容易蚀刻的狭槽允许形成粘合剂的各种成形“点”，促进了微部件自定心到衬底。图6展示一个不同SOI组件30的一部分，其在此情况下包括在多个同心圆中形成的狭槽32。如所示，分布体积的粘合剂34然后将在由狭槽32创造的圆形底座之后采取半球形。具有圆形底面形式的拓扑的特定微部件（未示出）然后将紧接着插入粘合剂34上适当位置而自然地自定心。
有可能的是通过改变其温度来修改应用粘合剂的性质。根据本发明的另一实施方案，一个或多个加热器元件（例如电阻带）可连同粘结槽一起形成并用来改变粘合剂局部区域中的温度。图7是本发明的该实施方案的顶视图，其示出了连同狭槽16一起布置的数条电阻带19。多种材料（例如硅、多晶硅、硅化物或金属）可用来形成这些加热器元件。通过另外的电路（未示出），电流可经过条带19，该条带然后将升高狭槽16附近的局部温度。尽管图7示出邻接狭槽16安置的加热器元件的使用，但同样有可能的是将一个加热器元件与狭槽自身一起嵌入。
通过允许加热后的粘合剂保持在一个粘稠状态，可以调整布置在粘合剂上的一个微部件的位置，直到已经实现关于衬底的期望程度对齐。一旦微部件已经被适当地对齐，那么这个或这些加热器元件还可用来激活固化。另外，加热器元件的内含物可用来通过以一个受控制方式“开启”加热器元件中的各种加热器元件提供“局部”加热。事实上，通过控制条带19的“开启”和“关闭”，数个分离微部件可安置在一个共用衬底上，其中通过在每个微部件的局部区域中控制粘合剂的温度，以一个预定顺序执行每个微部件的粘合。
图8是连同关联以上图示描述的相同组件配置（衬底14、空腔12等）的本发明一个替代实施方案的等距视图。在此情况下，附加配置50包括围绕狭槽54的外周形成的一条沟道52，从而协助将液体粘合剂保持在位。沟道52围绕狭槽的边缘54，并示作包括一个顶部沟道部分52-T、一个底部沟道部分52-B和多个侧面沟道部分52-S。
通常，本发明的粘合剂支撑狭槽示作允许粘合剂材料在用来粘结的感兴趣的预定（和有限）区域中可控制和均匀散布。已发现在相对小区域中形成多个这些狭槽的能力减少了表面摩擦并允许薄粘结线形成。狭槽自身的存在增加了表面积/粗糙度以便改善后固化接合强度。在与所填充的环氧树脂材料一起使用时，狭槽在固化之后向环氧树脂的移动提供额外的抵抗。
如在图6的展示中具体示出，形成狭槽的各种配置的能力允许附加组件自定心，提供了部件到衬底的（基本）被动对齐。尽管没有明确示出，但应进一步理解的是以上描述的加热器元件可与任何狭槽配置一起使用，包括图6的同心圆狭槽安排。
最后，尽管此时已经结合已知的示范实施方案详细描述了本发明，但应容易理解本发明不限于所披露的实施方案。相反，可以对本发明进行修改从而纳入以前没有描述但与本发明的精神和范围相称的任何数目的变化、更改、置换或等效安排。因此，不应将本发明视为受前面描述限制，而是仅受附属于此的权利要求的范围限制。

Claims (20)

1.一种用来将微部件粘结到衬底上的安排，该安排包括：
在该衬底的顶面中形成的多个并置狭槽，每个狭槽都具有一个关联的预定长度l并被形成为进入该衬底的顶面的一个关联深度d，该多个狭槽用来容纳和保存预定体积的液体粘合剂材料，该材料适合向该衬底提供该微部件的粘结。
2.如权利要求1所述的安排，其中该安排进一步包括至少一条沟道，该沟道邻接该多个狭槽布置，并用来紧接着该微部件接合到该衬底而捕捉和保持外来液体粘合剂材料。
3.如权利要求2所述的安排，其中该至少一条沟道被形成为围绕该多个狭槽的外围。
4.如权利要求2所述的安排，其中该至少一条沟道被形成为比该多个狭槽更深。
5.如权利要求1所述的安排，其中该多个狭槽被配置为模拟粘结到衬底的微部件的表面的拓扑，该多个狭槽的配置紧接着该微部件粘结到该衬底而提供该微部件关于该多个狭槽的自定心。
6.如权利要求1所述的安排，其中该多个狭槽被蚀刻进入该衬底的顶面中。
7.如权利要求1所述的安排，其中该多个狭槽各自都展现基本相同的长度。
8.如权利要求1所述的安排，其中该多个狭槽中的每个狭槽在该衬底表面下方被形成为基本相同的深度。
9.如权利要求1所述的安排，其中该多个狭槽由基本相同的间隔分离。
10.如权利要求1所述的安排，其中该安排进一步包括
至少一个加热器元件，该加热器元件与多个并置狭槽中的一个狭槽相关联地布置，从而提供布置在该关联狭槽上的该粘合剂材料的局部加热；以及
用来控制该至少一个加热器元件的“开启”和“关闭”的装置。
11.如权利要求10所述的安排，其中该至少一个加热器元件邻接一个关联狭槽而布置。
12.如权利要求10所述的安排，其中该至少一个加热器元件嵌入在一个关联狭槽内。
13.如权利要求10所述的安排，其中该至少一个加热器元件包括一个电阻元件，并且用来控制“开启”和“关闭”的装置包括用来将电流通过该电阻元件的一个开关。
14.如权利要求13所述的安排，其中该电阻元件包括选自下组的一种材料，该组的构成为：硅、多晶硅、硅化物、金属。
15.如权利要求1所述的安排，其中该衬底包括一个电气集成电路衬底。
16.如权利要求1所述的安排，其中该衬底包括一个光学系统衬底。
17.如权利要求16所述的安排，其中该光学系统衬底包括一个绝缘体上硅（SOI）衬底。
18.如权利要求17所述的安排，其中该SOI衬底进一步包括布置在该SOI衬底的顶面上的一个介电层。
19.如权利要求18所述的安排，其中该多个狭槽被蚀刻进入布置在SOI衬底上的该介电层中。
20.如权利要求1所述的安排，其中该衬底包括一个光电系统衬底。
CN201080053263.9A 2009-12-01 2010-11-30 用于使用粘合剂粘结的微部件最优化放置的开槽配置 Active CN102714199B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510046559.2A CN104614819B (zh) 2009-12-01 2010-11-30 用于使用粘合剂粘结的微部件最优化放置的开槽配置

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US26545909P 2009-12-01 2009-12-01
US61/265,459 2009-12-01
US12/955,011 2010-11-29
US12/955,011 US8836100B2 (en) 2009-12-01 2010-11-29 Slotted configuration for optimized placement of micro-components using adhesive bonding
PCT/US2010/058278 WO2011068777A2 (en) 2009-12-01 2010-11-30 Slotted configuration for optimized placement of micro-components using adhesive bonding

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201510046559.2A Division CN104614819B (zh) 2009-12-01 2010-11-30 用于使用粘合剂粘结的微部件最优化放置的开槽配置

Publications (2)

Publication Number Publication Date
CN102714199A true CN102714199A (zh) 2012-10-03
CN102714199B CN102714199B (zh) 2015-03-18

Family

ID=44068222

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201510046559.2A Active CN104614819B (zh) 2009-12-01 2010-11-30 用于使用粘合剂粘结的微部件最优化放置的开槽配置
CN201080053263.9A Active CN102714199B (zh) 2009-12-01 2010-11-30 用于使用粘合剂粘结的微部件最优化放置的开槽配置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201510046559.2A Active CN104614819B (zh) 2009-12-01 2010-11-30 用于使用粘合剂粘结的微部件最优化放置的开槽配置

Country Status (5)

Country Link
US (2) US8836100B2 (zh)
EP (1) EP2507830B1 (zh)
CN (2) CN104614819B (zh)
BR (1) BR112012012778A8 (zh)
WO (1) WO2011068777A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104979186A (zh) * 2014-04-10 2015-10-14 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8836100B2 (en) 2009-12-01 2014-09-16 Cisco Technology, Inc. Slotted configuration for optimized placement of micro-components using adhesive bonding
US9261652B2 (en) 2012-01-17 2016-02-16 Cisco Technology, Inc. Optical components including bonding slots for adhesion stability
US9656439B2 (en) 2013-07-10 2017-05-23 Lumentum Operations Llc Assembly of components having different coefficients of thermal expansion
US9565773B2 (en) 2014-03-31 2017-02-07 Apple Inc. Methods for assembling electronic devices with adhesive
GB2526150B (en) * 2014-05-16 2016-07-13 Xyratex Tech Ltd An optical printed circuit board and a method of mounting a component onto an optical printed circuit board
US10025033B2 (en) 2016-03-01 2018-07-17 Advanced Semiconductor Engineering, Inc. Optical fiber structure, optical communication apparatus and manufacturing process for manufacturing the same
US9933577B2 (en) 2016-03-11 2018-04-03 Globalfoundries Inc. Photonics chip
US10241264B2 (en) 2016-07-01 2019-03-26 Advanced Semiconductor Engineering, Inc. Semiconductor device packages
US11215762B2 (en) 2018-08-15 2022-01-04 Advanced Semiconductor Engineering, Inc. Optical device package and method for manufacturing the same
JP7357595B2 (ja) * 2020-09-17 2023-10-06 三菱電機株式会社 半導体装置および半導体装置の製造方法
US20220199881A1 (en) * 2020-12-17 2022-06-23 Intel Corporation Micro patterns created on the surface to control placement and uniformity of material with viscosity
WO2023217637A1 (en) * 2022-05-09 2023-11-16 X-Celeprint Limited High-precision printed structures and methods of making

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618654A (ja) * 1992-06-30 1994-01-28 Matsushita Electric Works Ltd 受光装置
US5789278A (en) * 1996-07-30 1998-08-04 Micron Technology, Inc. Method for fabricating chip modules
US20040058475A1 (en) * 2002-09-24 2004-03-25 Freund Joseph Michael Devices and method of mounting
US7104129B2 (en) * 2004-02-02 2006-09-12 Invensense Inc. Vertically integrated MEMS structure with electronics in a hermetically sealed cavity
US20060221586A1 (en) * 2005-04-01 2006-10-05 Lingsen Precision Industries, Ltd. Packaging substrate having adhesive-overflowing prevention structure
CN101034726A (zh) * 2006-03-09 2007-09-12 三星电机株式会社 发光二极管封装件

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2310052B (en) * 1996-02-08 2000-01-19 Northern Telecom Ltd Securing an optical fibre in a v-groove
US6535318B1 (en) * 1999-11-12 2003-03-18 Jds Uniphase Corporation Integrated optoelectronic devices having pop-up mirrors therein and methods of forming and operating same
US6215946B1 (en) * 2000-03-16 2001-04-10 Act Microdevices, Inc. V-groove chip with wick-stop trench for improved fiber positioning
US6363201B2 (en) * 2000-03-16 2002-03-26 Haleos, Inc. Fiber array with wick-stop trench for improved fiber positioning
US6404566B1 (en) * 2000-04-04 2002-06-11 Lucent Technologies Inc. Apparatus and method for assembling optical devices
US6848839B2 (en) * 2000-04-07 2005-02-01 Shipley Company, L.L.C. Methods and devices for coupling optoelectronic packages
US6547452B1 (en) * 2000-05-11 2003-04-15 International Business Machines Corporation Alignment systems for subassemblies of overmolded optoelectronic modules
US6526204B1 (en) * 2000-07-11 2003-02-25 Shipley Company Llc Optical fiber array for preventing flow of glue between fibers and waveguide
US6839474B2 (en) * 2000-11-16 2005-01-04 Shipley Company, L.L.C. Optical assembly for coupling with integrated optical devices and method for making
US6432695B1 (en) * 2001-02-16 2002-08-13 Institute Of Microelectronics Miniaturized thermal cycler
US7183195B2 (en) * 2002-02-22 2007-02-27 Samsung Electronics, Co., Ltd. Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler
US6932521B2 (en) * 2002-12-31 2005-08-23 Oplink Communications, Inc. Optical assembly and method for fabrication thereof
US6774415B2 (en) * 2003-01-02 2004-08-10 International Business Machines Corporation Method and structure for ultra-thin film SOI isolation
GB0305890D0 (en) * 2003-03-14 2003-04-16 Bookham Technology Plc Active alignment technique
EP1697987A4 (en) * 2003-11-10 2007-08-08 Henkel Corp ELECTRONIC CONDITIONING MATERIALS FOR SEMICONDUCTOR DEVICES WITH LOW DIELECTRIC CONSTANCE
US7575955B2 (en) * 2004-01-06 2009-08-18 Ismat Corporation Method for making electronic packages
JP4422624B2 (ja) * 2004-03-03 2010-02-24 日本航空電子工業株式会社 微小可動デバイス及びその作製方法
US7545075B2 (en) * 2004-06-04 2009-06-09 The Board Of Trustees Of The Leland Stanford Junior University Capacitive micromachined ultrasonic transducer array with through-substrate electrical connection and method of fabricating same
WO2006081606A1 (en) 2005-02-04 2006-08-10 Redfern Integrated Optics Pty Ltd Optical component and method of attachment
KR100620810B1 (ko) * 2005-03-07 2006-09-07 삼성전자주식회사 Ｍｅｍｓ 소자 패키지 및 그 제조방법
KR100593937B1 (ko) * 2005-03-30 2006-06-30 삼성전기주식회사 Ｓｉ기판을 이용한 ＬＥＤ 패키지 및 그 제조방법
US7447395B2 (en) * 2006-06-15 2008-11-04 Sioptical, Inc. Silicon modulator offset tuning arrangement
US7825501B2 (en) * 2007-11-06 2010-11-02 Fairchild Semiconductor Corporation High bond line thickness for semiconductor devices
US7829966B2 (en) * 2007-11-23 2010-11-09 Visera Technologies Company Limited Electronic assembly for image sensor device
US7821113B2 (en) * 2008-06-03 2010-10-26 Texas Instruments Incorporated Leadframe having delamination resistant die pad
US7981765B2 (en) * 2008-09-10 2011-07-19 Analog Devices, Inc. Substrate bonding with bonding material having rare earth metal
US8119498B2 (en) * 2008-09-24 2012-02-21 Evigia Systems, Inc. Wafer bonding method and wafer stack formed thereby
US8836100B2 (en) 2009-12-01 2014-09-16 Cisco Technology, Inc. Slotted configuration for optimized placement of micro-components using adhesive bonding

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618654A (ja) * 1992-06-30 1994-01-28 Matsushita Electric Works Ltd 受光装置
US5789278A (en) * 1996-07-30 1998-08-04 Micron Technology, Inc. Method for fabricating chip modules
US20040058475A1 (en) * 2002-09-24 2004-03-25 Freund Joseph Michael Devices and method of mounting
US7104129B2 (en) * 2004-02-02 2006-09-12 Invensense Inc. Vertically integrated MEMS structure with electronics in a hermetically sealed cavity
US20060221586A1 (en) * 2005-04-01 2006-10-05 Lingsen Precision Industries, Ltd. Packaging substrate having adhesive-overflowing prevention structure
CN101034726A (zh) * 2006-03-09 2007-09-12 三星电机株式会社 发光二极管封装件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104979186A (zh) * 2014-04-10 2015-10-14 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法

Also Published As

Publication number Publication date
US8836100B2 (en) 2014-09-16
EP2507830B1 (en) 2021-04-21
BR112012012778A8 (pt) 2018-05-08
CN102714199B (zh) 2015-03-18
US20140362457A1 (en) 2014-12-11
WO2011068777A3 (en) 2011-09-22
CN104614819B (zh) 2017-10-31
EP2507830A2 (en) 2012-10-10
WO2011068777A2 (en) 2011-06-09
EP2507830A4 (en) 2018-01-10
BR112012012778A2 (pt) 2017-12-12
US10175448B2 (en) 2019-01-08
CN104614819A (zh) 2015-05-13
US20110127633A1 (en) 2011-06-02

Similar Documents

Publication Publication Date Title
CN102714199B (zh) 用于使用粘合剂粘结的微部件最优化放置的开槽配置
JP6023253B2 (ja) 垂直集積システム
KR101194452B1 (ko) 광전자 기기 상의 마이크로 광학 기기
EP2312357A2 (en) Optical devices and methods of fabricating the same
JP2011014927A (ja) 光電子装置およびその製造方法
US8934745B2 (en) Apparatus for use in optoelectronics having a sandwiched lens
KR20110101059A (ko) 광 센서 모듈의 제조 방법 및 이에 의해서 획득된 광 센서 모듈
CN111316149A (zh) 具有单侧耦合的光子芯片的混合集成
US20160004029A1 (en) Selective component bonding technique
JP2004069824A (ja) 光配線基板
JPH04221865A (ja) 微小素子の固定方法
CN103378011A (zh) 光电子封装及其制造方法
US11300754B2 (en) Offset patterned micro-lens and micro-optical bench including the same
JP2004354947A (ja) 平面光回路部品及びその作製方法
JP2005099382A (ja) 製造方法、及び装置
JP2015204356A (ja) 部品実装基板及び部品実装方法
KR101663640B1 (ko) 다이본딩용 기판 및 이를 사용한 반도체 칩의 다이본딩 방법
JPH10341040A (ja) 光半導体モジュール及びその製造方法
US10514497B2 (en) Photonics packaging method
JPH07287141A (ja) 光回路部品およびその製造方法
JP2013061478A (ja) 光モジュール及びその製造方法
KR20150021871A (ko) 신뢰성있는 웨이퍼레벨 본딩을 위한 캡 웨이퍼 범프 구조물 및 그 제조 방법
WO2006016743A1 (en) Multi chip module and fabrication method therof
JPH10223690A (ja) 光素子の実装方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: CISCO TECH IND.

Free format text: FORMER OWNER: LIGHTWIRE INC.

Effective date: 20130613

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20130613

Address after: American California

Applicant after: Cisco Tech Ind.

Address before: American California

Applicant before: Lightwire, Inc.

C14 Grant of patent or utility model
GR01 Patent grant