WO2006016743A1 - Multi chip module and fabrication method therof - Google Patents

Multi chip module and fabrication method therof Download PDF

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Publication number
WO2006016743A1
WO2006016743A1 PCT/KR2005/002410 KR2005002410W WO2006016743A1 WO 2006016743 A1 WO2006016743 A1 WO 2006016743A1 KR 2005002410 W KR2005002410 W KR 2005002410W WO 2006016743 A1 WO2006016743 A1 WO 2006016743A1
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WIPO (PCT)
Prior art keywords
plate
chip module
multi chip
substrate
module according
Prior art date
Application number
PCT/KR2005/002410
Other languages
French (fr)
Inventor
Ju Haeng Lim
Original Assignee
Lg Innotek Co., Ltd
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Filing date
Publication date
Application filed by Lg Innotek Co., Ltd filed Critical Lg Innotek Co., Ltd
Publication of WO2006016743A1 publication Critical patent/WO2006016743A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0064—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a polymeric substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1034—Edge terminals, i.e. separate pieces of metal attached to the edge of the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment

Definitions

  • the present invention relates to a multi chip module and a fabrication method thereof.
  • Multi chip module refers to a module for minimizing an occupation area of a chip and a circuit on a substrate, thereby realizing miniaturization and simplification.
  • FIG. 1 is a schematic view illustrating a construction of a related art multi chip module.
  • the related art multi chip module includes a plate 11, a lead 13, a substrate 15, a passive element 17, a wire 19, and a signal pattern 21.
  • the lead 13 is connected to the plate 13, and the substrate 15 is adhered to the plate 11 by adherence member (for example epoxy).
  • adherence member for example epoxy
  • the signal pattern 21 and the passive element 17 are formed at the substrate 15.
  • the signal pattern 21 and the passive element 17 are connected with the lead 13 by the wire 19.
  • FIGS. 2 to 5 are process diagrams illustrating the related art process of fabricating the multi chip module.
  • the substrate 15 is formed.
  • the substrate 15 can have the necessary signal pattern 21 formed thereat.
  • the substrate 15 is adhered to a package shown in FIG. 3.
  • the package is comprised of the plate 11 and the lead 13.
  • the substrate 15 is adhered on the plate 11 using the epoxy (for example, sheet epoxy).
  • the substrate 15 is adjusted in position so that the signal pattern 21 formed at the substrate 15 and the lead 13 can be well aligned (Referring to FIG. 4).
  • the substrate 15 is equally rubbed to prevent the generation of a bubble at the epoxy and to disperse epoxy uniformly.
  • the epoxy is cured at a predetermined temperature to firmly adhere the substrate 15 to the plate 11. This process can be performed within an oven.
  • the passive element 17 is die bonded to the signal pattern 21 formed at the substrate 15. Further, the signal pattern 21 formed at the substrate 15 is connected with the lead 13 using the wire 19. At this time, the signal pattern 21 and the passive element 17 formed at the substrate 15 can be also connected using the wire 19.
  • the plate 11 and ⁇ e substrate 15 are mutually adhered using epoxy.
  • the substrate 15 is rubbed to prevent the generation of the bubble at the epoxy while the signal pattern 21 formed on the substrate 15 and the lead 13 can be well controlled and aligned.
  • the substrate 15 is put and rubbed on the plate 11 having the epoxy coated thereon and if so, the substrate 15 generates the motion on the plate 11.
  • the epoxy is completely cured before the substrate 15 is aligned in position on the plate 11, the signal pattern 21 formed at the substrate 15 and the lead 13 are not aligned rightly. This is illustrated in FIG. 6.
  • FIG. 6 illustrates a problem of the related art multi chip module.
  • the present invention is directed to a multi chip module and a fabrication method thereof that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
  • An object of the present invention is to provide a multi chip module for aligning a substrate in a desired position on a plate where the multi chip module is constructed, and a fabrication method thereof.
  • a multi chip module including: a plate; a substrate adhered to the plate, and having a chip and a signal pattern formed thereat; and a stopper formed at the plate, and defining a region where the substrate is adhered.
  • a method of fabricating a multi chip module including: providing a plate connected with a lead, and having a region defined by a stopper; adhering a substrate having a chip and a signal pattern, to the region defined by the stopper on the plate; and wire bonding the signal pattern with the lead.
  • a substrate can be aligned in a desired position on a plate where the multi chip module is constructed. Further, according to the present invention, there is an advantage in that a signal pattern formed at a substrate and a lead can be constantly aligned and therefore, a wire bonding process between the signal pattern and the lead can be efficiently performed.
  • FIG. 1 is a schematic view illustrating a construction of a related art multi chip module.
  • FIGS. 2 to 5 are process diagrams illustrating a related art process of fabricating a multi chip module.
  • FIG. 6 illustrates a problem of a related art multi chip module.
  • FIG. 7 schematically illustrates a construction of a multi chip module according to the present invention.
  • FIGS. 8 to 11 are process diagrams illustrating a process of fabricating a multi chip module according to the present invention.
  • FIG. 12 illustrates a multi chip module according to another embodiment of the present invention.
  • FIG. 13 illustrates a multi chip module according to a further another embodiment of the present invention.
  • FIG. 7 schematically illustrates a construction of a multi chip module according to the present invention.
  • the inventive multi chip module comprises a plate 51, a stopper 51a, a lead 53, a substrate 55, a passive element 57, a wire 59, and a signal pattern 61.
  • the lead 53 is connected to the plate 53, and the substrate 55 is adhered to the plate 51 by adherence member (for example epoxy).
  • the signal pattern 61 and the passive element 57 are formed at the substrate 55.
  • the signal pattern 61 and the passive element 57 are connected with the lead 53 by the wire 59.
  • a plurality of stoppers 51a are formed at the plate 51, and an adherence position of the substrate 55 is determined by the stopper 51a.
  • FIGS. 8 to 11 are process diagrams illustrating the process of fabricating the multi chip module according to the present invention.
  • the substrate 55 is formed.
  • the substrate 55 can have the necessary signal pattern 61 formed thereat.
  • the substrate 55 is adhered to a package shown in FIG. 9.
  • the package is comprised of the plate 51 and the lead 53.
  • the plurality of stoppers 51a are formed at the plate 51.
  • the stopper 51a defines a region at which the substrate 55 is adhered.
  • the stoppers 51a can be formed at outside of the plate 51.
  • the stoppers 51a can be formed at both left and right ends of the plate 51 and at both upper and lower ends of the plate 51.
  • the stoppers 51a can be also formed to have predetermined thicknesses and lengths at portions of the both left and right ends and the both upper and lower ends.
  • the stoppers 51a can be also formed to have predetermined thicknesses, though not illustrated, corresponding to total lengths of the left and right ends and the upper and lower ends of the plate 51.
  • the stopper 51a can be formed in a process of fabricating the plate 51, and this can be easily performed using a process such as a metallic injection. Further, the stopper 51a can be also separately formed to be adhered to the plate 51.
  • the substrate 55 is adhered within the region defined by the stopper 51a.
  • the substrate 55 is adhered on the plate 51 using epoxy (for example, sheet epoxy). It is designed to provide a minute gap between the stopper 51a and a rim of the substrate 55. Accordingly, the substrate 55 can generate a flow only within a determined region and allow a uniform dispersion of the epoxy resulting from a motion of the flow, thereby preventing the generation of a bubble at the epoxy.
  • the adherence position of the substrate 55 is limited by the stopper 51a, thereby naturally solving a drawback of the alignment of the signal pattern 61 formed at the substrate 55, and the lead 53.
  • the epoxy is cured at a predetermined temperature to firmly adhere the substrate 55 to the plate 51.
  • This process can be performed within an oven.
  • the passive element 57 is die bonded to the signal pattern 61 formed at the substrate 55. Further, the signal pattern 61 formed at the substrate 55 is connected with the lead 53 using the wire 59. At this time, the signal pattern 61 and the passive element 57 formed at the substrate 55 can be also connected using the wire 59.
  • the plate 51 and the substrate 55 are mutually adhered using epoxy, and its adherence region is defined and therefore, there is an advantage in that the signal pattern 61 formed on the substrate 55 and the lead 53 can be well aligned naturally.
  • the adherence position of the substrate 55 to the plate 51 can be limited, the alignment of the signal pattern 61 and the lead 53 can be constantly maintained, and their gap can be constantly maintained. Accordingly, a wire bonding process for connecting the signal pattern 61 and the lead 53 can be efficiently performed, and a reliability can be also secured. Further, there does not occur a drawback in the alignment of the plate 51 and the substrate 55 and therefore, the plate 51 and the substrate 55 can be efficiently used without disuse.
  • FIG. 12 illustrates a multi chip module according to another embodiment of the present invention.
  • the inventive multi chip module comprises a plate 51, a lead 53, and a stopper 61a. This is different from the multi chip module of FIG. 7 in that the stopper 61a is different in its formation position.
  • the stoppers 61a are formed at central regions of left and right ends and at central regions of upper and lower ends of the plate 51. Though not illustrated in the drawings, but a substrate to be later adhered is adhered and fixed within a region defined by the stopper 61a. As such, the region where the substrate is adhered is limited by the stopper 61a and accordingly, it is not required to consider an alignment drawback of a signal pattern formed at the substrate and the lead 53.
  • the stopper 61a can be formed in a process of fabricating the plate 51, and this can be easily performed using a process such as a metallic injection. Further, the stopper 61a can be also separately formed to be adhered to the plate 51.
  • FIG. 13 illustrates a multi chip module according to a further another embodiment of the present invention.
  • the inventive multi chip module comprises a plate 51, a lead 53, and a stopper 71a. This is different from the multi chip module of FIG. 7 in that the stopper 71a is different in its formation position.
  • the stoppers 71a are formed at corners where left and right ends of the plate 51 meet with upper and lower ends of the plate 51. Though not illustrated in the drawings, but a substrate to be later adhered is adhered and fixed within a region defined by the stopper 71a. As such, the region where the substrate is adhered is limited by the stopper 71a and accordingly, it is not required to consider an alignment drawback of a signal pattern formed at the substrate and the lead 53.
  • the stopper 71a can be formed in a process of fabricating the plate 51, and this can be easily performed using a process such as a metallic injection. Further, the stopper 71a can be also separately formed to be adhered to the plate 51.

Abstract

A multi chip module and a fabrication method thereof are provided. The multi chip module includes: a plate; a substrate adhered to the plate, and having a chip and a signal pattern formed thereat; and a stopper formed at the plate, and defining a region where the substrate is adhered. The method includes: providing a plate connected with a lead, and having a region defined by a stopper; adhering a substrate having a chip and a signal pattern, to the region defined by the stopper on the plate; and wire bonding the signal pattern with the lead.

Description

[DESCRIPTION] [Invention Title]
MULTI CHIP MODULE AND FABRICATION METHOD THEREOF
[Technical Field]
The present invention relates to a multi chip module and a fabrication method thereof.
[Background Art]
Multi chip module refers to a module for minimizing an occupation area of a chip and a circuit on a substrate, thereby realizing miniaturization and simplification.
FIG. 1 is a schematic view illustrating a construction of a related art multi chip module.
As shown in FIG. 1, the related art multi chip module includes a plate 11, a lead 13, a substrate 15, a passive element 17, a wire 19, and a signal pattern 21.
The lead 13 is connected to the plate 13, and the substrate 15 is adhered to the plate 11 by adherence member (for example epoxy). The signal pattern 21 and the passive element 17 are formed at the substrate 15. The signal pattern 21 and the passive element 17 are connected with the lead 13 by the wire 19.
A related art process of fabricating the above constructed multi chip module will be described with reference to FIGS. 2 to 5. FIGS. 2 to 5 are process diagrams illustrating the related art process of fabricating the multi chip module.
In order to form the related art multi chip module, as shown in FIG. 2, first, the substrate 15 is formed. Here, the substrate 15 can have the necessary signal pattern 21 formed thereat.
After that, the substrate 15 is adhered to a package shown in FIG. 3. Here, the package is comprised of the plate 11 and the lead 13. The substrate 15 is adhered on the plate 11 using the epoxy (for example, sheet epoxy). At this time, the substrate 15 is adjusted in position so that the signal pattern 21 formed at the substrate 15 and the lead 13 can be well aligned (Referring to FIG. 4). The substrate 15 is equally rubbed to prevent the generation of a bubble at the epoxy and to disperse epoxy uniformly.
After that, the epoxy is cured at a predetermined temperature to firmly adhere the substrate 15 to the plate 11. This process can be performed within an oven.
Next, as shown in FIG. 5, the passive element 17 is die bonded to the signal pattern 21 formed at the substrate 15. Further, the signal pattern 21 formed at the substrate 15 is connected with the lead 13 using the wire 19. At this time, the signal pattern 21 and the passive element 17 formed at the substrate 15 can be also connected using the wire 19.
As described above, the plate 11 and ά\e substrate 15 are mutually adhered using epoxy. The substrate 15 is rubbed to prevent the generation of the bubble at the epoxy while the signal pattern 21 formed on the substrate 15 and the lead 13 can be well controlled and aligned.
The substrate 15 is put and rubbed on the plate 11 having the epoxy coated thereon and if so, the substrate 15 generates the motion on the plate 11. However, in case where the epoxy is completely cured before the substrate 15 is aligned in position on the plate 11, the signal pattern 21 formed at the substrate 15 and the lead 13 are not aligned rightly. This is illustrated in FIG. 6.
FIG. 6 illustrates a problem of the related art multi chip module.
In other words, as shown in FIG. 6, in case where the signal pattern 21 formed at the substrate 15 and the lead 15 are not aligned rightly, there can occur a drawback in connecting the signal pattern 21 and the lead 13 using the wire 19. There is a disadvantage in that workability can be deteriorated in wire bonding, and a wire pull value representing a bonding degree of the wire 19 is reduced due to the lengthening of the wire 19, thereby releasing the wire 19 when an environmental test such as an impact test and a vibration test is performed.
In case where the wire bonding process is automatically performed using a bonding machine, in addition to the above mentioned drawback, there is a drawback in that the bonding machine does not rightly detect positions of the lead 13 and the signal pattern 21 and therefore, the wire bonding process itself cannot be rightly performed.
As such, in case where the signal pattern 21 formed at the substrate 15 and the lead 13 are not rightly aligned, there can also occur a case where the substrate 15 should be adhered to the plate 11 again, and a case where the plate 11 and the substrate 15 should be disused.
[Disclosure] [Technical Problem]
Accordingly, the present invention is directed to a multi chip module and a fabrication method thereof that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a multi chip module for aligning a substrate in a desired position on a plate where the multi chip module is constructed, and a fabrication method thereof.
[Technical Solution]
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a multi chip module including: a plate; a substrate adhered to the plate, and having a chip and a signal pattern formed thereat; and a stopper formed at the plate, and defining a region where the substrate is adhered.
In another aspect of the present invention, there is provided a method of fabricating a multi chip module, the method including: providing a plate connected with a lead, and having a region defined by a stopper; adhering a substrate having a chip and a signal pattern, to the region defined by the stopper on the plate; and wire bonding the signal pattern with the lead.
[Advantageous Effects]
According to the present invention, there is an advantage in that a substrate can be aligned in a desired position on a plate where the multi chip module is constructed. Further, according to the present invention, there is an advantage in that a signal pattern formed at a substrate and a lead can be constantly aligned and therefore, a wire bonding process between the signal pattern and the lead can be efficiently performed.
[Description of Drawings]
FIG. 1 is a schematic view illustrating a construction of a related art multi chip module.
FIGS. 2 to 5 are process diagrams illustrating a related art process of fabricating a multi chip module.
FIG. 6 illustrates a problem of a related art multi chip module.
FIG. 7 schematically illustrates a construction of a multi chip module according to the present invention.
FIGS. 8 to 11 are process diagrams illustrating a process of fabricating a multi chip module according to the present invention.
FIG. 12 illustrates a multi chip module according to another embodiment of the present invention.
FIG. 13 illustrates a multi chip module according to a further another embodiment of the present invention.
[Mode for Invention]
Hereinafter, embodiments of the present invention will be described in detail with reference to accompanying drawings.
FIG. 7 schematically illustrates a construction of a multi chip module according to the present invention.
As shown in FIG. 7, the inventive multi chip module comprises a plate 51, a stopper 51a, a lead 53, a substrate 55, a passive element 57, a wire 59, and a signal pattern 61.
The lead 53 is connected to the plate 53, and the substrate 55 is adhered to the plate 51 by adherence member (for example epoxy). The signal pattern 61 and the passive element 57 are formed at the substrate 55. The signal pattern 61 and the passive element 57 are connected with the lead 53 by the wire 59. Further, a plurality of stoppers 51a are formed at the plate 51, and an adherence position of the substrate 55 is determined by the stopper 51a.
A process of fabricating the above constructed multi chip module will be described with reference to FIGS. 8 to 11. FIGS. 8 to 11 are process diagrams illustrating the process of fabricating the multi chip module according to the present invention.
In order to form the inventive multi chip module, as shown in FIG. 8, first, the substrate 55 is formed. Here, the substrate 55 can have the necessary signal pattern 61 formed thereat.
After that, the substrate 55 is adhered to a package shown in FIG. 9. Here, the package is comprised of the plate 51 and the lead 53. The plurality of stoppers 51a are formed at the plate 51. The stopper 51a defines a region at which the substrate 55 is adhered. The stoppers 51a can be formed at outside of the plate 51. The stoppers 51a can be formed at both left and right ends of the plate 51 and at both upper and lower ends of the plate 51. Further, as shown in FIG. 9, the stoppers 51a can be also formed to have predetermined thicknesses and lengths at portions of the both left and right ends and the both upper and lower ends. The stoppers 51a can be also formed to have predetermined thicknesses, though not illustrated, corresponding to total lengths of the left and right ends and the upper and lower ends of the plate 51.
The stopper 51a can be formed in a process of fabricating the plate 51, and this can be easily performed using a process such as a metallic injection. Further, the stopper 51a can be also separately formed to be adhered to the plate 51.
Accordingly, as shown in FIG. 10, the substrate 55 is adhered within the region defined by the stopper 51a. Here, the substrate 55 is adhered on the plate 51 using epoxy (for example, sheet epoxy). It is designed to provide a minute gap between the stopper 51a and a rim of the substrate 55. Accordingly, the substrate 55 can generate a flow only within a determined region and allow a uniform dispersion of the epoxy resulting from a motion of the flow, thereby preventing the generation of a bubble at the epoxy.
In the present invention, the adherence position of the substrate 55 is limited by the stopper 51a, thereby naturally solving a drawback of the alignment of the signal pattern 61 formed at the substrate 55, and the lead 53.
After that, the epoxy is cured at a predetermined temperature to firmly adhere the substrate 55 to the plate 51. This process can be performed within an oven.
Next, as shown in FIG. 11, the passive element 57 is die bonded to the signal pattern 61 formed at the substrate 55. Further, the signal pattern 61 formed at the substrate 55 is connected with the lead 53 using the wire 59. At this time, the signal pattern 61 and the passive element 57 formed at the substrate 55 can be also connected using the wire 59.
In the present invention, as described above, the plate 51 and the substrate 55 are mutually adhered using epoxy, and its adherence region is defined and therefore, there is an advantage in that the signal pattern 61 formed on the substrate 55 and the lead 53 can be well aligned naturally.
Accordingly, in the present invention, the adherence position of the substrate 55 to the plate 51 can be limited, the alignment of the signal pattern 61 and the lead 53 can be constantly maintained, and their gap can be constantly maintained. Accordingly, a wire bonding process for connecting the signal pattern 61 and the lead 53 can be efficiently performed, and a reliability can be also secured. Further, there does not occur a drawback in the alignment of the plate 51 and the substrate 55 and therefore, the plate 51 and the substrate 55 can be efficiently used without disuse.
FIG. 12 illustrates a multi chip module according to another embodiment of the present invention.
As shown in FIG. 12, the inventive multi chip module comprises a plate 51, a lead 53, and a stopper 61a. This is different from the multi chip module of FIG. 7 in that the stopper 61a is different in its formation position.
In other words, in the multi chip module of FIG. 12, the stoppers 61a are formed at central regions of left and right ends and at central regions of upper and lower ends of the plate 51. Though not illustrated in the drawings, but a substrate to be later adhered is adhered and fixed within a region defined by the stopper 61a. As such, the region where the substrate is adhered is limited by the stopper 61a and accordingly, it is not required to consider an alignment drawback of a signal pattern formed at the substrate and the lead 53.
The stopper 61a can be formed in a process of fabricating the plate 51, and this can be easily performed using a process such as a metallic injection. Further, the stopper 61a can be also separately formed to be adhered to the plate 51.
Further, the inventive multi chip module can be also formed as shown in FIG. 13. FIG. 13 illustrates a multi chip module according to a further another embodiment of the present invention.
As shown in FIG. 13, the inventive multi chip module comprises a plate 51, a lead 53, and a stopper 71a. This is different from the multi chip module of FIG. 7 in that the stopper 71a is different in its formation position.
In other words, in the multi chip module of FIG. 13, the stoppers 71a are formed at corners where left and right ends of the plate 51 meet with upper and lower ends of the plate 51. Though not illustrated in the drawings, but a substrate to be later adhered is adhered and fixed within a region defined by the stopper 71a. As such, the region where the substrate is adhered is limited by the stopper 71a and accordingly, it is not required to consider an alignment drawback of a signal pattern formed at the substrate and the lead 53.
The stopper 71a can be formed in a process of fabricating the plate 51, and this can be easily performed using a process such as a metallic injection. Further, the stopper 71a can be also separately formed to be adhered to the plate 51.

Claims

[CLAIMS] [Claim 1]
A multi chip module comprising: a plate; a substrate adhered to the plate, and having a chip and a signal pattern formed thereat; and a stopper formed at the plate, and defining a region where the substrate is adhered.
[Claim 2]
The multi chip module according to claim 1, further comprising a lead connected to the plate.
[Claim 3]
The multi chip module according to claim I1 wherein the lead and the signal pattern are wire bonded.
[Claim 4]
The multi chip module according to claim 1, wherein the chip is die bonded to the substrate.
[Claim 5]
The multi chip module according to claim 1, further comprising a passive element formed at the substrate.
[Claim 6]
The multi chip module according to claim 5, wherein the passive element and the lead are wire bonded.
[Claim 7]
The multi chip module according to claim 1, wherein the stopper is formed in plural.
[Claim 8]
The multi chip module according to claim 1, wherein the stopper is formed outside of the plate.
[Claim 91
The multi chip module according to claim 1, wherein the stoppers are formed at left and right ends and upper and lower ends of the plate.
[Claim 10]
The multi chip module according to claim 8, wherein the stoppers are formed to have predetermined thicknesses and lengths at portions of left and right ends of the plate.
[Claim 11]
The multi chip module according to claim 8, wherein the stoppers are formed to have predetermined thicknesses and lengths at portions of upper and lower ends of the plate.
[Claim 12]
The multi chip module according to claim 8, wherein the stopper is formed at a predetermined thickness to correspond a total length of left and right ends of the plate.
[Claim 13]
The multi chip module according to claim 8, wherein the stopper is formed at a predetermined thickness to correspond a total length of upper and lower ends of the plate.
[Claim 14]
The multi chip module according to claim 8, wherein the stoppers are formed at central portions of left and right ends and central portions of upper and lower ends of the plate.
[Claim 15]
The multi chip module according to claim 8, wherein the stoppers are formed at corners where left and right ends of the plate meet with upper and lower ends of the plate.
[Claim 16]
The multi chip module according to claim 1, wherein the stopper is formed integrally with the plate.
[Claim 17]
The multi chip module according to claim 1, wherein the stopper is separately formed and adhered with the plate.
[Claim 18]
The multi chip module according to claim 1, further comprising an adherence member provided between the substrate and the plate.
[Claim 19]
The multi chip module according to claim 18, wherein the adherence member is epoxy.
[Claim 20]
A method of fabricating a multi chip module, the method comprising: providing a plate connected with a lead, and having a region defined by a stopper; adhering a substrate having a chip and a signal pattern, to the region defined by the stopper on the plate; and wire bonding the signal pattern with the lead.
[Claim 21]
The method according to claim 20, wherein the substrate is adhered to the plate using epoxy.
[Claim 22]
The method according to claim 20, wherein the stopper is formed outside of the plate.
[Claim 23]
The method according to claim 20, wherein the stoppers are formed at left and right ends and upper and lower ends of the plate.
[Claim 24]
The method according to claim 20, wherein the stoppers are formed to have predetermined thicknesses and lengths at portions of left and right ends of the plate.
[Claim 25]
The method according to claim 20, wherein the stoppers are formed at corners where left and right ends of the plate meet with upper and lower ends of the plate.
PCT/KR2005/002410 2004-08-10 2005-07-26 Multi chip module and fabrication method therof WO2006016743A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2004-0062702 2004-08-10
KR1020040062702A KR20060014119A (en) 2004-08-10 2004-08-10 Multi-chip module

Publications (1)

Publication Number Publication Date
WO2006016743A1 true WO2006016743A1 (en) 2006-02-16

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Application Number Title Priority Date Filing Date
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Country Status (3)

Country Link
KR (1) KR20060014119A (en)
TW (1) TW200623346A (en)
WO (1) WO2006016743A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5650544A (en) * 1979-10-01 1981-05-07 Citizen Watch Co Ltd Resin sealing structure for ic
JPS6243156A (en) * 1985-08-20 1987-02-25 Mitsubishi Electric Corp Resin case of semiconductor device
JPH06177314A (en) * 1992-12-08 1994-06-24 Mitsubishi Electric Corp Semiconductor device
JP2000059051A (en) * 1998-08-11 2000-02-25 Murata Mfg Co Ltd Manufacture of chassis structure and jig device used therefor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5650544A (en) * 1979-10-01 1981-05-07 Citizen Watch Co Ltd Resin sealing structure for ic
JPS6243156A (en) * 1985-08-20 1987-02-25 Mitsubishi Electric Corp Resin case of semiconductor device
JPH06177314A (en) * 1992-12-08 1994-06-24 Mitsubishi Electric Corp Semiconductor device
JP2000059051A (en) * 1998-08-11 2000-02-25 Murata Mfg Co Ltd Manufacture of chassis structure and jig device used therefor

Also Published As

Publication number Publication date
KR20060014119A (en) 2006-02-15
TW200623346A (en) 2006-07-01

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