JPH06177314A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06177314A JPH06177314A JP4328099A JP32809992A JPH06177314A JP H06177314 A JPH06177314 A JP H06177314A JP 4328099 A JP4328099 A JP 4328099A JP 32809992 A JP32809992 A JP 32809992A JP H06177314 A JPH06177314 A JP H06177314A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- solder
- parts
- chip
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、ワイヤーとリードフ
レームとの接続部分の信頼性を高くすることができる半
導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of improving the reliability of a connecting portion between a wire and a lead frame.
【０００２】[0002]
【従来の技術】図３〜７は従来の半導体装置の製造工程
を示す斜視図であり、図において、１はリードフレー
ム、２はその接続端子２ａがハンダ３によってリードフ
レーム１にダイボンドされるチップ部品、４はハンダ５
によってリードフレーム１にダイボンドされるＩＣチッ
プ、６はＩＣチップ４の電極とリードフレーム１とを接
続するワイヤー、７はエポキシ系等のモールド用樹脂で
ある。2. Description of the Related Art FIGS. 3 to 7 are perspective views showing a conventional manufacturing process of a semiconductor device. In the drawings, 1 is a lead frame, and 2 is a chip whose connection terminal 2a is die-bonded to a lead frame 1 by a solder 3. Parts 4 and solder 5
Is an IC chip that is die-bonded to the lead frame 1, 6 is a wire that connects the electrode of the IC chip 4 and the lead frame 1, and 7 is a molding resin such as an epoxy resin.
【０００３】上記従来の半導体装置を製造するには、ま
ず、銅系又は鉄系の金属からプレス加工や曲げ加工によ
ってリードフレーム１を製作し、表面にはハンダとのな
じみ向上及びワイヤーボンド性向上のためにメッキを施
しておく（図３参照）。このリードフレーム１をハンダ
が溶融する温度に加熱し、図４に示すようにリードフレ
ーム１上にハンダ３、５を置き、その上にチップ部品
２、ＩＣチップ４を置いて、これらをダイボンドによっ
て固定する。一般に、チップ部品２の接続端子２ａには
ハンダとのなじみを良くするために銀系の金属がメッキ
されており、ＩＣチップ４の裏面に形成された裏面電極
には、ハンダとのなじみを良くするために金等の金属が
メッキされている。In order to manufacture the above conventional semiconductor device, first, a lead frame 1 is manufactured from a copper-based or iron-based metal by press working or bending, and the surface is improved in compatibility with solder and wire bondability. Plating is applied (see Fig. 3). The lead frame 1 is heated to a temperature at which the solder melts, the solders 3 and 5 are placed on the lead frame 1 as shown in FIG. 4, and the chip component 2 and the IC chip 4 are placed on the lead frame 1 by die bonding. Fix it. In general, the connection terminal 2a of the chip component 2 is plated with a silver-based metal to improve compatibility with solder, and the back surface electrode formed on the back surface of the IC chip 4 has good compatibility with solder. In order to do so, a metal such as gold is plated.
【０００４】図４に示した工程においては、リードフレ
ーム１、接続端子２ａ、裏面電極のメッキ面の酸化の状
態によってハンダ付けの良否が左右される。特に、この
工程はリードフレーム１を加熱した状態で行うため、酸
化が加速されやすい。従って一般にこの工程は、フォー
ミングガスと呼ばれる水素ガス等の還元性ガス及び窒素
等の不活性ガスの混合ガス雰囲気中で、酸素を遮断して
酸化を還元しながら行われる。In the process shown in FIG. 4, the quality of soldering depends on the oxidation state of the lead frame 1, the connection terminals 2a, and the plated surface of the back electrode. In particular, since this step is performed while the lead frame 1 is heated, oxidation is likely to be accelerated. Therefore, generally, this step is performed in a mixed gas atmosphere of a reducing gas such as hydrogen gas called a forming gas and an inert gas such as nitrogen while oxygen is blocked and oxidation is reduced.
【０００５】続いて、図５に示すように、ＩＣチップ４
上に設けられている電極（図示せず）とリードフレーム
１の所定位置との間をワイヤー６で接続する。この接続
部分はステッチ部と呼ばれる。ここで、リードフレーム
１上のメッキとワイヤー６とは、それらの間の接続の信
頼性が高くなるような組み合わせにされている。例え
ば、メッキが銀であればワイヤー６としては金が選択さ
れる。Then, as shown in FIG.
An electrode (not shown) provided above and a predetermined position of the lead frame 1 are connected by a wire 6. This connecting portion is called a stitch portion. Here, the plating on the lead frame 1 and the wire 6 are combined so that the connection between them is highly reliable. For example, if the plating is silver, gold is selected as the wire 6.
【０００６】続いて、図５の状態の半製品をモールド用
の金型にセットして加熱した後、加熱されて流動状態と
なっているモールド用樹脂をプレス機から金型に流し込
み、硬化させる。この結果、図６に示すようにモールド
用樹脂７が形成され、内部にモールドされたＩＣチップ
４、チップ部品２やステッチ部等の接続部分が機械的、
環境的に保護される。Subsequently, the semi-finished product in the state shown in FIG. 5 is set in a mold for heating and heated, and then the heated molding resin is poured into the mold from a press machine and cured. . As a result, the molding resin 7 is formed as shown in FIG. 6, and the IC chip 4, the chip component 2 and the connecting portion such as the stitch portion, which are molded inside, are mechanical,
Environmentally protected.
【０００７】さらに、図６の状態のリードフレーム１の
不要部分を切断することによって、図７に示す完成品を
得る。この不要部分は、一般にタイバー部と呼ばれる。Further, by cutting an unnecessary portion of the lead frame 1 in the state shown in FIG. 6, a finished product shown in FIG. 7 is obtained. This unnecessary portion is generally called a tie bar portion.
【０００８】[0008]
【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、以下のような課題があ
った。すなわち、リードフレーム１のメッキの厚さ、平
滑さ、酸化度合等やフォーミングガスの濃度、流量、混
合比等がばらつくため、リードフレーム１へのダイボン
ド用のハンダのなじみ具合が様々であり、なじみ過多や
なじみ不足が発生する場合がある。図８は、なじみ過多
となりハンダがステッチ部７にまで流れ込んだ不具合状
態を示している。また、図９はチップ部品２のダイボン
ドされた位置がステッチ部８に片寄りすぎてしまい、ハ
ンダのなじみは適性であるのにステッチ部８にハンダが
流れ込んだ不具合状態を示している。このように、ステ
ッチ部７、８にハンダが流れ込んだ状態でリードフレー
ム１上にワイヤー６をワイヤーボンドすると、ハンダ面
にワイヤーボンドすることになり、その接合強度が低下
してしまうことになる。Since the conventional semiconductor device is constructed as described above, it has the following problems. That is, since the thickness, smoothness, oxidation degree, etc. of the lead frame 1 and the concentration, flow rate, mixing ratio, etc. of the forming gas vary, the familiarity of the solder for die bonding to the lead frame 1 varies. Excessiveness or lack of familiarity may occur. FIG. 8 shows a defective state in which the solder has flowed into the stitch portion 7 due to excessive fitting. Further, FIG. 9 shows a defect state in which the die-bonded position of the chip component 2 is shifted to the stitch portion 8 too much, and the solder is flowing into the stitch portion 8 although the familiarity of the solder is appropriate. As described above, when the wire 6 is wire-bonded onto the lead frame 1 in a state where the solder flows into the stitch portions 7 and 8, wire bonding is performed on the solder surface, and the bonding strength thereof is reduced.
【０００９】図８や図９に示すような半製品をモールド
する際には、流動状態のモールド用樹脂がワイヤー６に
当たり、ステッチ部７、８に応力が加わる。また、流動
状態のモールド用樹脂が硬化する際にはモールド用樹脂
が収縮するため、やはりステッチ部７、８に応力が加わ
る。さらに、組立工程や検査工程等の後工程において
も、ステッチ部７、８に種々の応力が作用する。このた
め、これらの応力によって不具合の生じたステッチ部
７、８が外れてしまうという課題があった。When molding a semi-finished product as shown in FIGS. 8 and 9, the fluid molding resin hits the wire 6 and stress is applied to the stitch portions 7, 8. Further, when the molding resin in the fluidized state is cured, the molding resin shrinks, so that stress is also applied to the stitch portions 7 and 8. Further, various stresses act on the stitch portions 7 and 8 even in the subsequent steps such as the assembly step and the inspection step. For this reason, there is a problem that the stitch portions 7 and 8 having a defect due to these stresses come off.
【００１０】この発明は、上記のような課題を解消する
ためになされたもので、なじみ過多の場合にステッチ部
にハンダが流れ込まないようにし、またチップ部品の位
置決め精度を向上させてチップ部品の位置ずれによるス
テッチ部へのハンダの流れ込みを防止し、ステッチ部の
信頼性の高い半導体装置を得ることを目的とする。The present invention has been made in order to solve the above-mentioned problems, and prevents solder from flowing into the stitch portion in the case of excessive fitting, and improves the positioning accuracy of the chip component to improve the chip component's positioning accuracy. It is an object of the present invention to prevent a solder from flowing into a stitch portion due to a positional shift and to obtain a semiconductor device having a highly reliable stitch portion.
【００１１】[0011]
【課題を解決するための手段】この発明の半導体装置
は、リードフレーム上に形成され、チップ部品の側面近
傍に設けられたストッパーを有するものである。A semiconductor device according to the present invention has a stopper formed on a lead frame and provided near a side surface of a chip component.
【００１２】[0012]
【作用】この発明の半導体装置においては、ストッパー
が、チップ部品をダイボンドするハンダのワイヤーとリ
ードフレームとの接続部分への流れ込みや、チップ部分
の位置ずれを防止する。In the semiconductor device of the present invention, the stopper prevents the solder for die-bonding the chip component from flowing into the connecting portion between the wire and the lead frame and the positional deviation of the chip portion.
【００１３】[0013]
【実施例】実施例１．図１の(ａ)、(ｂ)はこの発明の一
実施例である実施例１を示す半導体装置のそれぞれ平面
図、側面図であり、図８、図９に示した従来の半導体装
置と同一又は相当部分には同一符号を付し、その説明は
省略する。図において、１１はリードフレーム１に切り
込みを入れ上方に折り曲げて形成されたストッパーとし
ての折り曲げ部である。EXAMPLES Example 1. 1A and 1B are a plan view and a side view, respectively, of a semiconductor device showing a first embodiment which is an embodiment of the present invention, the same as the conventional semiconductor device shown in FIGS. 8 and 9. Alternatively, the same reference numerals are given to corresponding portions, and the description thereof will be omitted. In the figure, reference numeral 11 is a bent portion as a stopper formed by cutting a lead frame 1 and bending it upward.
【００１４】次に、この実施例１の半導体装置の動作に
ついて説明する。折り曲げ部１１は２つ形成され、チッ
プ部品２の側面に左右から当接している。このため、ダ
イボンド用のハンダがなじみ過多となった図８のような
不具合状態においても、ハンダがステッチ部９の方に流
れ込むのを折り曲げ部１１によって防止することができ
る。また、チップ部品２が折り曲げ部１１により位置決
めされ、チップ部品２の搭載位置がずれてステッチ部９
の方に移動して図９のような不具合状態になることがな
いため、この場合にもハンダがステッチ部９に達してし
まうことがない。その結果、ワイヤー６をハンダ面にワ
イヤーボンドしてしまうことがなくなり、ステッチ部の
接合強度が十分確保され、モールド工程や検査工程にお
けるステッチ部の外れ等の発生を防止でき、信頼性の向
上を図ることができる。Next, the operation of the semiconductor device of the first embodiment will be described. Two bent portions 11 are formed and are in contact with the side surface of the chip component 2 from the left and right. Therefore, even in the defective state as shown in FIG. 8 in which the solder for die bonding is excessively adapted, the bent portion 11 can prevent the solder from flowing into the stitch portion 9. Further, the chip component 2 is positioned by the bent portion 11, the mounting position of the chip component 2 is shifted, and the stitch portion 9 is moved.
In this case as well, the solder does not reach the stitch portion 9 because it does not move to the direction of FIG. As a result, the wire 6 is not wire-bonded to the solder surface, the bonding strength of the stitch portion is sufficiently secured, and the stitch portion can be prevented from coming off during the molding process and the inspection process, thus improving the reliability. Can be planned.
【００１５】実施例２．図２の(ａ)、(ｂ)はこの発明の
別の実施例である実施例２を示す半導体装置のそれぞれ
平面図、側面図である。上記実施例１では、折り曲げ部
１１をストッパーとしたが、この実施例２では、リード
フレーム１を下方からプレス加工して形成した打ち上げ
部１２をストッパーとしている。なお、打ち上げ部１２
は、チップ部品２を取り囲む適当な形状で、リードフレ
ーム１の板厚以内の高さに形成される。Example 2. 2A and 2B are a plan view and a side view, respectively, of a semiconductor device showing a second embodiment which is another embodiment of the present invention. In the first embodiment, the bent portion 11 is used as the stopper, but in the second embodiment, the upright portion 12 formed by pressing the lead frame 1 from below is used as the stopper. The launching unit 12
Is a suitable shape surrounding the chip component 2 and is formed within the thickness of the lead frame 1.
【００１６】このように構成された実施例２は、ダイボ
ンド用のハンダのステッチ部１０への流れ込みやチップ
部品２の位置ずれを打ち上げ部１２が防止するので、上
記実施例１と同様の効果を奏する。In the second embodiment having the above-described structure, the punching-up section 12 prevents the die-bonding solder from flowing into the stitch section 10 and the positional deviation of the chip component 2. Therefore, the same effects as those of the first embodiment are obtained. Play.
【００１７】[0017]
【発明の効果】この発明の半導体装置によれば、リード
フレーム上に形成されチップ部品の側面近傍に設けられ
たストッパーを備えたので、チップ部品をダイボンドす
るハンダがワイヤーとリードフレームとの接続部分に流
れ込まないようにし、またチップ部品の位置決め精度を
向上させることによって、ワイヤーとリードフレームと
の接続部分の信頼性を高くすることができるという効果
がある。According to the semiconductor device of the present invention, since the stopper formed on the lead frame and provided in the vicinity of the side surface of the chip component is provided, the solder for die-bonding the chip component is the connecting portion between the wire and the lead frame. It is possible to increase the reliability of the connection portion between the wire and the lead frame by preventing the liquid from flowing into the wire and improving the positioning accuracy of the chip component.
【図１】(ａ)、(ｂ)はそれぞれこの発明の実施例１を示
す半導体装置の平面図及び側面図である。1A and 1B are respectively a plan view and a side view of a semiconductor device showing a first embodiment of the present invention.
【図２】(ａ)、(ｂ)はそれぞれこの発明の実施例２を示
す半導体装置の平面図及び側面図である。2A and 2B are respectively a plan view and a side view of a semiconductor device showing a second embodiment of the present invention.
【図３】リードフレームを示す斜視図である。FIG. 3 is a perspective view showing a lead frame.
【図４】リードフレーム上に搭載される部品を示す斜視
図である。FIG. 4 is a perspective view showing components mounted on the lead frame.
【図５】ワイヤーによってワイヤーボンドされた状態を
示す斜視図である。FIG. 5 is a perspective view showing a state where wires are wire-bonded.
【図６】モールド用樹脂によってモールドされた状態を
示す斜視図である。FIG. 6 is a perspective view showing a state of being molded with a molding resin.
【図７】完成した半導体装置を示す斜視図である。FIG. 7 is a perspective view showing a completed semiconductor device.
【図８】従来の半導体装置の内部構造の一例を示す平面
図である。FIG. 8 is a plan view showing an example of the internal structure of a conventional semiconductor device.
【図９】従来の半導体装置の内部構造の別の例を示す平
面図である。FIG. 9 is a plan view showing another example of the internal structure of the conventional semiconductor device.
１ リードフレーム ２ チップ部品 ３ ハンダ ４ ＩＣチップ ６ ワイヤー １１ 折り曲げ部（ストッパー） １２ 打ち上げ部（ストッパー） 1 Lead frame 2 Chip parts 3 Solder 4 IC chip 6 Wire 11 Bending part (stopper) 12 Launch part (stopper)
Claims (1)
たチップ部品及びＩＣチップと、 一端が前記チップ部品に隣接した前記リードフレーム上
の位置にワイヤーボンドされ、他端が前記ＩＣチップに
接続されたワイヤーと、 を備えた半導体装置において、 前記リードフレーム上に形成され、前記チップ部品の側
面近傍に設けられたストッパーを有することを特徴とす
る半導体装置。1. A lead frame, a chip component and an IC chip die-bonded on the lead frame by solder, one end is wire-bonded to a position on the lead frame adjacent to the chip component, and the other end is the IC. A semiconductor device comprising a wire connected to a chip, comprising a stopper formed on the lead frame and provided near a side surface of the chip component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4328099A JPH06177314A (en) | 1992-12-08 | 1992-12-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4328099A JPH06177314A (en) | 1992-12-08 | 1992-12-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06177314A true JPH06177314A (en) | 1994-06-24 |
Family
ID=18206502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4328099A Pending JPH06177314A (en) | 1992-12-08 | 1992-12-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06177314A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6833607B2 (en) | 2001-11-30 | 2004-12-21 | Oki Electric Industry Co., Ltd. | Resin-molded semiconductor device that includes at least one additional electronic part |
| WO2006016743A1 (en) * | 2004-08-10 | 2006-02-16 | Lg Innotek Co., Ltd | Multi chip module and fabrication method therof |
-
1992
- 1992-12-08 JP JP4328099A patent/JPH06177314A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6833607B2 (en) | 2001-11-30 | 2004-12-21 | Oki Electric Industry Co., Ltd. | Resin-molded semiconductor device that includes at least one additional electronic part |
| WO2006016743A1 (en) * | 2004-08-10 | 2006-02-16 | Lg Innotek Co., Ltd | Multi chip module and fabrication method therof |
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