KR100234164B1 - Lead frame - Google Patents

Lead frame Download PDF

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Publication number
KR100234164B1
KR100234164B1 KR1019970013289A KR19970013289A KR100234164B1 KR 100234164 B1 KR100234164 B1 KR 100234164B1 KR 1019970013289 A KR1019970013289 A KR 1019970013289A KR 19970013289 A KR19970013289 A KR 19970013289A KR 100234164 B1 KR100234164 B1 KR 100234164B1
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South Korea
Prior art keywords
thin film
film layer
lead frame
palladium
nickel
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KR1019970013289A
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Korean (ko)
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KR19980076545A (en
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이규한
박세철
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유무성
삼성항공산업주식회사
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Priority to KR1019970013289A priority Critical patent/KR100234164B1/en
Publication of KR19980076545A publication Critical patent/KR19980076545A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

인너리드부와 아우터리드부를 가지는 금속기판과 상기 금속기판위에 형성된 니켈박막층 상기 니켈박막층 위에 형성된 팔라듐박막층과 상기 니켈 박막층과 팔라듐 박막층 사이에 설치되어 니켈 박막층을 보호하는 보호층을 포함하는 리드프레임과, 상기 인너리드부와 와이어 본딩된 칩과, 상기 칩과 인너리드부를 감싸는 몰딩부재를 포함하는 반도체 패키지를 개시한다. 이 반도체 패키지에 사용되는 리드 프레임은 납땜성을 향상시킬 수 있는 이점을 가진다.A lead frame including a metal substrate having an inner lead portion and an outer lead portion, a nickel thin film layer formed on the metal substrate, and a palladium thin film layer formed on the nickel thin film layer and a protective layer provided between the nickel thin film layer and the palladium thin film layer to protect the nickel thin film layer; Disclosed is a semiconductor package including a chip bonded to the inner lead part and a molding member surrounding the chip and the inner lead part. The lead frame used for this semiconductor package has the advantage of improving solderability.

Description

리드 프레임Lead frame

본 발명은 리드프레임에 관한 것으로서, 더 상세하게는 선도금방법(Pre-Plated Frame)을 적용함에 있어 금속기판의 상면에 적층되는 니켈 박막층을 보호하는 박막층이 개량된 리드 프레임에 관한 것이다.The present invention relates to a lead frame, and more particularly, to a lead frame having an improved thin film layer for protecting a nickel thin film layer laminated on an upper surface of a metal substrate in applying a pre-plated frame.

리드프레임은 반도체 칩과 함께 반도체 팩키지를 이루는 핵심구성요소의 하나로서, 반도체 팩키지의 칩과 외부회로를 연결해주는 도선의 역할과 반도체 칩을 지지해주는 지지체의 역할을 동시에 수행한다. 이러한 반도체 리드프레임은 반도체 칩의 고밀도화, 고집적화 및 기판 실장의 방법 등에 따라 다양한 형상으로 존재할 수 있는데, 기본적인 형상은 제1도에 도시된 바와 같다.The lead frame is one of the core components of the semiconductor package together with the semiconductor chip, and simultaneously serves as a conductor connecting the chip and the external circuit of the semiconductor package and a support for the semiconductor chip. Such a semiconductor lead frame may exist in various shapes according to the method of densification, high integration, and substrate mounting of a semiconductor chip. The basic shape is as shown in FIG. 1.

반도체 리드프레임은 반도체 기억소자인 칩을 탑재하여 정적인 상태를 유지하여 주는 패드부(11)와 와이어 본딩에 의해 연결되는 인너리드부(12) 및 외부 회로와의 연결을 위한 외부리드부(13)로 구성되어 있다. 이와 같은 구조를 갖는 반도체 리드프레임은 통상 스템핑(stamping) 공정 또는 에칭 공정에 의하여 제조된다.The semiconductor lead frame includes a pad 11 for mounting a chip, which is a semiconductor memory device, to maintain a static state, an inner lead 12 connected by wire bonding, and an external lead 13 for connection with an external circuit. It consists of). A semiconductor lead frame having such a structure is usually manufactured by a stamping process or an etching process.

상기 두가지 공정을 이용하여 제조되는 리드 프레임(10)은 도 2에 도시된 바와 같이 패드부에 안착된 칩(40) 등과의 와이어 본딩되고, 와이어 본딩된 칩(40)과 리드 프레임(10)의 인너리드부가 몰드 컴파운드에 의해 몰딩되어 반도체 패키지(15)를 이루게 된다.As shown in FIG. 2, the lead frame 10 manufactured using the above two processes is wire-bonded with the chip 40 mounted on the pad part, and the wire-bonded chip 40 and the lead frame 10 are separated from each other. The inner lead portion is molded by the mold compound to form the semiconductor package 15.

이러한 반도체 패키지의 제조과정중 칩(40)과 리드 프레임(10)의 인너리드부(12)와의 와이어 본딩성과 패드부(11)의 특성을 양호한 상태로 유지하기 위하여 패드부(11)와 리드 프레임의 인너리드부(12)의 단부를 은 등의 금속 소재를 도금한다. 또한 수지 보호막 몰딩후 기판 실장을 위한 납땜성 향상을 위하여 이우터리드부(13)의 소정영역에 솔더(solder) 즉, 주석-납(Sn-Pb) 도금을 실시한다.The pad part 11 and the lead frame in order to maintain the properties of the pad portion 11 and the wire bonding between the chip 40 and the inner lead portion 12 of the lead frame 10 during the manufacturing process of the semiconductor package. A metal material such as silver is plated at the end of the inner lead portion 12 of the metal. In addition, solder molding, that is, tin-lead (Sn-Pb) plating, is performed on a predetermined region of the educted portion 13 to improve solderability for mounting a substrate after molding the protective film.

그런데 이러한 공정을 실시하면 수지 보호막 몰딩후 습식처리과정을 반드시 거쳐야 되고 이로 인하여 완성된 제품의 신뢰성을 저하시키는 문제점이 있다.However, if this process is carried out, the wet protective process must be carried out after molding the resin protective film, which causes a problem of lowering the reliability of the finished product.

상기 문제점을 해결하기 위하여 선도금방법(Pre-Plated Frame)이 제안되었다. 이 방법은 반도체 팩키지 공정이전에 납땜젖음성(solder wettability)이 우수한 소재를 미리 도포하여 중간도금층을 형성하는 방법이다.In order to solve the above problems, a pre-plated frame has been proposed. This method is a method of forming an intermediate plating layer by applying a material having excellent solder wettability in advance before the semiconductor package process.

도 3 내지 도 4에는 이러한 선도금 방법에 의해 제조된 종래 리드 프레임들의 예를 나타내 보였다.3 to 4 show examples of conventional lead frames manufactured by this lead method.

도 3에 도시된 바와 같이 구리 또는 구리합금등의 금속기판(21)위에 중간층인 니켈박막층(22)과 최외곽층인 팔라듐박막층(23)이 순서적으로 적층되어 있으며, 도 4에 도시된 바와 같이 팔라듐 박막층(23)의 상면에 금(Au)으로 이루어진 박막층(24)이 형성된 구조를 가진다.As shown in FIG. 3, the nickel thin film layer 22, which is an intermediate layer, and the palladium thin film layer 23, which is the outermost layer, are sequentially stacked on a metal substrate 21 such as copper or a copper alloy. As described above, the thin film layer 24 made of gold (Au) is formed on the upper surface of the palladium thin film layer 23.

상술한 바와 같이 구성된 리드 프레임은 금속기판(21)의 상면에 도포된 니켈박막층(22)이 구리 또는 구리 합금으로 이루어진 금속기판의 구리 또는 철성분이 표면까지 확산되어 나오는 것이 방지되고, 구리 산화물이나 황화물 등이 생성되는 것이 방지된다. 그리고 상기 팔라듐박막층(23)은 니켈 박막층(22) 표면의 산화를 방지하게 되고, 상기 팔라듐 박막층(23)의 상면에 형성된 금박막층(24)는 납땜성을 향상시키게 된다.The lead frame constructed as described above prevents copper or iron components of the metal substrate made of copper or copper alloy from spreading to the surface of the nickel thin film layer 22 coated on the upper surface of the metal substrate 21, The formation of sulfides and the like is prevented. The palladium thin film layer 23 prevents oxidation of the surface of the nickel thin film layer 22, and the gold thin film layer 24 formed on the upper surface of the palladium thin film layer 23 improves solderability.

그러나 상술한 바와 같이 구성된 리드 프레임은 다음과 같은 문제점이 내재되어 있다.However, the lead frame configured as described above has the following problems.

첫째; 금속기판의 불완전한 표면에 니켈박막층을 도금하여 형성하는 경우 결함부위의 표면에 에너지가 높기 때문에 주위보다 니켈박막층의 도금이 급히 진행되어 주위와의 응집성이 좋지 않다. 특히 상기와 같이 결함부에 형성된 니켈박막층의 표면에 팔라듐박막층 도금하는 경우 팔라듐 석출의 전기적 전위가 수소석출의 전기적 전위와 비슷하므로 팔라듐 석출시 다량의 수소가 혼입되어 팔라듐박막층의 결함이 가속되고, 상기 팔라듐박막층의 결합은 니켈층의 산화로 이어져 납땜성이 좋지 않게 된다.first; When the nickel thin film layer is plated on the incomplete surface of the metal substrate, since the energy is high on the surface of the defective portion, the plating of the nickel thin film layer proceeds more rapidly than the surroundings, resulting in poor cohesion with the surroundings. In particular, when the palladium thin film is plated on the surface of the nickel thin film layer formed in the defect portion as described above, since the electrical potential of the palladium precipitation is similar to the electrical potential of the hydrogen precipitation, a large amount of hydrogen is mixed during the palladium precipitation to accelerate defects of the palladium thin film layer. Bonding of the palladium thin film layer leads to oxidation of the nickel layer, resulting in poor solderability.

둘째; 리드 프레임이 표면실장하기 위하여 아우터 리드부를 성형하는 경우 팔라듐 박막층에 크랙이 발생되고, 이로인하여 상기 니켈박막층이 노출되어 산화되거나 부식되어 납땜성이 저하된다.second; When the outer lead portion is molded to surface mount the lead frame, cracks are generated in the palladium thin film layer, thereby exposing the nickel thin film layer to be oxidized or corroded, thereby reducing solderability.

셋째, 팔라듐 박막층의 상면에 형성된 금 박막층을 이용하여 팔라듐 박막층의 표면을 보호하여 초기 웨팅(wetting)시 팔라듐과 납이 잘 용해되도록 촉진시켜 웨팅 시간(wetting time)을 단축할 수 있으나 실제 아우터 리드부의 실장환경에서 금 박막층에 대한 효과가 떨어진다. 또한 반도체 칩의 패키지에 사용되는 컴파운드와 금 박막층 접합 신뢰성이 좋지 않은 문제점을 가지고 있다.Third, by protecting the surface of the palladium thin film layer by using the gold thin film layer formed on the upper surface of the palladium thin film layer to facilitate the dissolution of palladium and lead during the initial wetting (wetting time) can shorten the wetting time (wetting time) The effect on the gold thin film layer is poor in the mounting environment. In addition, there is a problem that the compound and gold thin film layer bonding reliability used in the package of the semiconductor chip is poor.

본 발명은 상기 문제점을 해결하기 위하여 창출된 것으로, 내부식성과 납땜성이 향상된 리드 프레임을 제공함에 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a lead frame having improved corrosion resistance and solderability.

제1도는 통상적인 반도체 리드프레임을 나타내 보인 개략적인 평면도.1 is a schematic plan view showing a conventional semiconductor leadframe.

제2도는 종래 리드프레임이 장착된 반도체 패키지의 일부절개 사시도.2 is a partially cutaway perspective view of a semiconductor package in which a conventional lead frame is mounted.

제3도 및 제4도는 리드 프레임을 이루는 금속기판의 단면도.3 and 4 are cross-sectional views of the metal substrate constituting the lead frame.

제5도는 본 발명에 따른 반도체 패키지의 단면도.5 is a cross-sectional view of a semiconductor package according to the present invention.

제6도는 본 발명에 따른 리드 프레임을 이루는 금속기판의 단면도.6 is a cross-sectional view of a metal substrate forming a lead frame according to the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

31 : 인너리드부 32 : 아우터 리드부31: inner lead portion 32: outer lead portion

33 : 피드부 34 : 금속기판33: feed part 34: metal substrate

40 : 칩40: chip

상기 목적을 달성하기 위하여 본 발명은, 인너리드부와 아우터 리드부를 가지는 금속기판과, 상기 금속기판에 형성된 니켈박막층, 상기 니켈박막층 위에 형성된 팔라듐박막층과, 상기 니켈 박막층과 팔라듐 박막층 사이에 설치되어 니켈 박막층을 보호하는 보호층을 포함하여 된 것을 특징으로 한다.In order to achieve the above object, the present invention provides a metal substrate having an inner lead portion and an outer lead portion, a nickel thin film layer formed on the metal substrate, a palladium thin film layer formed on the nickel thin film layer, and disposed between the nickel thin film layer and the palladium thin film layer. It characterized by including a protective layer for protecting the thin film layer.

본 발명에 있어서, 상기 보호층은 금을 이용한 박막층으로 이루어진다.In the present invention, the protective layer is made of a thin film layer using gold.

이하 첨부된 도면을 참조하여 본 발명에 따른 한 바람직한 실시예를 상세하게 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

반도체 패키지는 도 5에 도시된 바와 같이 단부에 코인부(31a)가 형성된 복수개의 인너리드부(31)와, 상기 인너리드부(31)로부터 연장되며 외부의 회로와 연결하는 이우터리드부(32), 상기 인너리드부(31)들과 인접되게 설치되며 타이바(도시되지 않음)에 의해 지지되는 패드부(33)를 가지는 금속기판(34)을 포함 리드 프레임(30)과, 상기 패드부(33)에 설치되어 각 코인부와 와이어 본딩되어 전기적으로 접속된 칩(40)과, 상기 칩(40)과 인너리드부(31)를 감싸는 몰딩부재(50)를 포함한다. 상기 리드 프레임(30)를 이루는 금속기판(34) 도 6에 도시된 바와 같이 구리, 구리합금, 철 니켈계합금중 하나로 이루어진 판부재(34a)와, 상기 판부재(34a)의 적어도 일측면에 형성되는 니켈 박막층(34b)와, 상기 니켈 박막층(34b)의 상면에 형성되어 니켈 박막층(34b)을 보호하는 보호층(34c)을 포함한다. 상기 보호층(34c)은 금(Au)으로 이루어진다. 상기 보호층을 이루는 금속은 상기 금(Au)으로 한정되지 않고 니켈박막층을 보호할 수 있는 것이면 가능하다. 예컨대, 상기 보호층은 백금(Pt)으로 형성하여도 무방하다.As shown in FIG. 5, the semiconductor package includes a plurality of inner lead portions 31 having a coin portion 31a formed at an end portion thereof, and an outer lead portion extending from the inner lead portion 31 and connected to an external circuit. 32) a lead frame 30 including a metal substrate 34 installed adjacent to the inner lead portions 31 and having a pad portion 33 supported by a tie bar (not shown); The chip 33 includes a chip 40 installed in the unit 33 and wire-bonded with each coin unit to be electrically connected to the coin unit, and a molding member 50 surrounding the chip 40 and the inner lead unit 31. The metal substrate 34 constituting the lead frame 30, as shown in Figure 6, the plate member 34a made of one of copper, copper alloy, iron nickel-based alloy, and at least one side of the plate member 34a The nickel thin film layer 34b is formed, and a protective layer 34c formed on the upper surface of the nickel thin film layer 34b to protect the nickel thin film layer 34b. The protective layer 34c is made of gold (Au). The metal constituting the protective layer is not limited to the gold (Au), as long as it can protect the nickel thin film layer. For example, the protective layer may be formed of platinum (Pt).

그리고 상기 금으로 이루어진 보호층(34c)이 형성된 판부재(34a)의 상면에는 팔라듐(Pd)으로 이루어진 팔라듐박막층(34d)이 형성된다. 이 팔라듐 박막층(34d)의 형성시 칩(40)이 안착되는 패드부(33)와 와이어가 본딩되는 상기 코인부(coin position; 31a)는 상기 팔라듐 박막층(34d)이 형성되지 않도록 함이 바람직하다. 이는 칩의 안착시 사용되는 Ag 에폭시 수지의 친화력이 팔라듐 도금보다 금도금이 좋기 때문이며 와이어 본딩시 사용되는 금와이어도 팔라듐 도금보다 금도금의 접착 강도가 크기 때문이다.A palladium thin film layer 34d made of palladium (Pd) is formed on an upper surface of the plate member 34a on which the protective layer 34c made of gold is formed. When the palladium thin film layer 34d is formed, the pad portion 33 on which the chip 40 is seated and the coin position 31a where the wire is bonded are preferably such that the palladium thin film layer 34d is not formed. . This is because the affinity of Ag epoxy resin used for chip mounting is better in gold plating than palladium plating, and gold wire used in wire bonding has a larger adhesive strength than gold palladium plating.

상술한 바와 같이 구성된 본 발명에 따른 리드 프레임은 리드 프레임의 패드부에 칩이 장착되고, 이 칩과 인너리부의 코이닝부가 와이어 본딩된다. 이 상태에서 몰드 콤파운드 또는 세라믹에 의해 몰딩된다.In the lead frame according to the present invention configured as described above, a chip is mounted on a pad portion of the lead frame, and the coining portion of the chip and the inner portion is wire bonded. In this state, it is molded by mold compound or ceramic.

상술한 바와 같이 구성된 본 발명에 따른 리드 프레임은 다음과 같은 효과를 가진다.The lead frame according to the present invention configured as described above has the following effects.

첫째; 판부재의 상면에 니켈박막층이 형성되어 있으므로 잔류응력에 의해 에너지의 분포가 불균일하게 되는 것을 방지할 수 있으며 판부재를 이루는 합금원소들이 니켈 박막층에 곧바로 확산되는 것을 방지할 수 있다.first; Since the nickel thin film layer is formed on the upper surface of the plate member, the distribution of energy can be prevented from being uneven due to the residual stress, and the alloying elements constituting the plate member can be prevented from immediately spreading in the nickel thin film layer.

둘째; 니켈 박막층의 표면에 금 또는 백금으로 이루어진 보호층이 형성되어 있으므로 니켈의 산화와 부식을 막아주게 되며, 이로 인하여 회로기판에 반도체 패키지의 실장시 아우터 리드부의 니켈과 납의 접합강도를 향상시킬 수 있다. 즉, 팔라듐 박막층이 금으로 이루어진 보호층에 비하여 전위차가 낮으므로 팔라듐 박막층의 결함 또는 크랙의 발생시 팔라듐 박막층이 희생양극으로 작용하여 보호층을 외부 환경으로부터 보호함으로써 니켈 박막층의 산화 또는 부식을 막아 납과의 결합력을 향상시킬 수 있다.second; Since a protective layer made of gold or platinum is formed on the surface of the nickel thin film layer, it prevents the oxidation and corrosion of nickel, thereby improving the bonding strength of nickel and lead in the outer lead portion when the semiconductor package is mounted on the circuit board. That is, since the palladium thin film layer has a lower potential difference than the protective layer made of gold, the palladium thin film layer acts as a sacrificial anode when a defect or crack occurs in the palladium thin film layer to protect the protective layer from the external environment, thereby preventing oxidation or corrosion of the nickel thin film layer. Can improve the binding force.

셋째; 상기 금으로 이루어진 보호층의 상면에 팔라듐 박막층이 형성되어 있으므로 종래와 같이 Au과 몰드 컴파운드와의 친화력에 의해 몰딩시 몰드 컴파운드가 유출되는 것을 방지할 수 있다.third; Since the palladium thin film layer is formed on the upper surface of the protective layer made of gold, the mold compound may be prevented from flowing out during molding by the affinity between Au and the mold compound as in the related art.

상기한 바와 같이 본 발명은 도면에 도시된 일 실시예를 참고로 설명되었으나 이는 예시적인 것에 불과하며, 본 기술 분야의 통상적 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다.As described above, the present invention has been described with reference to one embodiment shown in the drawings, but this is merely exemplary, and those skilled in the art may realize various modifications and other equivalent embodiments therefrom. Will understand.

Claims (3)

인너리드부와 아웃터 리드부를 포함하는 금속기판과, 상기 금속기판 위에 형성된 니켈 박막층, 상기 니켈 박막층위에 형성된 팔라듐 박막층과, 상기 니켈 박막층과 팔라듐 박막층 사이에 금 또는 백금으로 이루어진 보호층이 형성되어 이루어진 것을 특징으로 하는 리드 프레임.A metal substrate including an inner lead portion and an outer lead portion, a nickel thin film layer formed on the metal substrate, a palladium thin film layer formed on the nickel thin film layer, and a protective layer made of gold or platinum is formed between the nickel thin film layer and the palladium thin film layer. A lead frame characterized by the above. 제1항에 있어서, 상기 기판의 금속소재는 구리, 구리 합금, 철 니켈계합금 중의 하나로 이루어진 것을 특징으로 하는 리드 프레임.The lead frame according to claim 1, wherein the metal material of the substrate is made of one of copper, a copper alloy, and an iron nickel-based alloy. 제1항에 있어서, 상기 인너리드부의 와이어 본딩되는 단부에 팔라듐 박막층의 형성되지 않은 것을 특징으로 하는 리드 프레임.The lead frame according to claim 1, wherein a palladium thin film layer is not formed at the wire bonded end of the inner lead portion.
KR1019970013289A 1997-04-10 1997-04-10 Lead frame KR100234164B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07326701A (en) * 1994-05-31 1995-12-12 Kobe Steel Ltd Conductive material for electric-electronic part, lead frame and semiconductor integrated circuit using the same
KR970700379A (en) * 1993-12-27 1997-01-08 PROTECTIVE COATING COMBINATION FOR LEAD FRAMES

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970700379A (en) * 1993-12-27 1997-01-08 PROTECTIVE COATING COMBINATION FOR LEAD FRAMES
JPH07326701A (en) * 1994-05-31 1995-12-12 Kobe Steel Ltd Conductive material for electric-electronic part, lead frame and semiconductor integrated circuit using the same

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