CN102693968A - 芯片堆叠封装结构 - Google Patents

芯片堆叠封装结构 Download PDF

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CN102693968A
CN102693968A CN2012101655548A CN201210165554A CN102693968A CN 102693968 A CN102693968 A CN 102693968A CN 2012101655548 A CN2012101655548 A CN 2012101655548A CN 201210165554 A CN201210165554 A CN 201210165554A CN 102693968 A CN102693968 A CN 102693968A
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substrate
chip
stack
superposed
circuit trace
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CN102693968B (zh
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刘伟锋
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN201210165554.8A priority Critical patent/CN102693968B/zh
Publication of CN102693968A publication Critical patent/CN102693968A/zh
Priority to EP12877457.7A priority patent/EP2819163B1/en
Priority to PCT/CN2012/083609 priority patent/WO2013174099A1/zh
Priority to US14/552,674 priority patent/US9257358B2/en
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Abstract

本发明提供一种芯片堆叠封装结构，涉及芯片封装技术领域，实现芯片的高密度堆叠，提高芯片堆叠封装结构的散热效率。一种芯片堆叠封装结构，包括：主基板和至少一个叠加基板，所述主基板内设置有主芯片，所述叠加基板上设置有至少一个叠加芯片；所述叠加基板的侧边设置在所述主基板上，使所述叠加芯片与所述主芯片连接。

Description

芯片堆叠封装结构
技术领域
本发明涉及芯片封装技术领域，尤其涉及一种芯片堆叠封装结构。
背景技术
为适应集成电路高密度小型化的要求，芯片堆叠已经成为集成电路发展的趋势。在现有技术中，芯片堆叠方式一般为：将芯片水平放置，并在竖直方向上层层向上进行叠加。芯片之间可以通过激光钻孔实现连接，即在堆叠后的芯片上激光钻孔，然后通过电镀的方式实现芯片之间的连接。
现有技术中的芯片堆叠封装结构，由于芯片水平紧密堆叠在一起，这种堆叠方式使得芯片的散热性能很低。芯片产生的热量只能通过金属走线和芯片本体材料向外传导，导热效率很低，并且由于高功率芯片和低功率芯片叠加在一起，低功率芯片的温度会在高功率芯片的影响下升高，进而影响芯片性能。
发明内容
本发明所要解决的技术问题在于提供一种芯片堆叠封装结构，实现芯片的高密度堆叠，提高芯片堆叠封装结构的散热效率。
一种芯片堆叠封装结构，包括：主基板和至少一个叠加基板，所述主基板内设置有主芯片，所述叠加基板上设置有至少一个叠加芯片；
所述叠加基板的侧边设置在所述主基板上，使所述叠加芯片与所述主芯片连接。
本发明实施例提供的芯片堆叠封装结构，通过将叠加基板的侧边设置在主基板上，实现芯片的高密度堆叠，叠加芯片通过叠加基板侧边设置在主基板上的方式连接到主芯片上，使得叠加基板起到类似与金属散热器中散热齿的作用，在有强迫风冷的情况下，芯片的热量可以很快被带走，同时避免了芯片之间的热量的串扰，可以有效的实现堆叠芯片的高效散热。并且由于叠加基板竖直设置在主基板上，相对于现有技术，叠加芯片与主芯片之间走线的长度被大大缩短，使得芯片封装结构的电学性能得到提高。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的芯片堆叠封装结构的示意图；
图2为本发明实施例中叠加基板排列成一行且相互平行的设置在主基板上的示意图；
图3为本发明实施例中叠加基板排列成两行且相互平行的设置在主基板上的示意图；
图4为本发明实施例中叠加基板延主基板的对角线斜着相互平行的设置在主基板上的示意图；
图5为本发明实施例中散热片设置在所述主基板上示意图；
图6为本发明实施例中金属散热器设置在所述主基板上示意图；
图7为本发明实施例中叠加基板排列成一行设置在金属散热器的两边的示意图；
图8为本发明实施例中叠加芯片设置在叠加基板内部的示意图；
图9为本发明实施例中叠加芯片设置在叠加基板表面的示意图；
图10为本发明实施例中主芯片设置在主基板表面的示意图；
图11为本发明实施例中叠加基板双面设置有铜箔的示意图；
图12为本发明实施例中叠加基板单面覆盖有铜箔的示意图；
图13为本发明实施例中主基板的结构示意图；
图14为本发明实施例中叠加基板的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种芯片堆叠封装结构，如图1所示，该结构包括：
主基板1和至少一个叠加基板2，所述主基板1内设置有主芯片3，所述叠加基板2上设置有至少一个叠加芯片4；
所述叠加基板2的侧边设置在所述主基板1上，使所述叠加芯片4与所述主芯片3连接。
在本发明实施例中，叠加基板2的侧边设置在所述主基板1上，这种结构类似于金属散热器的结构，叠加基板2起到类似与金属散热器中散热齿的作用，叠加基板2可以垂直或以任意角度设置在主基板1上。
本发明实施例提供的芯片堆叠封装结构，通过将叠加基板的侧边设置在主基板上，实现芯片的高密度堆叠，这种设置方式使得叠加基板起到类似与金属散热器中散热齿的作用，在有强迫风冷的情况下，芯片的热量可以很快被带走，同时避免了芯片之间(叠加芯片与主芯片之间或者叠加芯片之间)的热量的串扰，可以有效的实现堆叠芯片的高效散热。并且由于叠加基板的侧边设置在主基板上，相对于现有技术，叠加芯片与主芯片之间走线的长度被大大缩短，使得芯片封装结构的电学性能得到提高。
在本发明实施例中，如图1至图7所示，叠加基板2垂直设置在所述主基板1上，使得叠加芯片以竖直的方式连接到主芯片上，进而实现芯片的高密度堆叠并能够进一步提高散热效率。
进一步的，本发明实施例提供的芯片堆叠封装结构包括：多个所述叠加基板2，多个叠加基板2之间留有间隔。叠加基板2可按照多种布局竖直设置在主基板1上，例如，如图2所示，叠加基板2可排列成一行且相互平行的设置在主基板1上；如图3所示，叠加基板2可排列成两行设置在主基板1上，且每行的叠加基板2之间相互平行；如图4所示，叠加基板2可延主基板1的对角线斜着相互平行的设置在主基板1上。在本发明实施例中，叠加基板的布局并不局限于上述三种方式，叠加基板在主基板上的具体布局方式在这里不做限定。
进一步的，本发明实施例提供的芯片堆叠封装结构，如图5所示，还包括：至少一个散热片6，所述散热片6设置在所述主基板1上，散热片与所述叠加基板2之间设置有间隔。当叠加基板垂直设置时，散热片可以同时垂直主机板设置，从而保证散热片与叠加基板之间能够留有间隔。
散热片6可以和叠加基板2混合设置在主基板1上，散热片6起到类似与金属散热器中散热齿的作用，可以进一步增强芯片堆叠封装结构的散热。
进一步的，本发明实施例提供的芯片堆叠封装结构，如图6和图7所示，还包括：金属散热器7，所述金属散热器7设置在所述主基板1上与所述主芯片设置位置相对应，金属散热器7与叠加基板2之间留有间隔。
主基板1中间区域可以预留一些空间，用于安装金属散热器7，叠加基板2围绕所述金属散热器设置，这样可以更有效的实现对叠加芯片和主芯片的散热。金属散热器7可按照多种布局竖直设置在主基板1上，例如，如图6所示，金属散热器7可以设置在主基板1的中间区域，叠加基板2可排列成两行设置在金属散热器7的两边，或如图7所示，叠加基板2可排列成一行设置在金属散热器7的两边。在本发明实施例中，金属散热器和叠加基板的布局并不局限于上述方式，金属散热器和叠加基板的具体布局方式在这里不做限定。
进一步的，在本发明实施例中，所述叠加芯片设置在所述叠加基板的表面或内部，如图8所示，叠加芯片4可以埋入叠加基板2的内部，或如图9所示，叠加芯片4可以表贴在叠加基板2的表面。
主芯片设置在主基板的表面或设置在主基板的内部。如图10所示，主芯片3可以表贴在主基板1的表面。若主芯片3设置在所述主基板1的表面，则主基板的中间区域（即主芯片所在区域）可以不设置叠加基板，而用来设置金属散热器，或者在主基板1的中间区域以跨界的形式设置叠加基板2，即叠加基板2位于主芯片上方的区域21不与主基板1连接，而通过叠加基板2上跨过主芯片的区域22与主基板1连接。
所述叠加基板与所述散热片的单面或双面覆盖有铜箔，表面覆盖铜箔，进一步提高叠加基板和散热片的散热能力，如图11所示，叠加基板2可以双面设置有铜箔5，如图12所示，叠加基板2可以单面覆盖有铜箔5，另一表面设置叠加芯片4。
进一步的，在本发明实施例中，如图13所示，所述主基板1包括：主芯片基板12、电路走线11、层压片18、主芯片3、芯片连接区域17、下表面基板19和设置有多个连接孔洞16的上表面基板15，电路走线11设置在主芯片基板12的上下两个表面，电路走线11可以为多层，多层电路走线通过层压片相互隔开，层压片可以为半固化片，主芯片3设置在主芯片基板12的上表面上，并与电路走线11连接，层压片18设置在主芯片基板12上表面的电路走线11上，上表面基板15设置在主芯片3和层压片18上，下表面基板19设置在主芯片基板12下表面的电路走线下，多个连接孔洞16的位置与主芯片3的输入输出接口的位置和电路走线11的位置分别相对应，连接孔洞16内设置有导电介质，导电介质与主芯片3的输入输出接口或电路走线11连接，芯片连接区域17覆盖在连接孔洞16的远离主芯片3一侧的端口外，并与导电介质连接，即芯片连接区域17通过连接孔洞16与主芯片3的输入输出接口或电路走线11连接，芯片连接区域17用于连接叠加基板。
如图14所示，所述叠加基板2包括：叠加芯片基板22、电路走线21、层压片28、叠加芯片4、外接走线、焊盘27、下表面基板29和设置有多个连接孔洞26的上表面基板25，电路走线21设置在叠加芯片基板22的上下两个表面，电路走线21可以为多层，多层电路走线通过层压片相互隔开，层压片可以为半固化片，叠加芯片4设置在叠加芯片基板22的上表面上，并与电路走线21连接，层压片28设置在叠加芯片基板22上表面的电路走线21上，上表面基板25设置在叠加芯片4和层压片28上，下表面基板29设置在叠加芯片基板22下表面的电路走线21下，多个连接孔洞26的位置与叠加芯片4的输入输出接口的位置和电路走线21的位置分别相对应，连接孔洞26内设置有导电介质，导电介质与叠加芯片4的输入输出接口或电路走线21连接，焊盘27设置在上表面基板25的外侧面（即远离叠加芯片和电路走线的一侧）的底端（图中右侧），焊盘27用于连接主基板，外接走线设置在上表面基板25的外侧面上，外接走线的两端分别与焊盘和导电介质连接，即焊盘27通过外接走线和连接孔洞26与叠加芯片4的输入输出接口和电路走线21连接。
本发明实施例提供的芯片堆叠封装结构，通过将叠加基板垂直设置在主基板上，实现芯片的高密度堆叠，叠加芯片以竖直的方式连接到主芯片上，使得叠加基板起到类似与金属散热器中散热齿的作用，在有强迫风冷的情况下，芯片的热量可以很快被带走，同时避免了芯片之间的热量的串扰，并在主基板上设置专门用于散热的散热片或金属散热器，可以有效的实现堆叠芯片的高效散热。并且由于叠加基板竖直设置在主基板上，相对于现有技术，叠加芯片与主芯片之间走线的长度被大大缩短，使得芯片封装结构的电学性能得到提高。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (9)

1.一种芯片堆叠封装结构，其特征在于，包括：主基板和至少一个叠加基板，所述主基板内设置有主芯片，所述叠加基板上设置有至少一个叠加芯片；
所述叠加基板的侧边设置在所述主基板上，使所述叠加芯片与所述主芯片连接。
2.根据权利要求1所述的结构，其特征在于，所述叠加基板垂直设置在所述主基板上。
3.根据权利要求1或2所述的结构，其特征在于，所述至少一个叠加基板包括：多个所述叠加基板，多个所述叠加基板之间留有间隔。
4.根据权利要求3所述的结构，其特征在于，所述结构还包括：至少一个散热片，所述散热片设置在所述主基板上，所述散热片与所述叠加基板之间留有间隔。
5.根据权利要求4所述的结构，其特征在于，所述结构还包括：金属散热器，所述金属散热器设置在所述主基板上与所述主芯片设置位置相对应，所述金属散热器与所述叠加基板之间留有间隔。
6.根据权利要求1至5任一项所述的结构，其特征在于，所述叠加芯片设置在所述叠加基板的表面或设置在所述叠加基板的内部，所述主芯片设置在所述主基板的表面或设置在所述主基板的内部。
7.根据权利要求1至6任一项所述的结构，其特征在于，所述叠加基板的单面或双面覆盖有铜箔。
8.根据权利要求1所述的结构，其特征在于，所述主基板包括：主芯片基板、电路走线、层压片、主芯片、芯片连接区域、下表面基板和设置有多个连接孔洞的上表面基板，所述电路走线设置在所述主芯片基板的上下两个表面，所述主芯片设置在所述主芯片基板的上表面上，并与所述电路走线连接，所述层压片设置在所述主芯片基板上表面的电路走线上，所述上表面基板设置在所述主芯片和所述层压片上，所述下表面基板设置在所述主芯片基板下表面的电路走线下，所述多个连接孔洞的位置与所述主芯片的输入输出接口的位置和所述电路走线的位置分别相对应，所述连接孔洞内设置有导电介质，所述导电介质与所述主芯片的输入输出接口或所述电路走线连接，所述芯片连接区域覆盖在所述连接孔洞的远离所述主芯片一侧的端口外，并与所述导电介质连接，所述芯片连接区域用于连接所述叠加基板。
9.根据权利要求1所述的结构，其特征在于，所述叠加基板包括：叠加芯片基板、电路走线、层压片、叠加芯片、外接走线、焊盘、下表面基板和设置有多个连接孔洞的上表面基板，所述电路走线设置在所述叠加芯片基板的上下两个表面，所述叠加芯片设置在所述叠加芯片基板的上表面上，并与所述电路走线连接，所述层压片设置在所述叠加芯片基板上表面的电路走线上，所述上表面基板设置在所述叠加芯片和所述层压片上，所述下表面基板设置在所述叠加芯片基板下表面的电路走线下，所述多个连接孔洞的位置与所述叠加芯片的输入输出接口的位置和所述电路走线的位置分别相对应，所述连接孔洞内设置有导电介质，所述导电介质与所述叠加芯片的输入输出接口或所述电路走线连接，所述焊盘设置在所述上表面基板的外侧面的底端，所述焊盘用于连接所述主基板，所述外接走线设置在所述上表面基板的外侧面上，所述外接走线的两端分别与所述焊盘和所述导电介质连接。
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