CN102687258A - 安装方法和安装装置 - Google Patents
安装方法和安装装置 Download PDFInfo
- Publication number
- CN102687258A CN102687258A CN2010800594438A CN201080059443A CN102687258A CN 102687258 A CN102687258 A CN 102687258A CN 2010800594438 A CN2010800594438 A CN 2010800594438A CN 201080059443 A CN201080059443 A CN 201080059443A CN 102687258 A CN102687258 A CN 102687258A
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- liquid
- hydrophilicity
- year
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 250
- 239000007788 liquid Substances 0.000 claims abstract description 31
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 99
- 238000009434 installation Methods 0.000 claims description 62
- 239000011248 coating agent Substances 0.000 claims description 15
- 238000000576 coating method Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 15
- 230000007246 mechanism Effects 0.000 claims description 14
- 230000006837 decompression Effects 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims 2
- 230000008020 evaporation Effects 0.000 claims 2
- 238000012423 maintenance Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 9
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 230000002209 hydrophobic effect Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 238000009736 wetting Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000010023 transfer printing Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000008676 import Effects 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 230000010148 water-pollination Effects 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 2
- 239000004809 Teflon Substances 0.000 description 2
- 229920006362 Teflon® Polymers 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000013011 mating Effects 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
- 230000000116 mitigating effect Effects 0.000 description 2
- 239000012188 paraffin wax Substances 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- -1 resist Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910021642 ultra pure water Inorganic materials 0.000 description 2
- 239000012498 ultrapure water Substances 0.000 description 2
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 1
- LSDPWZHWYPCBBB-UHFFFAOYSA-N Methanethiol Chemical compound SC LSDPWZHWYPCBBB-UHFFFAOYSA-N 0.000 description 1
- 241000531807 Psophiidae Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000019253 formic acid Nutrition 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 235000011187 glycerol Nutrition 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
- H01L2224/75101—Chamber
- H01L2224/75102—Vacuum chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75272—Oven
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75743—Suction holding means
- H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75753—Means for optical alignment, e.g. sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
- H01L2224/83907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
- H01L2224/95136—Aligning the plurality of semiconductor or solid-state bodies involving guiding structures, e.g. shape matching, spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
- H01L2224/95143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
- H01L2224/95146—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium by surface tension
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/17—Surface bonding means and/or assemblymeans with work feeding or handling means
- Y10T156/1702—For plural parts or plural areas of single part
- Y10T156/1744—Means bringing discrete articles into assembled relationship
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Die Bonding (AREA)
Abstract
本发明提供一种在基板上安装元件的安装方法,包括:第一亲水化处理工序,对基板的基板表面的接合元件的区域进行亲水化处理;第二亲水化处理工序,对元件(50)的元件表面进行亲水化处理;载置工序,以经过亲水化处理的元件表面朝向上方的方式将该元件载置在载置部;涂敷工序,在经过亲水化处理的元件表面涂敷液体;配置工序,以基板表面的接合元件的区域朝向下方的方式,将该基板配置在载置部的上方;和接触工序,使配置在载置部上方的基板与载置有元件的载置部彼此靠近,使液体与基板表面接触。
Description
技术领域
本发明涉及在基板上安装元件的安装方法和安装装置。
背景技术
近年来,作为半导体集成化的方法之一,三维安装技术备受瞩目。在三维安装技术中,将预先制作有集成电路的基板单片化为铸模,从单片化的铸模中挑选在单片化之前进行的合格品判断试验中确认为合格品的铸模(Known Good Die:KGD(已知合格芯片))。而且,将挑选的铸模叠层在挑选的另外的基板上,进行安装。
作为这种将铸模(以下称为“芯片”或“元件”)叠层在基板上进行安装的安装方法,例如有专利文献1中公开的芯片的安装方法。在该安装方法中,使用将芯片一并载置的一并载置用的盘。将如上所述由在合格品判断试验中作为合格品选出的多个半导体芯片等芯片构成的芯片组的各芯片,一并载置在盘的芯片载置区域。并且,在所有的芯片载置区域都载置有芯片之后,经由设置芯片载置区域的底部的供气排气孔,通过使用真空泵进行真空吸附,从而将芯片保持在盘上。之后,将吸附保持有芯片组的各芯片的盘上下反转,使水移动至堆积在接合区域上的载置基板上,解除真空吸附,使各芯片同时从盘落到载置基板上。落到基板上的各芯片利用水的表面张力进行对位,使其自动移动到载置基板上的接合区域。
现有技术文献
专利文献
专利文献1:国际公开第06/77739号手册
发明内容
发明要解决的技术问题
但是,在专利文献1所公开的方法中,在一并载置在盘上的芯片组中即便是一个芯片由于翘曲或缺陷等某些原因而发生真空吸附不良的情况下,可能导致无法将芯片准确地安装在基板上。这是因为即便是一个芯片发生真空吸附不良,也可能导致吸附各芯片的真空吸附力降低,当将盘反转时所述的芯片都落下。
作为用于防止这种芯片落下的安装方法,考虑有对每个载置各芯片的区域控制真空排气的方法。但是,如果对每个载置各芯片的区域控制真空排气,则盘的结构就会变得复杂。另外,根据产品,芯片的大小和配置、数量等有所不同,难以使用一个盘应付,有时必须准备多个盘。这样,为了防止芯片落下,盘的结构变得复杂,有时必须准备多个盘,因此存在装置成本增大的问题。
本发明是鉴于上述问题而完成的,提供一种能够不增加装置成本就能够将芯片等元件可靠地安装在基板上的安装方法和安装装置。
解决技术问题的方案
为了解决上述技术问题,在本发明中采取下述各方案。
根据本发明的一个实施例,在基板上安装元件的安装方法包括:第一亲水化处理工序,对基板的基板表面的接合元件的区域进行亲水化处理;第二亲水化处理工序,对元件的元件表面进行亲水化处理;载置工序,以经过亲水化处理的元件表面朝向上方的方式,将该元件载置在载置部;涂敷工序,在经过亲水化处理的元件表面涂敷液体;配置工序,以基板表面的接合所述元件的区域朝向下方的方式,将该基板配置在载置部的上方;和接触工序,使配置在载置部的上方的基板与载置有元件的载置部彼此靠近,使液体与基板表面接触。
另外,根据本发明的一个实施例,在基板上安装元件的安装装置包括:载置部,以经过亲水化处理的元件表面朝向上方的方式载置该元件,该元件的元件表面经过亲水化处理,经过亲水化处理的元件表面涂敷有液体;基板保持机构,设置在载置部的上方,以基板表面的接合元件的区域朝向下方的方式保持该基板,该基板的基板表面的接合元件的区域经过亲水化处理;和控制台,以基板保持机构和载置部的至少一方能够移位的方式设置,使保持有基板的基板保持机构与载置有元件的载置部彼此靠近,使液体与基板表面接触。
发明效果
根据本发明,能够不增加装置成本就可靠地在基板上安装芯片等元件。
附图说明
图1是表示第一实施方式的安装装置的结构的截面示意图。
图2是用于说明第一实施方式的安装方法的各工序的顺序的流程图。
图3A是表示第一实施方式的安装方法的各工序中的芯片和基板的状态的截面示意图(其一)。
图3B是表示第一实施方式的安装方法的各工序中的芯片和基板的状态的截面示意图(其二)。
图3C是表示第一实施方式的安装方法的各工序中的芯片和基板的状态的截面示意图(其三)。
图4是表示各芯片保持在盘的规定位置的状态的平面图。
图5是合并表示第一实施方式的安装方法的各工序中的芯片和基板的状态以及安装装置的截面示意图(其一)。
图6是合并表示第一实施方式的安装方法的各工序中的芯片和基板的状态以及安装装置的截面示意图(其二)。
图7是表示将芯片由第一基板转印(移载)到第二基板时芯片和基板的状态的截面示意图。
图8是表示在芯片相对于接合区域扭曲的状态下,由与水的表面接触的状态至自匹配地载置的状态的平面图和截面图。
图9是表示在芯片相对于接合区域在水平方向上偏离的状态下,由与水的表面接触的状态至自匹配地载置的状态的平面图和截面图。
图10是表示芯片的表面的经过亲水化处理的区域的平面图。
图11是用于说明第一实施方式的变形例的安装方法的各工序的顺序的流程图。
图12A是表示第一实施方式的变形例的安装方法的各工序中的芯片和基板的状态的截面示意图(其一)。
图12B是表示第一实施方式的变形例的安装方法的各工序中的芯片和基板的状态的截面示意图(其二)。
图12C是表示第一实施方式的变形例的安装方法的各工序中的芯片和基板的状态的截面示意图(其三)。
图13是表示第二实施方式的安装装置结构的截面示意图。
图14是用于说明第二实施方式的安装方法的各工序的顺序的流程图。
图15A是表示第二实施方式的安装方法的各工序中的芯片和基板的状态的截面示意图(其一)。
图15B是表示第二实施方式的安装方法的各工序中的芯片和基板的状态的截面示意图(其二)。
图15C是表示第二实施方式的安装方法的各工序中的芯片和基板的状态的截面示意图(其三)。
具体实施方式
下面,参照附图说明用于实施本发明的方式。
(第一实施方式)
首先,参照图1~图10,说明第一实施方式的安装方法和安装装置。
先参照图1说明安装装置。图1是表示本实施方式的安装装置结构的截面示意图。
如图1所示,安装装置100具备:处理室101;支承台侧控制台102;真空夹具侧控制臂103;支承台104;红外灯105;真空夹具106;CCD照相机107;和计算机108。另外,安装装置100还具备未图示的搬入搬出口和用于搬送基板和盘的搬送机。
处理室101以包围支承台侧控制台102、真空夹具侧控制臂103、支承台104、红外灯105和真空夹具106的方式设置,并且以能够控制其包围的内部的氛围、例如能够减压的方式设置。处理室101上连接有用于导入已控制了温度和湿度的洁净空气或氮气等气体的未图示的供给器、和能够对内部进行排气的未图示的泵,根据处理,能够控制处理室101的压力。
支承体侧控制台102能够进行在水平面(包括图1的左右方向,与图1的纸面正交的平面)内正交的两个方向(X方向和Y方向)以及与水平面正交的上下方向(Z方向)的各自的并行运动,也能够进行水平面内的转动运动(θ方向)。即,能够实现X、Y、Z、θ的四轴控制。支承台侧控制台102具有粗动模式和微动模式两种动作(控制)状态,可以根据需要切换两种模式。通常,以粗动模式进行粗略的对位,之后切换为微动模式进行精密的对位。
真空夹具侧控制臂103能够沿着在与水平面正交的上下方向(Z方向)上设置的导轨103a并行运动。另外,真空夹具侧控制臂103也可以设置成能够进行在水平面内正交的两个方向(X方向和Y方向)的并行运动、以及水平面内的转动运动(θ方向)。即,能够实现X、Y、Z、θ的四轴控制。真空夹具侧控制臂103也具有粗动模式和微动模式两种动作(控制)状态,可以根据需要切换两种模式。通常,以粗动模式进行粗略的对位,之后切换为微动模式进行精密的对位。
其中,支持台侧控制台102和真空夹具侧控制臂103相当于本发明的控制台。其中,只要支承台侧控制台102与真空夹具侧控制臂103之间的相对位置能够以X、Y、Z、θ的四轴控制即可。因此,对于X、Y、Z、θ的各轴,也可以设置成仅支承台侧控制台102和真空夹具侧控制臂103的一方能够控制。
支承台104以固定在支承台侧控制台102的上表面(搭载面)上的方式设置。支承台104以大致中央部为空洞的方式设置,在其空洞内安装有用作光源的红外灯105。
另外,支承台104的上表面侧为盘保持机构,该盘保持机构用于保持一并载置芯片的一并载置用的盘200。盘保持机构(支承台)104使用适当的卡止部件(例如螺钉、钩等)将盘200卡止,从而将盘200保持水平状态。
其中,芯片相当于本发明的元件。另外,通过盘保持机构保持在支承台上的盘相当于本发明的载置部。
盘200具有平面形状为矩形的主体部201。主体部201的上壁203的表面被分隔壁204分隔为矩形,形成多个作为用于载置芯片50的区域的芯片载置区域205。其中,盘200由能够透过由红外灯105发出的红外线的材料形成,例如由石英或能够更廉价地制造的透明的塑料等形成。
真空夹具106,以能够以水平状态保持基板10的方式,设置于保持在盘保持机构(支承台)104上的盘200的正上方的位置。真空夹具106的内部为空洞,其下表面形成有多个小孔106a,在其一端形成有供气排气孔106b。真空夹具106的下表面为保持基板10的保持面106c。在将基板10按压在保持面106c的状态下,通过供气排气孔106b排出内部空间106d的空气,达到所希望的真空状态,从而通过真空吸附将基板10固定保持在保持面106c。或者,也可以能够上下反转地设置真空夹具106。在这种情况下,以真空夹具106的保持面106c向上的状态,将基板10载置在保持面106c,使内部空间106d形成真空状态,将基板10真空吸附在保持面106c并固定保持,之后,使真空夹具106上下反转。另一方面,经由供气排气孔106b向内部空间106d导入空气解除真空状态,由此能够解除基板10的固定保持。真空夹具106由能够透过由红外灯105发出的红外线的材料(例如石英或能够更廉价地制造的透明的塑料等)形成。
其中,真空夹具106相当于本发明的基板保持机构。并且,代替真空夹具106,也可以设置通过静电吸附等方法将基板上下反转进行保持的夹具。
如图1所示,芯片50载置在盘200的芯片载置区域205,在基板10保持在真空夹具106的状态下,在保持在盘200的芯片50与保持在真空夹具106的基板10之间设置适当的间隔。另外,通过支承台侧控制台102和真空夹具侧控制臂103,能够拉近或拉远芯片50和基板10之间的间隔。
CCD照相机(传感器使用Charge-Coupled Device(电荷耦合器件)的照相机)107设置在处理室101的外侧且在支承台(盘保持机构)104的上方,在红外灯105的基本正上方的位置。CCD照相机107是用于检测从红外灯105放射出的红外线的摄像装置,将检测到的红外线转换为电信号,并传输到作为运算装置的计算机108,进行规定的数据处理。这样,利用CCD照相机107等,使保持在真空夹具106上的基板10上的多个接合区域11的位置相对于载置在盘200上的多个芯片50的位置,以规定的精度一对一地匹配。即,利用CCD照相机107等,进行保持在真空夹具106上的基板10和用于保持芯片50的盘200的对位。
其中,支承台侧控制台102(或真空夹具侧控制臂103)、红外灯105、CCD照相机107和计算机108相当于本发明中的对位机构。
为了使此时的对位容易进行,在芯片50或盘200和基板10上分别形成多个对位标记(未图示),利用CCD照相机107检测出它们的对位标记,对支承台侧控制台102的位置进行微调并固定,使得芯片50或盘200的对位标记与基板10的对位标记形成固定的位置关系。由此,能够使基板10的接合区域11的位置与载置在盘200上的芯片50的位置一对一地匹配。
接着,参照图2~图7,对于本实施方式的安装装置的安装方法进行说明。
图2是用于说明本实施方式的安装方法的各工序的顺序的流程图。图3A~图3C是表示本实施方式的安装方法的各工序中的芯片和基板的状态的截面示意图。图4是表示各芯片保持在盘的规定位置的状态的平面图。图5和图6是合并表示本实施方式的安装方法的各工序中的芯片和基板的状态以及安装装置的截面示意图。
如图2所示,本实施方式的安装方法具备:第一亲水化处理工序(步骤S11);第二亲水化处理工序(步骤S12);载置工序(步骤S13);涂敷工序(步骤S14);配置工序(步骤S15);接触工序(步骤S16);隔离工序(步骤S17);减压工序(步骤S18);加热工序(步骤S19);和反转工序(步骤S20)。
最初,进行步骤S11的第一亲水化处理工序。在步骤S11中,对于基板10的表面的接合芯片50的区域接合区域11进行亲水化处理。图3A(a)表示步骤S11中的基板的状态。
首先,最初准备基板10,该基板10具有能够将所需数量的例如由半导体芯片构成的芯片50全部以预期的布局搭载的大小,并且具有能够耐受所需数量的芯片50的重量的足够的刚性。作为基板10,例如可以使用具有足够刚性的玻璃基板、半导体晶片等。
如图3A(a)所示,在基板10的一个表面上,以与芯片50的总数相同数量(在此仅示出6个)的矩形形成有薄膜状的接合区域11。接合区域11的大小和形状分别与载置在其上的芯片50的大小和形状基本一致。
在本实施方式中,由于使用“水”作为芯片50的预粘合用材料,所以接合区域11具备亲水性。这种接合区域11,例如能够通过使用具有亲水性的二氧化硅(SiO2)膜而容易地实现。即,采用公知的方法在基板10的搭载面整体薄薄地形成SiO2膜(厚度例如为0.1μm),之后,通过采用公知的蚀刻方法选择性地除去该SiO2膜,从而容易地获得。这样,由于接合区域11具有亲水性,所以当将少量的水放到接合区域11上时,该水在接合区域11的表面整体溶合(换言之,接合区域11的表面整体润湿),形成覆盖该表面整体的薄的水膜(水滴)12。由于接合区域11均形成为岛状彼此分离,所以该水不会从接合区域11流出到外侧。
作为具有亲水性的接合区域11能够使用的材料,除了SiO2之外,还有Si3N4,但也可以使用铝和氧化铝的双层膜(Al/Al2O3)、钽和氧化钽的双层膜(Ta/Ta2O5)等。
为了更可靠地防止水从接合区域11向外侧流出而积存,优选基板10的接合芯片50一侧的表面的接合区域11以外的区域不是亲水性。例如,优选基板10本身由具有疏水性的单晶硅(Si)、氟树脂、有机硅树脂、特氟龙(注册商标)树脂、聚酰亚胺树脂、抗蚀剂、石蜡、BCB(苯并环丁烯)等形成。或者,也优选由多晶硅、无定形硅、氟树脂、有机硅树脂、特氟龙(注册商标)树脂、聚酰亚胺树脂、抗蚀剂、石蜡、BCB等覆盖形成有接合区域11的基板10的搭载面。
或者,也可以利用喷墨技术等选择性地对接合区域11进行亲水化处理。
接着,进行步骤S12的第二亲水化处理工序。在步骤S12中,进行芯片50的表面的亲水化处理。图3A(b)表示步骤S12中的芯片的状态。
如图3A(b)所示,在各芯片50的一个表面上形成具有亲水性的接合部51。接合部51,例如通过由具有亲水性SiO2膜覆盖芯片50的表面整体而容易地实现。此外,也可以在各芯片50的形成有接合部51的表面的相反面的表面,形成用于将芯片50电连接的连接部53。
在本实施方式中,作为基板10能够使用例如直径为300mm半导体晶片。作为芯片50,例如能够使用在直径为300mm的半导体晶片上形成,通过切割而得到的例如一边为5mm的正方形的半导体芯片。另外,也可以在芯片50的接合部51以及基板10的接合区域11形成例如直径为5μm的贯通电极。
接着,进行步骤S13的载置工序。在步骤S13中,以经过亲水化处理的表面朝向上方的方式将芯片50载置在盘200的芯片载置区域205。如图3A(c)表示步骤S13中的芯片状态。
在以芯片载置区域205朝向上方的方式保持的盘200的芯片载置区域205的各个上,以接合部51朝向上方的方式,载置所需数量的芯片50。这样,各芯片50载置在盘200上的规定位置。此时的状态如图3A(c)和图4所示。(在图4中,为了容易理解芯片载置区域205的结构,将部分芯片50除去。)
在如4中,为了绘图简便,表示将芯片载置区域205配置成底座状的情况。但是,在盘200上的芯片50的配置当然也可以根据所需要的盘而适当变更。另外,在本实施方式中,由于各芯片50不是真空吸附在各芯片载置区域205,所以不必在整个芯片载置区域205载置芯片50,盘200上的芯片50的配置能够任意变更。所以,即使在芯片50的配置不同的情况下,也能挪用用同一盘200,与每次制造盘的情况相比,能够削减装置成本。
各芯片载置区域205形成为与芯片50相同的矩形形状,但为了使芯片50的配置容易进行,使其比芯片50的外径稍大。因此,在芯片50与其周围的分隔壁204之间,通常出现1μm~数百μm左右的间隙。
下面,进行步骤S14的涂敷工序。在步骤S14中,在经过亲水化处理的芯片50的表面涂敷液体。图3A(d)表示步骤S14中的芯片的状态。
通过使少量的水滴至各接合部51之上,或者将芯片50整体或接合部51浸入水中再取出,从而用水将各接合部51润湿。于是,由于各接合部51具有亲水性,所以如图3A(d)所示,水在接合部51的整个表面扩展,形成有覆盖各接合部51的整个表面的薄的水的膜52。这些水的膜52由于水的张力而自然地弯曲为缓和的凸状。优选将水的量调节为例如在各接合部51之上形成如图3A(d)所示那样的水的膜52的程度。
作为本实施方式中使用的“水”,优选现有的半导体制造工序中通常使用的“超纯水”。另外,为了强化芯片50相对于基板10的接合区域11的自匹配功能,更优选添加有用于增强水的表面张力的适当的添加剂的“超纯水”。通过强化自匹配功能,芯片50相对于基板10的接合区域11的位置精度得到提高。其中,如上所述,作为具有“亲水性”的物质,适宜使用二氧化硅(SiO2)。
或者,也能够使用其他的无机或有机的液体代替“水”。例如甘油、丙酮、乙醇、SOG(Spin On Glass(旋涂玻璃))材料等液体是适合的。此时,为了形成接合区域11,需要对这种液体具有“亲液性”的材料,作为这种材料,能够列举氮化硅(Si3N4)、各种金属、硫醇、烷硫醇等。此外,也能够使用具有适度粘性的粘合剂,还能够使用蚁酸等还原性液体。
接着,进行步骤S15的配置工序。在步骤S15中,将基板10反转,使基板10的表面的接合芯片50的区域接合区域11朝向下方,将反转后的基板10配置在盘200的上方。图3B(e)表示步骤S15中的芯片和基板的状态。
图3B(e)表示已经载置有规定数量的芯片50的盘200、和接合芯片50的基板10,以基板10的接合区域11朝向下方的方式彼此相对的状态。如上所述,此时,各芯片50的与基板10相对的表面已经预先实施过亲水化处理,形成水的膜52。
如图1所示,在将基板10从下方按压至真空夹具106的保持面106c的状态下,使内部空间106d形成真空状态,将基板10真空吸附在保持面106c,并固定保持。或者,也可以在真空夹具106的保持面106c朝向上方的状态下,将基板10载置在保持面106c,使内部空间106d形成真空状态,将基板10真空吸附在保持面106c并固定保持,之后,将真空夹具106上下反转。
并且,点亮红外灯105产生红外线,使用透过盘200、基板10和真空夹具106的红外线,利用CCD照相机107拍摄芯片50与基板10的各接合区域11的重叠情况。一边利用CCD照相机107进行拍摄,一边先使支承台侧控制台102以粗动模式移动,使基板10的接合区域11的位置与盘200上的芯片50的位置基本一致。之后,将支承台侧控制台102切换成微动模式,进行微调,完成基板10的接合区域11与盘200上的芯片50的对位。
接着,进行步骤S16的接触工序。在步骤S16中,使基板10与盘200彼此接近,使水的膜52与基板10的表面的接合区域11彼此接触。图3B(f)表示步骤S16中的芯片和基板的状态。
如图3B(f)所示,在盘200与基板10相对的状态下,使盘200与基板10彼此接近。此时芯片50与基板10的最短距离例如为500μm。于是,在芯片50的表面的接合部51形成的水的膜52与基板10的表面的接合区域11接触。
由于也对基板10的表面的接合区域11实施了亲水化处理,所以在芯片50的表面的接合部51形成的水的膜52在整个接合区域11润湿并扩展。并且,芯片50移动,使得接合部51由于水的膜52的水的表面张力而向接合区域11吸引。其结果,各芯片50通过水的膜52而吸附在对应的接合区域11,形成图3B(f)所示的状态。即,在水的膜52与芯片50之间、以及水的膜52与基板10之间,引力分别发挥作用,通过水的膜52,芯片50吸附在基板10。其中,此时,芯片50和接合区域11之间的对位通过水的表面张力自匹配地进行。即,本发明的对位机构包括水。另外,各芯片50从盘200浮起,从盘200分离。
接着,进行步骤S17的隔离工序。在步骤S17中,基板10与盘200彼此远离。图5和图3B(g)表示步骤S17中的芯片和基板的状态。
如图5和图3B(g)所示,使基板10向上方移动。此时,基板10在各芯片50通过水的膜52吸附在各接合区域11的状态下,从盘200分离。
接着,进行步骤S18的减压工序。在步骤S18中,将处理室101内减压。图3C(h)表示步骤S18中的芯片和基板的状态。其中,步骤S18相当于本发明的固定工序。
当将处理室101内稍稍减压时,位于各芯片50的接合部51与对应的接合区域11之间的水慢慢蒸发。其结果,接合部51与对应的接合区域11密接,如图3C(h)所示,芯片50固定在基板10,进行基板10与芯片50之间的预接合。
接着,进行步骤S19的加热工序。在步骤S19中,对预接合有芯片50的基板10进行加热。图3C(i)表示步骤S 19中的芯片和基板的状态。其中,步骤S19也相当于本发明的固定工序。
在进行步骤S18后的状态下,当将基板10上下反转时,可能出现各芯片50从各接合区域11偏离。因此,如图3C(i)所示,从处理室101移动至例如加热炉150中进行加热。通加热至例如90~100℃附近,能够使水完全蒸发。即,水的膜52消失。由此,将预接合的芯片50和基板10之间牢固地接合。
其中,如果能够通过在真空夹具106等中设置加热器等对基板10进行加热,也可以不使基板10在加热炉中移动,在处理室101内加热。此时,也可以同时进行步骤S18和步骤S19。或者,根据芯片50接合在基板10上的接合力的大小而省略步骤S19。
此外,还可以如图6所示,通过在预接合有芯片50的基板20上按压压板,使芯片50与基板10接合。在该情况下,将盘200从支承台(盘保持机构)104除去,代替它安装压板180。然后,使真空夹具侧控制臂103下降或者使支承台侧控制台102上升,将预接合在接合区域11的芯片50按压在压板180的下表面。由此,芯片50的接合部51与接合区域11进一步密接。
接着,进行步骤S20的反转工序。在步骤S20中,将接合有芯片50的基板10反转。图3C(j)表示步骤S20中的芯片和基板的状态。
在步骤S20中,进行步骤S18和步骤S19、芯片50与基板10之间的接合完成之后,如图3C(j)所示,将基板10反转。
在芯片50与接合区域11接合之后,向真空夹具106的内部空间106d中导入空气,将基板10从真空夹具106卸下。之后,将搭载有芯片50的基板10移至与安装装置100一体设置或分别设置的进行粘结工序的装置,使用微凸电极,与支承基板或对应的半导体电路层的搭载面电·机械连接。
在本实施方式中,上述基板(以下称为“第一基板”)10也可以不是安装芯片的基板,而是用于将芯片向安装芯片的基板转印(移载)的预转印基板,即可以是载体基板。下面,使用图7,对当第一基板10是载体基板时进一步向安装芯片的基板(以下称为“第二基板”)20转印(移载)的方法进行说明。
图7是表示将芯片由第一基板转印(移载)到第二基板时芯片和基板的状态的截面示意图。
如图7(a)所示,使预接合有所需要的全部芯片50的作为载体基板的第一基板10,以相对于搭载面21朝向上方、水平保持的作为支承基板的第二基板20平行的状态下降,从而使在芯片50的表面形成的连接部53与相对应的第二基板20的连接部22一体地接触。或者,也可以使第二基板20以与第一基板10平行的状态上升,使连接部53与连接部22一体地接触。之后,采用适当的方法,将各芯片50的连接部53与第二基板20上的相对应的连接部22固定。作为适当的方法,例如能够采用夹着粘结用金属将微凸电极彼此粘结的方法。或者,能够采用不夹着粘结用金属将微凸电极彼此压接的方法,或不夹着粘结用金属将微凸电极彼此熔敷的方法。
在连接部53与连接部22的固定完成之后,施加将第一基板10从芯片50拉开的方向的力。于是,如图7(b)所示,在芯片50与第二基板20接合的状态下,能够容易地将芯片50的接合部51与第一基板10的接合区域11之间拉开。之后,在芯片50的周围的间隙配置液态或流动性的粘合剂,通过进行加热、紫外线照射等使粘合剂固化等的方法,将芯片50可靠地固定在第二基板20。
下面,参照图8~图10,对于通过本实施方式的安装方法,利用液体在芯片与基板之间自匹配地进行的对位进行说明。
图8是表示在芯片相对于接合区域扭曲的状态下,由与水的表面接触的状态至自匹配地载置的状态的平面图和截面图。图8(a)~图8(d)依次表示伴随时间经过的变化。图8(a)~图8(d)的各图中,上面是从下方观察时的平面图,下面是侧视图。图9是表示在芯片相对于接合区域在水平方向上偏离的状态下,由与水的表面接触的状态至自匹配地载置的状态的平面图和截面图。图9(a)~图9(d)依次表示伴随时间经过的变化。图9(a)~图9(d)的各图中,上排是从下方观察时的平面图,下排是侧视图。在图8和图9中,基板10仅表示接合区域11的周围部分。图10是表示芯片的表面的经过亲水化处理的区域的平面图。
在芯片50的接合部51相对于基板10的接合区域11扭曲的状态下接触时,如图8(a)所示,来自形成于接合部51的水的膜52的水润湿扩展至经过亲水化处理的接合区域11。之后,芯片50由于水的表面张力一边由图8(b)向图8(c)转动,使得设计为相同尺寸的接合部51与接合区域11基本整个面地重合,一边缩小接合部51与接合区域11的间隔地移动。然后,最终如图8(d)所示,芯片50的接合部51与基板10的接合区域11基本整个面地重合。
另一方面,在芯片50的接合部51相对于基板10的接合区域11在水平方向上偏离的状态下接触时,如图9(a)所示,来自形成于接合部51的水的膜52的水润湿扩展至经过亲水化处理的接合区域11。之后,芯片50由于水的表面张力一边由图9(b)向图9(c)在平行方向上移动,使得设计为相同尺寸的接合部51与接合区域11基本整个面地重合,一边缩小接合部51与接合区域11的间隔地移动。然后,最终如图9(d)所示,芯片50的接合部51与基板10的接合区域11基本整个面地重合。
通常,如图10(a)所示,由于将芯片50的整个表面作为接合部51进行亲水化处理,所以芯片50的周边部的表面也经过亲水化处理。但是,如图10(b)所示,也可以将芯片50a的中心部作为接合部51a,在芯片50a的周边部不进行亲水化处理,设置疏水性的区域(疏水框)51b。通过在周边部设置疏水框51b,能够利用接合部51a与疏水框51b的边界的形状进行对位。因此,在切割芯片制成单片时,即使在由于伴随切割的飞边等而导致芯片的周边部的形状偏离所期望的形状时,只要能够维持中心部的接合部51a的形状,就能够利用水以良好的精度使芯片与接合区域对位。
形成疏水框51b的方法没有限定,能够使接合部51a的表面例如为具有亲水性的SiO2膜、使疏水框51b的表面例如为Si,由此形成疏水框51b。
以上,根据本实施方式,在不真空吸附芯片而将其载置在盘上的状态下,使配置在盘的上方的基板与盘接近,使涂敷在芯片表面的水与基板表面接触,从而通过水使芯片吸附在基板上。由于芯片在通过水牢固地吸附在基板的状态下进行移动,所以在工序中无须担心芯片落下。另外,利用水使芯片与基板自匹配地对位。因此,能够不增加装置成本就将芯片等元件可靠地安装在基板上。
(第一实施方式的变形例)
接着,参照图11~图12C,对于第一实施方式的变形例的安装方法进行说明。
图11是用于说明本变形例的安装方法的各工序的顺序的流程图。图12A~图12C是表示本变形例的安装方法的各工序中的芯片和基板的状态的截面示意图。其中,在下文中,有时对前面说明过的部分标注相同的符号,省略说明(以下的实施方式也相同)。
本变形例的安装方法,在经过亲水化处理的基板的接合区域涂敷水这一点上,与第一实施方式的安装方法不同。
本变形例的安装方法能够使用第一实施方式的安装装置进行。
如图11所示,本变形例的安装方法具备:第一亲水化处理工序(步骤S31);第二亲水化处理工序(步骤S32);载置工序(步骤S33);第一涂敷工序(步骤S34);第二涂敷工序(步骤S35);配置工序(步骤S36);接触工序(步骤S37);隔离工序(步骤S38);减压工序(步骤S39);加热工序(步骤S40);和反转工序(步骤S41)。
首先,进行步骤S31~步骤S34。在步骤S31~步骤S34各工序中,能够与第一实施方式的步骤S11~步骤S14各工序相同。在此,步骤S34的第一涂敷工序与第一实施方式中的步骤S14的涂敷工序相同。即,第一涂敷工序相当于本发明的涂敷工序。另外,表示步骤S31~步骤S34各工序中的芯片和基板状态的图12A(a)~图12A(d)分别与图3A(a)~图3A(d)相同。
接着,进行步骤S35的第二涂敷工序。在步骤S35中,在经过亲水化处理的基板10的表面的作为接合芯片50的区域的接合区域11涂敷水。图12A(e)表示步骤S35中基板的状态。
通过使少量的水滴至各接合区域11之上,或者将基板10浸入水中再取出,从而用水将各接合区域11润湿。于是,由于各接合区域11具有亲水性,所以如图12A(e)所示,水在各接合区域11的整个表面扩展,形成有覆盖各接合区域11的整个表面的薄的水的膜12。这些水的膜12由于张力而自然地弯曲为缓和的凸状。优选:水的量调节为例如在各接合区域11之上形成有如图12A(e)所示那样的水的膜12的程度。
其中,步骤S35也可以在进行步骤S36之后进行。当在进行步骤S36之后进行步骤S35时,以接合区域11朝向下方的状态将基板10保持在真空夹具106,之后,也可以通过从基板10的下方吹纯水等,在各接合区域11上形成水的膜12。
下面,进行步骤S36的配置工序。步骤S36的工序能够与第一实施方式中的步骤S 15的工序相同。另外,表示步骤S36的工序中的芯片和基板状态的图12B(f)与图3B(e)相同。
接着,进行步骤S37的接触工序。在步骤S37中,使基板10与盘200彼此接近,通过水的膜12使水的膜52与基板10的表面的接触区域11接触。图12B(g)表示步骤S37中芯片和基板的状态。
如图12B(g)所示,在盘200与基板10相对的状态下,使盘200与基板10彼此接近。此时芯片50与基板10的最短距离例如为500μm。于是,在芯片50的表面的接合部51形成的水的膜52与基板10的表面的接合区域11,通过在接合区域11形成的水的膜12接触。
水的膜52和水的膜12形成一体,成为水的膜52a。芯片50移动,使得接合部51由于水的膜52a的水的表面张力而向接合区域11吸引。其结果,各芯片50通过水的膜52a而吸附在对应的接合区域11,形成图12B(g)所示的状态。即,在水的膜52a与芯片50之间、以及水的膜52a与基板10之间,引力分别发挥作用,通过水的膜52a,芯片50吸附在基板10。其中,此时,芯片50与接合区域11之间的对位通过水的表面张力自匹配地进行。并且,各芯片50从盘200浮起,从盘200分离。
下面,进行步骤S38~步骤S41。步骤S38~步骤S41的各工序分别与第一实施方式的步骤S17~步骤S20各工序相同。另外,表示步骤S38~步骤S41的各工序中的芯片和基板状态的图12B(h)~图12C(k)分别与图3B(g)~图3C(j)相同。
即使在本变形例中,也在不真空吸附芯片而载置在盘上的状态下,通过使配置在盘的上方的基板与盘接近,使涂敷在芯片表面的水与涂敷在基板表面的水接触,从而通过水使芯片吸附在基板上。由于芯片在通过水牢固地吸附在基板的状态下移动,所以在工序中无须担心芯片落下。另外,利用水使芯片与基板自匹配地对位。因此,能够不增加装置成本就将芯片等元件可靠地安装在基板上。
(第二实施方式)
下面,参照图13~图15C,对于第二实施方式的安装方法和安装装置进行说明。
本实施方式的安装装置,在使用真空吸附盘这一点上,与第一实施方式的安装装置不同。
图13是表示本实施方式的安装装置的结构的截面示意图。
本实施方式的安装装置100a具有真空吸附盘200a。
真空吸附盘200a具有平面形状为矩形的主体部201。在主体部201的内部设置有内部空间207。主体部201的上壁203的表面被分隔壁204分隔,形成多个矩形的载置区域205a。这些芯片载置区域205a位于外壁的内侧。各个芯片载置区域205a,在芯片载置区域205a的大致中心处形成有贯通上壁203到达内部空间207的小孔206。在主体部201的底部设置有与内部空间207连通的供气排气孔208,使用真空泵,通过供气排气孔208将内部空间207内的空气排出,从而能够使内部空间207达到所希望的真空状态。因此,通过真空吸附保持载置在芯片载置区域205a的芯片50,并且解除真空吸附,从而使这些芯片50从芯片载置区域205a分离。
在其他方面,本实施方式的安装装置与第一实施方式的安装装置相同。
下面,参照图14~图15C,对于本实施方式的安装装置的安装方法进行说明。
图14是用于说明本实施方式的安装方法的各工序的顺序的流程图。图15A~图15C是表示本实施方式的安装方法的各工序中的芯片和基板的状态的截面示意图。
如图14所示,本实施方式的安装方法具备:第一亲水化处理工序(步骤S51);第二亲水化处理工序(步骤S52);载置工序(步骤S53);涂敷工序(步骤S54);配置工序(步骤S55);接触工序(步骤S56);解除真空吸附工序(步骤S57);隔离工序(步骤S58);减压工序(步骤S59);加热工序(步骤S60);和反转工序(步骤S61)。其中,解除真空吸附工序相当于本发明中的解除工序。
首先,进行步骤S51和步骤S52。步骤S51和步骤S52的各工序能够与第一实施方式中的步骤S11和步骤S12相同。并且,表示步骤S51和步骤S52各工序中的芯片和基板状态的图15A(a)和图15A(b)分别与图3A(a)和图3A(b)相同。
接着,进行步骤S53的载置工序。在步骤S53中,将芯片50以经过亲水化处理的表面朝向上方的方式载置并吸附在真空吸附盘200a的芯片载置区域205a。图15A(c)表示步骤S53中芯片的状态。
在以芯片载置区域205a朝向上方的方式保持的真空吸附盘200a的芯片载置区域205a的各个中,以接合部51朝向上方的方式载置所需数量的芯片50。然后,由供气排气孔208排出内部空间207的空气,在内部空间207中形成规定的真空状态。于是,芯片50周围的空气经小孔206和内部空间207被排气,所以各芯片50吸附在相对应的芯片载置区域205a。这样,通过真空吸附,各芯片50被载置吸附在真空吸附盘200a上的规定位置。
各芯片载置区域205a形成与芯片50相同的矩形,但为了使芯片50的配置容易进行,使其比芯片50的外径稍大。因此,在芯片50与其周围的分隔壁204之间,通常出现1μm~数百μm左右的间隙。
下面,进行步骤S54和步骤S55。步骤S54和步骤S55各工序分别与第一实施方式的步骤S14和步骤S15各工序相同。表示步骤S54和步骤S55各工序中的芯片和基板状态的图15A(d)和图15B(e)分别与图3A(d)和图3A(e)相同。
接着,进行步骤S56的接触工序。在步骤S56中,使基板10与真空吸附盘200a彼此接近,使水的膜52与基板10的表面的接合区域11接触。图15B(f)表示步骤S56中的芯片和基板的状态。
如图15B(f)所示,在真空吸附盘200a与基板10相对的状态下,使真空吸附盘200a与基板10彼此接近。此时的芯片50与基板10的最短距离例如为500μm。于是,在芯片50的表面的接合部51形成的水的膜52与基板10的表面的接合区域11接触。
由于也对基板10的表面的接合区域11实施了亲水化处理,所以在芯片50的表面的接合部51形成的水的膜52在整个接合区域11润湿并扩展。但是,由于芯片50被真空吸附在真空吸附盘200a,因而不能移动。
接着,进行步骤S57的解除真空吸附工序。在步骤S57中,解除真空吸附盘的真空吸附。图15B(g)表示步骤S57中的芯片和基板的状态。
解除利用真空吸附盘200a的真空吸附进行的芯片50的保持。于是,各芯片50自由移动,由于水的膜52的水的表面张力而被吸引向接合区域11一侧。其结果,各芯片50通过水的膜52而吸附在对应的接合区域11,形成图15B(g)所示的状态。即,在水的膜52与芯片50之间、以及水的膜52与基板10之间,引力分别发挥作用,通过水的膜52,芯片50吸附在基板10。其中,此时,芯片50与接合区域11之间的对位通过水的表面张力自匹配地进行。另外,各芯片50从真空吸附盘200a浮起,从真空吸附盘200a分离。
下面,进行步骤S58~步骤S61。步骤S58~步骤S61的各工序分别与第一实施方式的步骤S17~步骤S20的各工序相同。并且,表示步骤S58~步骤S61的各工序中的芯片和基板状态的图15B(h)~图15C(k)分别与图3B(g)~图3C(j)相同。
在本实施方式中,在将芯片真空吸附在真空吸附盘上的状态下,使配置在真空吸附盘的上方的基板与真空吸附盘彼此接近,使涂敷在芯片表面的水与基板表面接触,通过解除芯片的真空吸附状态,通过水将芯片吸附在基板上。由于芯片在通过水牢固地吸附在基板的状态下移动,所以在工序中无须担心芯片落下。另外,由于在使水与基板表面接触之前不解除真空吸附,所以无须担心在基板接近真空吸附盘之前由于振动等导致芯片从真空吸附盘脱离。因此,能够不增加装置成本就将芯片等元件可靠地安装在基板上。
另外,即使在本实施方式中,也可以如第一实施方式的变形例那样,进行在基板的接合区域涂敷水的第二涂敷工序。
以上,对本发明的优选实施方式进行了说明,但是本发明不限于这些特定的实施方式,在权利要求书记载的本发明的范围内,可以进行各种变形和变更。
本申请主张基于2009年12月28日提出的日本专利申请2009-297627号的优先权,在本国际申请中引用日本专利申请2009-297627号的全部内容。
符号说明
10:基板
11:接合区域
50:芯片
51:接合部
52:水的膜
100:安装装置
101:处理室
102:支承台侧控制台
106:真空夹具
200:盘
205:芯片载置区域。
Claims (19)
1.一种安装方法,用于在基板上安装元件,该方法的特征在于,包括:
第一亲水化处理工序,对所述基板的基板表面的接合所述元件的区域进行亲水化处理;
第二亲水化处理工序,对所述元件的元件表面进行亲水化处理;
载置工序,以经过所述亲水化处理的元件表面朝向上方的方式,将所述元件载置在载置部;
涂敷工序,在经过所述亲水化处理的元件表面涂敷液体;
配置工序,以所述基板表面的接合所述元件的区域朝向下方的方式,将所述基板配置在所述载置部的上方;和
接触工序,使配置在所述载置部的上方的所述基板与载置有所述元件的所述载置部靠近,使所述液体与所述基板表面接触。
2.如权利要求1所述的安装方法,其特征在于:
在所述接触工序中,通过所述液体使所述元件吸附在所述基板。
3.如权利要求1所述的安装方法,其特征在于:
在所述接触工序中,使所述元件从所述载置部分离。
4.如权利要求1所述的安装方法,其特征在于:
在所述载置工序中,通过真空吸附将所述元件保持在所述载置部,
具备在所述接触工序之后,解除所述载置部的真空吸附、使所述元件从所述载置部分离的解除工序。
5.如权利要求1所述的安装方法,其特征在于:
在所述接触工序中,通过所述液体进行所述元件与所述基板的对位。
6.如权利要求1所述的安装方法,其特征在于:
具备在所述接触工序之后,使所述液体蒸发、使所述元件固定在所述基板上的固定工序。
7.如权利要求1所述的安装方法,其特征在于:
具备在经过所述亲水化处理的基板表面的接合所述元件的区域涂敷液体的第二涂敷工序。
8.如权利要求1所述的安装方法,其特征在于:
所述液体是水。
9.如权利要求7所述的安装方法,其特征在于:
所述液体是水。
10.一种安装装置,用于在基板上安装元件,该装置的特征在于,包括:
载置部,以经过亲水化处理的元件表面朝向上方的方式载置所述元件,所述元件的元件表面经过所述亲水化处理,经过所述亲水化处理的元件表面涂敷有液体;
基板保持机构,设置在所述载置部的上方,以所述基板的基板表面的接合所述元件的区域朝向下方的方式保持所述基板,所述基板的基板表面的接合所述元件的区域经过亲水化处理;和
控制台,以所述基板保持机构和所述载置部的至少一方能够移位的方式设置,使保持有所述基板的所述基板保持机构与载置有所述元、件的所述载置部彼此靠近,使所述液体与所述基板表面接触。
11.如权利要求10所述的安装装置,其特征在于:
具备对位机构,其用于进行保持在所述基板保持机构的所述基板与载置在所述载置部的所述元件的对位。
12.如权利要求10所述的安装装置,其特征在于:
所述控制台通过所述液体使所述元件吸附在所述基板。
13.如权利要求10所述的安装装置,其特征在于:
所述控制台使所述元件从所述载置部分离。
14.如权利要求10所述的安装装置,其特征在于:
载置部通过真空吸附保持所述元件,在所述液体与所述基板表面接触后,解除真空吸附,使所述元件分离。
15.如权利要求11所述的安装装置,其特征在于:
所述对位机构通过所述液体进行所述元件与所述基板的对位。
16.如权利要求10所述的安装装置,其特征在于:
具备以包围所述载置部和所述基板保持机构的方式设置且内部能够减压的处理室,
所述处理室,在所述液体与所述基板表面接触之后,使所述处理室内减压使所述液体蒸发,使所述元件固定在所述基板上。
17.如权利要求10所述的安装装置,其特征在于:
所述基板保持机构保持在经过所述亲水化处理的基板表面的接合所述元件的区域涂敷有液体的所述基板。
18.如权利要求10所述的安装装置,其特征在于:
所述液体是水。
19.如权利要求17所述的安装装置,其特征在于:
所述液体是水。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009297627A JP2011138902A (ja) | 2009-12-28 | 2009-12-28 | 実装方法及び実装装置 |
JP2009-297627 | 2009-12-28 | ||
PCT/JP2010/073354 WO2011081095A1 (ja) | 2009-12-28 | 2010-12-24 | 実装方法及び実装装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN102687258A true CN102687258A (zh) | 2012-09-19 |
Family
ID=44226501
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2010800594438A Pending CN102687258A (zh) | 2009-12-28 | 2010-12-24 | 安装方法和安装装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20120291950A1 (zh) |
JP (1) | JP2011138902A (zh) |
KR (1) | KR20120109586A (zh) |
CN (1) | CN102687258A (zh) |
TW (1) | TW201137994A (zh) |
WO (1) | WO2011081095A1 (zh) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103172271A (zh) * | 2013-03-15 | 2013-06-26 | 京东方科技集团股份有限公司 | 一种涂布方法 |
CN108735863A (zh) * | 2017-04-14 | 2018-11-02 | 原子能与替代能源委员会 | 发射型led显示装置制造方法 |
CN110753487A (zh) * | 2018-07-23 | 2020-02-04 | 飞传科技股份有限公司 | 芯片转移的方法及其芯片转移系统 |
CN112531079A (zh) * | 2019-09-19 | 2021-03-19 | Lg电子株式会社 | 用于自组装半导体发光二极管的装置 |
CN113764286A (zh) * | 2020-06-01 | 2021-12-07 | 天芯互联科技有限公司 | 芯片组装方法及组件 |
CN114122203A (zh) * | 2021-11-19 | 2022-03-01 | 东莞市中麒光电技术有限公司 | 一种利用液体表面张力实现芯片转移的方法 |
TWI774020B (zh) * | 2020-03-13 | 2022-08-11 | 日商鎧俠股份有限公司 | 半導體製造裝置 |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8664039B2 (en) * | 2011-10-18 | 2014-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for alignment in flip chip bonding |
CN103165541B (zh) * | 2011-12-12 | 2016-05-04 | 中芯国际集成电路制造(北京)有限公司 | 芯片与晶片的接合方法以及三维集成半导体器件 |
CN103199172B (zh) | 2012-01-10 | 2015-10-07 | 展晶科技(深圳)有限公司 | 发光二极管封装结构的制造方法 |
JP2015135835A (ja) * | 2012-03-23 | 2015-07-27 | 日本碍子株式会社 | 部品の位置合わせ装置 |
WO2013145610A1 (ja) * | 2012-03-28 | 2013-10-03 | パナソニック株式会社 | 撥水性表面および親水性裏面を有するチップを製造する方法 |
US9538582B2 (en) | 2012-07-26 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage control in the packaging of integrated circuits |
KR102072411B1 (ko) * | 2012-10-24 | 2020-03-03 | 삼성디스플레이 주식회사 | 본딩 장치 및 이를 이용하여 부품을 기판에 본딩하는 방법 |
JP6210590B2 (ja) * | 2013-09-30 | 2017-10-11 | 国立研究開発法人物質・材料研究機構 | 液中接着用基板を用いた被着物の実装方法 |
TWI567834B (zh) * | 2014-06-13 | 2017-01-21 | 新東亞微電子股份有限公司 | 指紋辨識晶片封裝模組的製造方法 |
JP6408394B2 (ja) * | 2015-02-06 | 2018-10-17 | 株式会社ジェイデバイス | 半導体装置、半導体装置の製造方法、及び製造装置 |
DE102016221281A1 (de) * | 2016-10-28 | 2018-05-03 | Osram Opto Semiconductors Gmbh | Verfahren zum transferieren von halbleiterchips und transferwerkzeug |
WO2018146880A1 (ja) | 2017-02-09 | 2018-08-16 | ボンドテック株式会社 | 部品実装システム、樹脂成形装置、部品実装方法および樹脂成形方法 |
FR3063832B1 (fr) * | 2017-03-08 | 2019-03-22 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede d'auto-assemblage de composants microelectroniques |
KR102646798B1 (ko) * | 2018-10-16 | 2024-03-13 | 주식회사 루멘스 | 엘이디 디스플레이 패널 제조를 위한 마이크로 엘이디 칩 어레이 방법 및 이에 이용되는 멀티 칩 캐리어 |
KR102294101B1 (ko) * | 2018-08-09 | 2021-08-27 | (주)라이타이저 | 디스플레이 장치의 제조 방법 |
JP7343891B2 (ja) * | 2019-06-07 | 2023-09-13 | 株式会社ブイ・テクノロジー | 貼り合わせ装置、貼り合わせ方法及び表示装置の製造方法 |
JP7357268B2 (ja) * | 2019-06-12 | 2023-10-06 | パナソニックIpマネジメント株式会社 | 部品供給装置 |
WO2021054548A1 (en) * | 2019-09-19 | 2021-03-25 | Lg Electronics Inc. | Substrate chuck for self-assembling semiconductor light-emitting diodes |
EP4071789A4 (en) * | 2019-09-19 | 2024-02-14 | LG Electronics Inc. | SUBSTRATE CHUCK FOR SELF-ASSEMBLY OF LIGHT-EMITTING SEMICONDUCTOR DIODES |
KR102323256B1 (ko) | 2019-09-19 | 2021-11-08 | 엘지전자 주식회사 | 반도체 발광소자의 자가조립 장치 |
WO2021054547A1 (ko) * | 2019-09-19 | 2021-03-25 | 엘지전자 주식회사 | 자가 조립용 칩 트레이 및 반도체 발광소자의 공급 방법 |
WO2021054550A1 (en) * | 2019-09-19 | 2021-03-25 | Lg Electronics Inc. | Device for self-assembling semiconductor light-emitting diodes |
WO2021054508A1 (ko) | 2019-09-19 | 2021-03-25 | 엘지전자 주식회사 | 반도체 발광소자의 자가조립 장치 |
KR20210134097A (ko) * | 2020-04-29 | 2021-11-09 | 삼성디스플레이 주식회사 | 표시 장치의 제조 장치 및 표시 장치의 제조 방법 |
FR3112023B1 (fr) * | 2020-06-25 | 2022-09-23 | Commissariat Energie Atomique | Procédé de transfert de puces |
WO2022249431A1 (ja) * | 2021-05-28 | 2022-12-01 | 東北マイクロテック株式会社 | 整列トレイ、整列装置、及び整列方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000133999A (ja) * | 1998-10-23 | 2000-05-12 | Tokin Corp | ワークの位置出し方法 |
CN1729561A (zh) * | 2002-12-18 | 2006-02-01 | 皇家飞利浦电子股份有限公司 | 利用小滴流体操纵物体 |
WO2006077739A1 (ja) * | 2004-12-28 | 2006-07-27 | Mitsumasa Koyanagi | 自己組織化機能を用いた集積回路装置の製造方法及び製造装置 |
CN1908563A (zh) * | 2005-08-01 | 2007-02-07 | 精工爱普生株式会社 | 减压干燥装置 |
CN101400599A (zh) * | 2006-03-10 | 2009-04-01 | 松下电器产业株式会社 | 各向异性形状部件的安装方法和安装装置、电子器件的制造方法、电子器件和显示装置 |
-
2009
- 2009-12-28 JP JP2009297627A patent/JP2011138902A/ja active Pending
-
2010
- 2010-12-24 US US13/519,237 patent/US20120291950A1/en not_active Abandoned
- 2010-12-24 CN CN2010800594438A patent/CN102687258A/zh active Pending
- 2010-12-24 WO PCT/JP2010/073354 patent/WO2011081095A1/ja active Application Filing
- 2010-12-24 KR KR1020127019775A patent/KR20120109586A/ko not_active Application Discontinuation
- 2010-12-27 TW TW099145987A patent/TW201137994A/zh unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000133999A (ja) * | 1998-10-23 | 2000-05-12 | Tokin Corp | ワークの位置出し方法 |
CN1729561A (zh) * | 2002-12-18 | 2006-02-01 | 皇家飞利浦电子股份有限公司 | 利用小滴流体操纵物体 |
WO2006077739A1 (ja) * | 2004-12-28 | 2006-07-27 | Mitsumasa Koyanagi | 自己組織化機能を用いた集積回路装置の製造方法及び製造装置 |
CN1908563A (zh) * | 2005-08-01 | 2007-02-07 | 精工爱普生株式会社 | 减压干燥装置 |
CN101400599A (zh) * | 2006-03-10 | 2009-04-01 | 松下电器产业株式会社 | 各向异性形状部件的安装方法和安装装置、电子器件的制造方法、电子器件和显示装置 |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103172271A (zh) * | 2013-03-15 | 2013-06-26 | 京东方科技集团股份有限公司 | 一种涂布方法 |
CN103172271B (zh) * | 2013-03-15 | 2015-11-25 | 京东方科技集团股份有限公司 | 一种涂布方法 |
CN108735863A (zh) * | 2017-04-14 | 2018-11-02 | 原子能与替代能源委员会 | 发射型led显示装置制造方法 |
CN108735863B (zh) * | 2017-04-14 | 2023-06-02 | 原子能与替代能源委员会 | 发射型led显示装置制造方法 |
CN110753487A (zh) * | 2018-07-23 | 2020-02-04 | 飞传科技股份有限公司 | 芯片转移的方法及其芯片转移系统 |
CN112531079A (zh) * | 2019-09-19 | 2021-03-19 | Lg电子株式会社 | 用于自组装半导体发光二极管的装置 |
CN112531079B (zh) * | 2019-09-19 | 2023-11-14 | Lg电子株式会社 | 用于自组装半导体发光二极管的装置 |
US12002691B2 (en) | 2019-09-19 | 2024-06-04 | Lg Electronics Inc. | Device for self-assembling semiconductor light-emitting diodes |
TWI774020B (zh) * | 2020-03-13 | 2022-08-11 | 日商鎧俠股份有限公司 | 半導體製造裝置 |
CN113764286A (zh) * | 2020-06-01 | 2021-12-07 | 天芯互联科技有限公司 | 芯片组装方法及组件 |
CN114122203A (zh) * | 2021-11-19 | 2022-03-01 | 东莞市中麒光电技术有限公司 | 一种利用液体表面张力实现芯片转移的方法 |
CN114122203B (zh) * | 2021-11-19 | 2023-03-14 | 东莞市中麒光电技术有限公司 | 一种利用液体表面张力实现芯片转移的方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20120109586A (ko) | 2012-10-08 |
TW201137994A (en) | 2011-11-01 |
WO2011081095A1 (ja) | 2011-07-07 |
JP2011138902A (ja) | 2011-07-14 |
US20120291950A1 (en) | 2012-11-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102687258A (zh) | 安装方法和安装装置 | |
US10804132B2 (en) | Apparatus for manufacturing semiconductor | |
US8136564B2 (en) | Attaching device and attaching apparatus for supporting plate, and attaching method for supporting plate | |
KR101357933B1 (ko) | 임프린트 장치, 임프린트 방법 및 디바이스 제조 방법 | |
TWI404196B (zh) | 固體攝像元件模組之製造方法 | |
US20130153116A1 (en) | Joint system, substrate processing system, and joint method | |
JP2001007179A (ja) | 両面粘着シートに固定された物品の剥離方法および剥離装置 | |
US20070093079A1 (en) | Imprinting method and imprinting apparatus | |
KR102668071B1 (ko) | 기판 처리 장치 및 기판 처리 방법 | |
CN105742222A (zh) | 基板吸附辅助构件和基板输送装置 | |
TWI437649B (zh) | Semiconductor device manufacturing method and electrical connection method | |
US9427913B2 (en) | Heat transfer sheet adhering apparatus and method | |
JP2007242662A (ja) | 微小チップの剥離方法及び剥離装置、微小チップの選択転写方法 | |
US8749068B2 (en) | Mounting method and mounting device | |
US20010017405A1 (en) | Solid-state image pickup device and a method of manufacturing the same | |
KR20220048018A (ko) | 접합 장치, 접합 시스템 및 접합 방법 | |
US20080016682A1 (en) | Method and apparatus for microstructure assembly | |
CN111834276A (zh) | 裸芯顶出器及包含其的裸芯拾取装置 | |
KR102398207B1 (ko) | 수지 성형 장치 및 수지 성형품의 제조 방법 | |
CN111615739A (zh) | 基板处理装置、以及基板处理方法 | |
KR102536175B1 (ko) | 다이 본딩 장치 | |
JP4926630B2 (ja) | 固体撮像装置の製造方法および製造装置、並びに貼付装置 | |
US11599028B2 (en) | Methods and systems for clamping a substrate | |
TWI499098B (zh) | 用於模塑電子器件的襯底載體 | |
KR102288925B1 (ko) | 본딩 툴 정렬 모듈 및 이를 포함하는 다이 본딩 장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120919 |