CN102664166A - CMOS (complementary metal-oxide-semiconductor) device and manufacturing method thereof - Google Patents
CMOS (complementary metal-oxide-semiconductor) device and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a CMOS (complementary metal-oxide-semiconductor) device and a manufacturing method thereof. The manufacturing method for the CMOS device includes the following steps: respectively forming a first groove and a second groove in a Si (silicon) substrate with a SiO2 (silicon dioxide) layer, wherein the first groove is in a first depth, the second groove is in a second depth which is larger than the first depth; respectively forming a Ge (germanium) layer, an etch stop layer and a III-V family semiconductor layer in the first groove and the second groove; etching the above formed structure till the Ge layer in the first groove via optional corrosion technology, and enabling the Ge layer, the SiO2 layer and the III-V family semiconductor layer to be located in the same surface; manufacturing a PMOS (p-channel metal oxide semiconductor) device on the Ge layer and an NMOS (n-channel metal oxide semiconductor) device on the III-V family semiconductor layer to complete manufacturing of the CMOS device. The substrate with mixture of grooves of Ge layer and III-V family semiconductor layer can be obtained via the optional corrosion technology and polishing technology after epitaxy. The manufacturing method for the CMOS device is simple in technology and beneficial to lower cost. Manufacturing the CMOS device on the substrate is high in speed and beneficial to improvement of performances of the CMOS device.
Description
Technical field
The invention belongs to semiconductor applications, particularly relate to a kind of cmos device and preparation method thereof.
Background technology
Metal oxide semiconductor field-effect (MOS) transistor can be divided into N raceway groove and P raceway groove two big classes; P channel silicon MOS field-effect transistor has two P+ districts on N type silicon substrate; Be called source electrode and drain electrode respectively, admittance not between the two poles of the earth is when being added with enough negative voltages (source ground) on the grid; N type silicon face under the grid presents P type inversion layer, becomes the raceway groove that connects source electrode and drain electrode.Change grid voltage and can change the electron density in the raceway groove, thereby change the resistance of raceway groove.This MOS field-effect transistor is called the P-channel enhancement type field-effect transistor.If N type surface of silicon does not add grid voltage and just has P type inversion-layer channel, add suitable bias voltage, the resistance of raceway groove is increased or reduce.Such MOS field-effect transistor is called P channel depletion type field-effect transistor.Be referred to as the PMOS transistor.
The hole mobility of P channel MOS transistor is low, thereby under the physical dimension of the MOS transistor situation equal with the operating voltage absolute value, the transistorized mutual conductance of PMOS is less than the N-channel MOS transistor.In addition, the absolute value of P channel MOS transistor threshold voltage is generally higher, requires to have higher operating voltage.The voltage swing of its power supply and polarity, with bipolar transistor---transistor-transistor logic circuit is incompatible.PMOS is big because of logic swing, and the charging and discharging process is long, and the device mutual conductance is little in addition, so operating rate is lower, after nmos circuit (seeing N channel metal-oxide-semiconductor integrated circuit) occurred, majority was replaced by nmos circuit.Just, because of the PMOS circuit technology is simple, low price, scale still adopts the PMOS circuit engineering with the small-scale digital control circuit in some.
CMOS is made up of PMOS pipe and NMOS pipe jointly, and its feature is low-power consumption.Since the gate circuit that a pair of MOS forms among the CMOS moment PMOS conducting NMOS conducting otherwise all by, more much higher than triode (BJT) efficient of linearity, so power consumption is very low.Therefore, CMOS has application very widely at semiconductor applications, also is one of most important basic building block of current semiconductor device.
Nineteen sixty-five, Gordon Moore makes the prophesy of " transistor size on the chip is along with time index increases, and the transistor on the unit are doubled in per 18 months ".Along with constantly dwindling of FET characteristic size, its device performance is increasingly high, and operating rate is also more and more faster, but its characteristic size is near the limit of Si material.Must take new technology to improve performance (new material, new construction, new technology).Wherein, introducing new channel material is main innovation way.Research shows that Ge has higher hole mobility, III-V family semi-conducting material has higher electron mobility, therefore with above-mentioned channel material and the integrated important technology approach that obtains the high-performance CMOS device that become of current semiconductor Si technology.
Therefore provide that a kind of technology is simple, low-cost, the preparation method of high performance composite material raceway groove and cmos device real belong to necessary.
Summary of the invention
The shortcoming of prior art in view of the above; The object of the present invention is to provide a kind of cmos device and preparation method thereof, a kind of technology is simple, low-cost to provide, preparation method and a kind of high performance CMOS device of high performance composite material raceway groove and cmos device.
For realizing above-mentioned purpose and other relevant purposes, the present invention provides a kind of manufacture method of cmos device, and said manufacture method comprises step at least: 1) a Si substrate is provided, and on said Si substrate, forms the SiO with first thickness
2Layer; 2) the said SiO of etching
2Layer and Si substrate form first groove that at least one reaches first degree of depth; And the said SiO of etching
2Layer and Si substrate form second groove that at least one reaches second degree of depth, and said second degree of depth are greater than said first degree of depth; 3) in said first groove and second groove, form the Ge layer, and make the upper surface of the Ge layer in said first groove be higher than the upper surface of said Si substrate, the upper surface of the Ge layer in said second groove is lower than the upper surface of said Si substrate; 4) end the layer at quarter in said Ge laminar surface formation; 5) form III-V family semiconductor layer in the said laminar surface of only carving, and make the upper surface of the III-V family semiconductor layer in said second groove be higher than the upper surface of the Ge layer in said first groove; 6) the Ge layer of the surface of the above-mentioned resulting structures of etching in exposing said first groove, and make said Ge layer, SiO
2The upper surface of layer and III-V family semiconductor layer is in same plane; 7) prepare the PMOS device in said Ge layer, prepare nmos device in said III-V family semiconductor layer.
In the manufacture method of cmos device of the present invention, adopt the selective epitaxial technology to form said Ge layer, end and carve layer and III-V family semiconductor layer.
In the manufacture method of cmos device of the present invention, the material of said III-V family semiconductor layer is the combination in any of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb or above-mentioned material.
In the manufacture method of cmos device of the present invention, said end to carve layer be Si
xGe
yC
zSn
(1-x-y-z)Layer, component are different from III-V family semiconductor layer that the second III-V family semiconductor layer, B of said III-V family semiconductor layer or SiGe layer, B or P that P mixes mix.
In the manufacture method of cmos device of the present invention; In the said step 6); Adopt interior the ending of surface to said first groove of the above-mentioned resulting structures of selective corrosion technology etching to carve layer earlier, continue the Ge layer of etching in exposing said first groove then, and make said Ge layer, SiO
2The surface of layer and III-V family semiconductor layer is in same plane.
As a preferred version of the manufacture method of cmos device of the present invention, said step 6) also comprises and adopts the chemical mechanical polishing method to said Ge layer, SiO
2Layer and the step that III-V family semiconductor layer surface is polished.
In the manufacture method of cmos device of the present invention, said step 7) comprises step at least: 7-1) said Ge layer is carried out N type conductive type ion and inject formation N trap, said III-V family semiconductor layer is carried out P-type conduction type ion inject formation P trap; 7-2) make the grid region structure in said Ge laminar surface and III-V family semiconductor layer surface; 7-3) said Ge layer being carried out P-type conduction type ion injects to form the source region and the drain region of PMOS pipe in structure both sides, said grid region; 7-4) said III-V family semiconductor layer being carried out N type conductive type ion injects to form the source region and the drain region of NMOS pipe in structure both sides, said grid region; 7-5) the source electrode and the drain electrode of preparation PMOS pipe and NMOS pipe.
The present invention also provides the cmos device of the manufacture method made of the above-mentioned any described cmos device of a kind of foundation.
As stated, cmos device of the present invention and preparation method thereof has following beneficial effect: in having SiO
2First groove that forms first degree of depth in the Si substrate of layer respectively reaches second groove greater than second degree of depth of said first degree of depth; In said first groove and second groove, form the Ge layer respectively, end and carve layer and III-V family semiconductor layer; Adopt the Ge layer in selective corrosion technology etching said structure to said first groove then, and make said Ge layer, SiO
2Layer and III-V family semiconductor layer are in same plane, on said Ge layer, make the PMOS device at last, on said III-V family semiconductor layer, make nmos device to accomplish the making of said cmos device.The present invention only need delay the substrate that can obtain to have Ge layer and III-V family semiconductor layer composite material raceway groove through selective corrosion technology and glossing outside, and technology is simple, helps reducing cost; On this substrate, prepare cmos device, have higher operating rate, help improving the performance of device.
Description of drawings
Fig. 1 ~ 2 are shown as the structural representation that the manufacture method step 1) of of the present invention kind of cmos device is appeared.
Fig. 3 ~ 4 are shown as the manufacture method step 2 of of the present invention kind of cmos device) structural representation that appeared.
Fig. 5 is shown as the structural representation that the manufacture method step 3) of of the present invention kind of cmos device is appeared.
Fig. 6 is shown as the structural representation that the manufacture method step 4) of of the present invention kind of cmos device is appeared.
Fig. 7 is shown as the structural representation that the manufacture method step 5) of of the present invention kind of cmos device is appeared.
Fig. 8 ~ 9 are shown as the structural representation that the manufacture method step 6) of of the present invention kind of cmos device is appeared.
Figure 10 is shown as the structural representation that the manufacture method step 7) of of the present invention kind of cmos device is appeared.
Structural representation that cmos cell appears after the manufacture method step 7) that Figure 11 is shown as of the present invention kind of cmos device is accomplished.
The element numbers explanation
101 Si substrates
102 SiO
2Layer
103 first grooves
104 second grooves
105 Ge layers
106 end the layer at quarter
107 III-V family semiconductor layer
108 nmos devices
109 PMOS devices
Embodiment
Below through specific instantiation execution mode of the present invention is described, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.The present invention can also implement or use through other different embodiment, and each item details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
See also Fig. 1 ~ Figure 11.Need to prove; The diagram that is provided in the present embodiment is only explained basic conception of the present invention in a schematic way; Satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and plotted when implementing according to reality; Kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also maybe be more complicated.
Shown in Fig. 1 ~ 11, the present invention provides a kind of manufacture method of cmos device, and said manufacture method comprises step at least:
Shown in Fig. 1 ~ 2, at first carry out step 1), a Si substrate 101 is provided, and on said Si substrate 101, forms SiO with first thickness
2Layer 102.Said SiO
2 Layer 102 can be through thermal oxidation process preparation, also can prepare through chemical vapour deposition technique etc.In the present embodiment, said SiO
2 Layer 102 prepares through thermal oxidation process.Said first thickness can be selected according to different demands, and its thickness range is 10 ~ 9000nm.
Shown in Fig. 3 ~ 4, carry out step 2 then), the said SiO of etching
2Layer 102 and Si substrate 101 form first groove 103 that at least one reaches first degree of depth; And the said SiO of etching
2Layer 102 and Si substrate 101 form second groove 104 that at least one reaches second degree of depth, and said second degree of depth are greater than said first degree of depth.
In the present embodiment, make litho pattern earlier, then to said SiO
2Layer 102 and Si substrate 101 carry out etching, form first groove 103 that at least one reaches first degree of depth; And then making litho pattern and the said SiO of etching
2Layer 102 and Si substrate 101 form second groove 104 that at least one reaches second degree of depth, and said second degree of depth are greater than said first degree of depth.Certainly, in other embodiment, also can etch the bigger groove of the degree of depth earlier, and then the less groove of etching depth.
As shown in Figure 5; Then carry out step 3); In said first groove 103 and second groove 104, form Ge layer 105; And the upper surface that makes the Ge layer 105 in said first groove 103 is higher than the upper surface of said Si substrate 101, and the upper surface of the Ge layer 105 in said second groove 104 is lower than the upper surface of said Si substrate 101.
In the present embodiment, adopt chemical vapour deposition technique to deposit pure Ge, because pure Ge is at SiO
2Layer is difficult to nucleating growth on 102, and can be on the Si surface can nucleating growth, thereby outer time-delay, only optionally Si substrate 101 superficial growths in first groove 103 and second groove 104 of Ge.Certainly, also can in deposition Ge, feed an amount of HCl to reduce Ge at SiO
2The nucleation rate and the speed of growth on the layer 102 are selected effect to reach better extension.
The upper surface of the Ge layer 105 in said first groove 103 is higher than the upper surface of said Si substrate 101, and the upper surface of the Ge layer 105 in said second groove 104 is lower than the upper surface of said Si substrate 101.As shown in Figure 5, the upper surface of the Ge layer 105 in said first groove 103 and the upper surface of said Si substrate 101 have one on the occasion of difference in height h
1, and the upper surface of the Ge layer 105 in the upper surface of said Si substrate 101 and said second groove 104 also have one on the occasion of difference in height h
2, wherein, h
1, h
2Concrete numerical value confirm according to the actual requirements.
As shown in Figure 6, then carry out step 4), form to end in said Ge layer 105 surface and carve layer 106.Concentrate in this enforcement, adopt the selective epitaxial method to form said ending and carve layer 106.
As shown in Figure 7, then carry out step 5), form III-V family semiconductor layers 107 in said layer 106 surface of end carving, and make the upper surface of the III-V family semiconductor layer 107 in said second groove 104 be higher than the upper surface of the Ge layer 105 in said first groove 103.In the present embodiment, adopt the selective epitaxial method to carve the layer 106 surperficial III-V family semiconductor layer 107 that forms in said ending.
The material of said III-V family semiconductor layer 107 is the combination in any of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb or above-mentioned material.In the present embodiment, the material of said III-V family semiconductor layer 107 is GaAs.The upper surface of the III-V family semiconductor layer 107 in said second groove 104 is higher than the upper surface of the Ge layer 105 in said first groove 103; As shown in Figure 7, the upper surface of the Ge layer 105 in the upper surface of said III-V family semiconductor layer 107 and said first groove 103 have one on the occasion of difference in height h
3
It is said that end to carve layer 106 be Si
xGe
yC
zSn
(1-x-y-z)Layer, component are different from III-V family semiconductor layer 107 that the second III-V family semiconductor layer 107, B of said III-V family semiconductor layer 107 or SiGe layer 105, B or P that P mixes mix.It is in the present embodiment, said that end to carve layer 106 be Si
0.6Ge
0.1C
0.2Sn
0.1Layer.
Shown in Fig. 8 ~ 9, then carry out step 6), the Ge layer 105 of the surface of the above-mentioned resulting structures of etching in exposing said first groove 103, and make said Ge layer 105, SiO
2The upper surface of layer 102 and III-V family semiconductor layer 107 is in same plane.
In the present embodiment, adopt earlier ending in surface to said first groove 103 of the above-mentioned resulting structures of selective corrosion technology etching to carve layer 106, continue the Ge layer 105 of etching in exposing said first groove 103 then, and make said Ge layer 105, SiO
2The surface of layer 102 and III-V family semiconductor layer 107 is in same plane.After above-mentioned steps is accomplished, also comprise and adopt the chemical mechanical polishing method said Ge layer 105, SiO
2 Layer 102 and the step that III-polishes on V family semiconductor layer 107 surfaces are so that said Ge layer 105, SiO
2The surfacing of layer 102 and III-V family semiconductor layer 107 is in order to the carrying out of subsequent technique.The present invention only need can obtain Ge layer 105 and III-V family semiconductor layer 107 raceway groove as device through selective corrosion and polishing, and technology is simple, can practice thrift the fabrication cycle and the cost of manufacture of device widely.
Shown in Figure 10 ~ 11, carry out step 7) at last, in said Ge layer 105 preparation PMOS device 109, in said III-V family semiconductor layer 107 preparation nmos devices 108.
In the present embodiment, said step 7) comprises step at least:
7-1) said Ge layer 105 is carried out N type conductive type ion and inject formation N trap, said III-V family semiconductor layer 107 is carried out P-type conduction type ion inject formation P trap;
7-2) in said Ge layer 105 surface and III-V family semiconductor layer 107 surfaces make the grid region structures; In the present embodiment, said grid region structure comprises the grid oxide layer that is incorporated into Ge layer 105 or III-V family semiconductor layer 107, is incorporated into the polysilicon gate of said grid oxide layer, and the protection sidewall structure that is made in said grid oxide layer and polysilicon gate sidewall.
7-3) said Ge layer 105 being carried out P-type conduction type ion injects to form the source region and the drain region of PMOS pipe in structure both sides, said grid region; In the present embodiment, make mask and shelter from III-V family semiconductor layer 107 zones, adopt self-registered technology that said Ge layer 105 is carried out P-type conduction type ion then and inject to form the source region and the drain region of PMOS pipe in structure both sides, said grid region.
7-4) said III-V family semiconductor layer 107 is carried out N type conductive type ion and inject source region and drain region with the two-layer formation of structure NMOS pipe in said grid region; In the present embodiment, make mask and shelter from Ge layer 105 zone, adopt self-registered technology that said III-V family semiconductor layer 107 is carried out N type conductive type ion then and inject to form the source region and the drain region of NMOS pipe in structure both sides, said grid region.
7-5) the source electrode and the drain electrode of preparation PMOS pipe and NMOS pipe have been accomplished the making of said cmos device.
See also Figure 10 and Figure 11; The present invention also provides the cmos device of the manufacture method made of the above-mentioned cmos device of a kind of foundation; Said cmos device is included in the NMOS that III-V family semiconductor layer 107 is made at least and manages and manage at the PMOS of Ge layer 105 making; Its structure is shown in figure 10, and its local structure of amplifying is shown in figure 11.Because III-semi-conductive electron transfer rate of V family is higher; And the hole mobility of Ge is higher; The present invention manages at the PMOS that the NMOS that III-V family semiconductor layer 107 is made manages and makes at Ge layer 105, thereby cmos device of the present invention has operating rate faster.
In sum, cmos device of the present invention and preparation method thereof is in having SiO
2Form first groove 103 of first degree of depth in layer 102 the Si substrate 101 respectively and greater than second groove 104 of second degree of depth of said first degree of depth; In said first groove 103 and second groove 104, form Ge layer 105 respectively, end and carve layer 106 and III-V family semiconductor layer 107; Adopt the Ge layer 105 in selective corrosion technology etching said structure to said first groove 103 then, and make said Ge layer 105, SiO
2Layer 102 and III-V family semiconductor layer 107 are in same plane, on said Ge layer 105, make PMOS device 109 at last, on said III-V family semiconductor layer 107, make nmos device 108 to accomplish the making of said cmos device.The present invention only need delay the substrate that can obtain to have Ge layer 105 and III-V family semiconductor layer 107 composite material raceway grooves through selective corrosion technology and glossing outside, and technology is simple, helps reducing cost; On this substrate, prepare cmos device, have higher operating rate, help improving the performance of device.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any be familiar with this technological personage all can be under spirit of the present invention and category, the foregoing description is modified or is changed.Therefore, have common knowledge the knowledgeable in the affiliated such as technical field, must contain by claim of the present invention not breaking away from all equivalence modifications of being accomplished under disclosed spirit and the technological thought or changing.
Claims (8)
1. the manufacture method of a cmos device is characterized in that, said manufacture method comprises step at least:
1) a Si substrate is provided, and on said Si substrate, forms SiO with first thickness
2Layer;
2) the said SiO of etching
2Layer and Si substrate form first groove that at least one reaches first degree of depth; And the said SiO of etching
2Layer and Si substrate form second groove that at least one reaches second degree of depth, and said second degree of depth are greater than said first degree of depth;
3) in said first groove and second groove, form the Ge layer, and make the upper surface of the Ge layer in said first groove be higher than the upper surface of said Si substrate, the upper surface of the Ge layer in said second groove is lower than the upper surface of said Si substrate;
4) end the layer at quarter in said Ge laminar surface formation;
5) form III-V family semiconductor layer in the said laminar surface of only carving, and make the upper surface of the III-V family semiconductor layer in said second groove be higher than the upper surface of the Ge layer in said first groove;
6) the Ge layer of the surface of the above-mentioned resulting structures of etching in exposing said first groove, and make said Ge layer, SiO
2The upper surface of layer and III-V family semiconductor layer is in same plane;
7) prepare the PMOS device in said Ge layer, prepare nmos device in said III-V family semiconductor layer.
2. the manufacture method of cmos device according to claim 1 is characterized in that: adopt the selective epitaxial technology to form said Ge layer, end and carve layer and III-V family semiconductor layer.
3. the manufacture method of cmos device according to claim 1, it is characterized in that: the material of said III-V family semiconductor layer is the combination in any of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb or above-mentioned material.
4. the manufacture method of cmos device according to claim 3 is characterized in that: said ending carved layer and is Si
xGe
yC
zSn
(1-x-y-z)Layer, component are different from III-V family semiconductor layer that the second III-V family semiconductor layer, B of said III-V family semiconductor layer or SiGe layer, B or P that P mixes mix.
5. the manufacture method of cmos device according to claim 1; It is characterized in that: in the said step 6); Adopt interior the ending of surface to said first groove of the above-mentioned resulting structures of selective corrosion technology etching to carve layer earlier; Continue the Ge layer of etching in exposing said first groove then, and make said Ge layer, SiO
2The surface of layer and III-V family semiconductor layer is in same plane.
6. the manufacture method of cmos device according to claim 1 is characterized in that: said step 6) also comprises and adopts the chemical mechanical polishing method to said Ge layer, SiO
2Layer and the step that III-V family semiconductor layer surface is polished.
7. the manufacture method of cmos device according to claim 1, it is characterized in that: said step 7) comprises step at least:
7-1) said Ge layer is carried out N type conductive type ion and inject formation N trap, said III-V family semiconductor layer is carried out P-type conduction type ion inject formation P trap;
7-2) make the grid region structure in said Ge laminar surface and III-V family semiconductor layer surface;
7-3) said Ge layer being carried out P-type conduction type ion injects to form the source region and the drain region of PMOS pipe in structure both sides, said grid region;
7-4) said III-V family semiconductor layer being carried out N type conductive type ion injects to form the source region and the drain region of NMOS pipe in structure both sides, said grid region;
7-5) the source electrode and the drain electrode of preparation PMOS pipe and NMOS pipe.
8. cmos device according to the manufacture method made of any described cmos device of claim 1 ~ 7.
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| CN111785616A (en) * | 2019-04-04 | 2020-10-16 | 上海新微技术研发中心有限公司 | Preparation method of selective area germanium-lead alloy based on ion implantation and annealing method |
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| CN111785616B (en) * | 2019-04-04 | 2023-06-23 | 上海新微技术研发中心有限公司 | Preparation method of selected-area germanium-lead alloy based on ion implantation and annealing method |
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